JPH06258665A - Production of liquid crystal panel - Google Patents

Abstract

PURPOSE:To protect thin-film transistors(TFTs) and wirings against electrostatic breakdown. CONSTITUTION:An electrostatic protective element SP is formed by arranging a drain first conductive film d1 and drain second conductive film d2 via an alumina film AOF and an insulating film GI on a gate second conductive film (A1) g2 drawn out of a common date wiring. These films d1, d2 are connected to the gate fist conductive film (Cr) g1 and transparent conductive film TC drawn out of the common drain wiring. The structure of the part where TFT and the wiring intersect is a structure where the alumina film AOF, the insulating film GI and an i type amorphous silicon film AS exsist between the two conductive films and, therefore, the dielectric strength is higher than that of the electrostatic protective element SP.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal panel, and more particularly to a method for manufacturing an active matrix type liquid crystal panel using thin film transistors and the like.

[0002]

2. Description of the Related Art An active matrix type liquid crystal panel is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal display device. Then it is becoming an indispensable technology. A typical example of the switching element is a thin film transistor (TFT).

An active matrix substrate (pixel electrode substrate) using a thin film transistor is one in which a gate wiring and a drain wiring are cross-arranged on a glass substrate and a thin film transistor is formed in the vicinity of the crossing, but the substrate is insulated. Since it is a glass substrate with high properties, it is extremely easy to be charged, and since the thin film transistor and the wiring intersection have a structure in which a thin insulating film is sandwiched between two conductive films, it is easy to cause electrostatic breakdown. Has become. Therefore, it is necessary to take some electrostatic protection measures on the active matrix substrate.

FIG. 7 is a plan view showing the structure of a conventional electrostatic protection element, and FIG. 8 is a sectional view taken along the line CC of FIG. 7 and 8, SUB is a transparent glass substrate, g1 is a first gate conductive film made of chromium, g2 is a second gate conductive film made of aluminum, and AOF is a second gate conductive film g.
Alumina film formed on the surface of No. 2 by anodization, T
C is a transparent conductive film made of ITO or the like, GI is an insulating film, AS
Is an i-type (intrinsic) amorphous silicon film, d1 is a drain first conductive film made of chromium, d2 is a drain second conductive film made of aluminum, and G is a discharge gap formed as an electrostatic protection element. .

The conductive film in the illustrated portion is formed in a region outside the cutting line of the glass substrate and constitutes a common gate wiring and a common drain wiring, respectively.
Then, on these conductive films, gate wirings drawn from the pixel region (display portion) where the thin film transistors are formed,
The drain wirings are commonly connected. In this active matrix substrate, when the substrate is charged by transportation or mounting on a manufacturing apparatus, it is attempted to prevent static electricity from entering the pixel region by discharging through the discharge gap.

[0006]

The above-mentioned conventional electrostatic protection means discharges static electricity by means of the discharge gap. However, in the current liquid crystal panel manufacturing process, it is 10 μm.
Therefore, it is difficult to form the discharge gap with a gap of 10 μm or less. On the other hand, the nitride film serving as the gate insulating film in the pixel region is required to be thinner in order to improve the characteristics of the transistor, and particularly to increase gm. Therefore, the electrostatic breakdown voltage of the discharge gap as a protective element is
The withstand voltage of the thin film transistor or the wiring to be protected becomes higher, and it is becoming difficult to sufficiently protect the thin film transistor or the wiring from electrostatic breakdown.

Therefore, it is an object of the present invention to set the pixel region statically without being related to the thickness of the gate insulating film or the interlayer insulating film at the thin film transistor or the wiring crossing portion, or to the design rule. A protective element having a withstand voltage lower than the withstand voltage can be formed, and thus a thin film transistor and a wiring can be effectively protected from electrostatic breakdown so that a liquid crystal panel can be manufactured with a high yield.

[0008]

In order to achieve the above object, according to the present invention, a plurality of gate wirings, a plurality of drain wirings and a plurality of thin film transistors are cut inside a cutting line of a first glass substrate. Forming a common gate wiring to which the plurality of gate wirings are connected outside the line, a common drain wiring to which the plurality of drain wirings are connected, and an electrostatic protection element provided between the common gate wiring and the common drain wiring Then, a step of manufacturing an active matrix substrate, a step of forming a common electrode made of a transparent conductive film on a second glass substrate to manufacture a common electrode substrate, the active matrix substrate and the common electrode substrate. And a liquid crystal are sealed in the gap by adhering to each other with a narrow gap, and a step of cutting the first glass substrate along a cutting line.
A method of manufacturing a liquid crystal panel, wherein the electrostatic protection element is an element having a MIM (metal-insulator-metal) structure having a breakdown voltage lower than an electrostatic breakdown voltage of the thin film transistor. , Are provided.

[0009]

According to the present invention, between the common drain wiring and the common source wiring, the electrostatic protection element of the MIM structure having a withstand voltage lower than that of the thin film transistor is provided. Thus, the electrostatic breakdown voltage of the thin film transistor is determined by the gate insulating film and the intrinsic amorphous silicon film which is an active layer formed thereon. Therefore, the MIM structure having the gate insulating film as an insulating layer is selected as the electrostatic protection element.

As a gate insulating film, alumina (Al2O3
(A) and (b) of FIG. 6 show the insulating structures of the electrostatic protection element and the thin film transistor according to the present invention when a composite film of a film) and a silicon nitride film (SiN) is used.
Assuming that the alumina film has a thickness of 1500Å, the silicon nitride film has a thickness of 2000Å, and the amorphous silicon film has a thickness of 2000Å, the protective element has a withstand voltage of about 300V and the thin film transistor has a withstand voltage of about 350V. . The situation is illustrated in FIG. 6 (c).
Incidentally, the breakdown voltage of the alumina film alone was about 130 V, and that of the protective element (discharge gap) of the conventional structure was about 400 V (in the case of the 10 μm rule).

Therefore, if the electrostatic protection element having this structure is arranged between the common drain wiring and the common source wiring,
When the substrate is charged, the protective element is destroyed faster than the thin film transistor is destroyed, so that the thin film transistor is not electrostatically destroyed. The same can be said for wiring intersections having the same insulating structure as thin film transistors.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. Prior to describing the electrostatic protection element having the characteristics of the present invention, the wiring structure of the thin film transistor and the active matrix substrate in this embodiment will be described. In the active matrix substrate of this embodiment, the pixel electrode is formed in the lower layer of the drain wiring,
It has a so-called BI (Buried ITO) structure.

FIG. 3 shows an active system to which the present invention is applied.
FIG. 4 is a plan view of one pixel portion of a matrix type liquid crystal panel.
FIG. 4 is a sectional view taken along the line BB of FIG. As shown in FIG. 3, each pixel has two adjacent gate lines GL.
And in the area where the two adjacent drain wirings DL intersect (in the area surrounded by the four signal lines).
Each pixel has a thin film transistor TFT and a pixel electrode PE
Composed of.

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain decreases, and when the bias is zero, the channel resistance increases. The thin film transistor TFT includes a gate electrode GT, a gate insulating film GI, i.
Amorphous silicon (Si) film AS and phosphorus (P) of a type (in the present embodiment, “i-type” means “conductivity type determining impurities are not intentionally doped”) are highly doped. It has an n + type amorphous silicon film nAS, a source electrode SD1 and a drain electrode SD2. In addition,
The source and drain are originally determined by the bias polarity between them, and since the polarity is reversed during operation in the circuit of this liquid crystal panel, the source and drain are switched during operation. However, for convenience of explanation, the electrode connected to the pixel electrode PE will be referred to as the source electrode, and the other electrode will be referred to as the drain electrode.

Gate electrode GT of thin film transistor TFT
Is formed of a metal film continuously and integrally formed with the gate line GL, branches in a T-shape in the vertical direction from the gate line GL, and protrudes beyond the active region of the thin film transistor TFT. In this embodiment, the gate electrode G
T is formed of a single-layer gate second conductive film g2.
As the gate second conductive film g2, for example, an aluminum (Al) film formed by sputtering is used, and A is formed on the aluminum film.
An alumina film AOF which is an anodized film of 1 is provided. The gate line GL is the second conductive film g of the gate electrode GT.
The second conductive film g2 is formed in the same manufacturing process as that of No. 2. Further, an alumina film AOF which is an anodized film of Al is also provided on the gate line GL.

The first gate conductive film g1 made of chromium (Cr) or the like formed prior to the formation of the second gate conductive film g2 is shown in FIGS. 3 and 4 in this embodiment. (In the present embodiment, the gate first conductive film g1 has a gate connection terminal, a drain connection terminal, a common gate line, a common drain line, etc. together with the transparent conductive film TC in the outside of the pixel region. Used to form).

The pixel electrode PE is formed of a transparent conductive film TC, and the source electrode SD of the thin film transistor TFT1.
Connected to 1. This transparent conductive film TC is formed of ITO (In) having a thickness of 1000 to 2000 Å (in this embodiment, a film thickness of about 1400 Å) by a sputtering method.
dium-Tin-Oxide) film. The insulating film GI is used as a gate insulating film for applying an electric field to the amorphous silicon film AS together with the gate electrode GT in the thin film transistor TFT, and is also used as an interlayer insulating film on the gate wiring GL. The insulating film GI covers the entire pixel region (AR) except the pixel electrode PE (see FIG. 5).

The insulating film GI is, for example, plasma CV.
The silicon nitride film formed in D is selected, 1200-2
It is formed to a thickness of 700Å (in this embodiment, about 2000Å). The i-type amorphous silicon film AS is formed so as to be an independent island region for each thin film transistor TFT, and has a thickness of 200 to 2200Å (20 in this embodiment).
It is formed to a film thickness of about 00Å).

NAS is an n + -type amorphous silicon film doped with phosphorus (P) for ohmic contact, the i-type semiconductor layer AS is present on the lower side, and the conductive layer d is on the upper side.
It is left only where 2 (d3) exists. The i-type amorphous silicon film AS is also provided between both the intersections (crossover portions) of the gate wiring GL and the drain wiring DL. The i-type amorphous silicon film AS at the intersection reduces the short circuit between the gate wiring GL and the drain wiring DL at the intersection and improves the breakdown voltage between them.

Each of the source electrode SD1 and the drain electrode SD2 is composed of a drain first conductive film d1 in contact with the n + type amorphous silicon film nAS and a drain second conductive film d2 formed thereon. Chromium (Cr) formed by sputtering on the drain first conductive film d1
Using a membrane, a thickness of 500 to 1000 Å (in this embodiment,
It is formed to about 600Å). Since the stress of the Cr film increases as the film thickness increases, it is desirable to form the Cr film within a range of about 2000 Å. Cr
The film is used for the purpose of improving adhesion to the n + type amorphous silicon film nAS and preventing Al of the second drain conductive film d2 from diffusing into the n + type amorphous silicon film nAS (so-called barrier layer). To be done. As the drain first conductive film d1, in addition to the Cr film, refractory metal (Mo,
Ti, Ta, W) film, refractory metal silicide (MoS
i, TiSi, TaSi, WSi) film may be used.

The drain second conductive film d2 has a thickness of 3000 to 5000 Å by sputtering (4 in this embodiment).
It is an Al film having a thickness of about 000Å). Al film is C
The stress is smaller than that of the r film, the film can be formed to have a large film thickness, the resistance values of the source electrode SD1, the drain electrode SD2, and the drain wiring DL can be reduced, and the gate electrode GT and the i-type amorphous film can be formed. It has a function of overcoming a step due to the silicon film AS without causing step breaks (improving the step coverage).

After patterning the drain first conductive film d1 and the drain second conductive film d2 with the same mask pattern,
The exposed n + -type amorphous silicon film nAS is removed by using the same mask or by using the first conductive film d1 and the second conductive film d2 as masks. That is, the n + -type amorphous silicon film nAS left on the i-type amorphous silicon film AS is the first conductive film d1 and the second conductive film d.
The portion other than the portion covered with 2 is removed by the self-aligning method. At this time, the n + -type amorphous silicon film nAS is etched so that the entire thickness thereof is removed, so that the surface of the i-type amorphous silicon film AS is also slightly etched, but the degree is controlled by the etching time. do it.

The drain wiring DL is connected to the source electrode SD1,
A drain first conductive film d1 in the same layer as the drain electrode SD2,
It is composed of the drain second conductive film d2. Next, FIG.
The overall configuration including the peripheral portion of the active matrix substrate will be described with reference to FIG. FIG. 5 shows a state before cutting the transparent glass substrate SUB, and CT indicates a position where the transparent glass substrate SUB should be cut.

A protective film PSV is provided on the pixel area AR in which the thin film transistor, the pixel electrode and the like are formed. The protective film PSV is a film formed mainly for protecting the thin film transistor from moisture and the like, and a film having high transparency and good moisture resistance is used. For example, a silicon oxide film or a silicon nitride film having a film thickness of about 1 μm formed by the plasma CVD method is used.

As shown in FIG. 5, the protective film PSV is formed so as to cover the entire pixel region AR, and is removed in the peripheral portion so as to expose the drain connection terminal DTM and the gate connection terminal GTM. The gate line GL drawn from the pixel region AR is connected to the gate connection terminal GTM arranged along the cutting line CT. Each gate connection terminal GTM is drawn out beyond the cutting line CT and short-circuited by the common gate wiring SHg. Similarly, the pixel area A
The drain wiring DL drawn from R is connected to a drain connection terminal DTM arranged along the cutting line CT,
Each drain connection terminal DTM drawn out beyond the cutting line
Are short-circuited by the common drain wiring SHd.

These gate wiring GL and gate connection terminal G
TM, drain wiring DL, drain connection terminal DTM,
It is composed of a two-layer film of a gate first conductive film g1 made of chromium or the like and a transparent conductive film TC made of ITO. In the upper left corner of the transparent glass substrate SUB, the electrostatic protection element SP connected to the common gate wiring SHg and the common drain wiring SHd is arranged.

FIG. 1 is a plan view showing a region where the electrostatic protection element of this embodiment is formed, and FIG. 2 is a sectional view taken along the line AA. As shown in FIGS. 1 and 2, the gate-side electrode of the electrostatic protection element SP is composed of the gate second conductive film g2, and the surface thereof is covered with the alumina film AOF. This electrode is connected to the common gate line via the second gate conductive film g2.

On the other hand, the common drain wiring SHd is extended to the electrostatic protection element portion as it is as a two-layer film of the gate first conductive film g1 and the transparent conductive film TC. A part of the extension of the common drain wiring SHd is covered with the insulating film GI together with the gate side electrode of the electrostatic protection element. The electrode on the drain side of the electrostatic protection element SP is divided into five and is provided on the insulating film GI, and the ends thereof are commonly connected to the extension of the common drain wiring SHd. That is, in this embodiment, five elementary electrostatic protection elements are connected in parallel.

Since the electrostatic protection element SP is an element of the MIM structure having the alumina film AOF and the insulating film GI as the insulating layers, the alumina film AOF, the insulating films GI and i are provided between the conductive layers.
The breakdown voltage is lower than that of the thin film transistor having the amorphous silicon film AS and the cross wiring portion. Therefore, when invading static electricity, it can be destroyed earlier than the elements and wirings in the pixel area to protect the pixel area.

When the electrostatic protection element is short-circuited, the laser repair area LRA can be irradiated with a laser to cut the short-circuited portion. Each element electrostatic protection device is laser repair area L
When cut by RA, the remaining elemental electrostatic protection element can be used to continue the protection. In FIG. 2, the amorphous silicon film AS on the insulating film GI is
The insulating film GI is left in order to process the end portion into a tapered shape at the time of patterning, but the illustration is omitted in FIG. 1 for clarity.

The active matrix substrate having the above-mentioned structure is superposed on a separately manufactured common electrode substrate having a transparent common electrode, a color filter, a light shielding film (black matrix) and the like, and is bonded with a narrow gap. It After that, liquid crystal is injected into the gap, the injection port is sealed, and then the transparent glass substrate is cut along a cutting line to be assembled into a liquid crystal panel.

The optimum embodiment has been described above.
Several variations on this embodiment are possible within the scope of the invention. For example, a conductive film, an insulating film, a transparent conductive film, or the like can be formed using a material other than those in Examples, and B can be used to form an active matrix substrate.
It can be formed by conventional methods without using the I process, but these are not excluded from the invention.

The present invention can be applied not only to the direct-view type liquid crystal display device but also to other liquid crystal panel devices such as a liquid crystal valve.

[0034]

As described above, according to the present invention, the MIM type electrostatic protection element having a withstand voltage lower than that of the elements and wirings in the pixel region is provided between the common gate wiring and the common drain wiring. Therefore, the pixel region can be surely protected from electrostatic breakdown, and the manufacturing yield of the liquid crystal panel can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a formation region of an electrostatic protection element used in an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA of FIG.

FIG. 3 is a plan view of a pixel portion of an active matrix substrate to which the present invention is applied.

4 is a cross-sectional view taken along the line BB of FIG.

FIG. 5 is a plan view showing a configuration of a peripheral portion of an active matrix substrate to which the present invention is applied.

6A and 6B are a sectional view and a characteristic view for explaining the operation of the present invention.

FIG. 7 is a plan view showing a formation region of an electrostatic protection element used in a conventional example.

8 is a cross-sectional view taken along the line CC of FIG.

[Explanation of symbols]

 SUB Transparent glass substrate GL Gate line DL Drain line GI Insulating film GT Gate electrode AS i type amorphous silicon film nAS n + type amorphous silicon film SD1 Source electrode SD2 Drain electrode PSV Protective film TFT Thin film transistor AOF Alumina film PE Pixel electrode g1 Gate 1st Conductive film g2 gate second conductive film d1 drain first conductive film d2 drain second conductive film GTM gate connection terminal DTM drain connection terminal TC transparent conductive film G discharge gap SP electrostatic protection device SHg common gate wiring SHd common drain wiring CT cutting Line AR Pixel area LRA Laser repair area.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Norio Tsukii 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Device Division (72) Hideaki Yamamoto 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronics Device Division

Claims (1)

[Claims] 1. A plurality of gate wirings, a plurality of drain wirings, and a plurality of thin film transistors inside a cutting line of a first glass substrate, and a common gate wiring to which the plurality of gate wirings are connected outside the cutting line, A step of forming an active matrix substrate by forming a common drain wiring to which a plurality of drain wirings are connected and a common gate wiring and an electrostatic protection element provided between the common drain wiring; and a second glass substrate A step of forming a common electrode made of a transparent conductive film thereon to manufacture a common electrode substrate; and a step of adhering the active matrix substrate and the common electrode substrate with a narrow gap and enclosing a liquid crystal in the gap. And a step of cutting the first glass substrate along a cutting line, wherein the electrostatic protection element includes the thin film transistor. A method of manufacturing a liquid crystal panel, which is an element having a MIM (metal-insulator-metal) structure having a breakdown voltage lower than the electrostatic breakdown voltage of the star.