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JP2695424B2 - Liquid crystal display - Google Patents

Liquid crystal display

Info

Publication number
JP2695424B2
JP2695424B2 JP5340188A JP5340188A JP2695424B2 JP 2695424 B2 JP2695424 B2 JP 2695424B2 JP 5340188 A JP5340188 A JP 5340188A JP 5340188 A JP5340188 A JP 5340188A JP 2695424 B2 JP2695424 B2 JP 2695424B2
Authority
JP
Japan
Prior art keywords
wiring
gate
liquid crystal
electrode
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5340188A
Other languages
Japanese (ja)
Other versions
JPH01227128A (en
Inventor
直紀 中川
弘和 阪本
誠 大谷
太郎 前島
昌宏 羽山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5340188A priority Critical patent/JP2695424B2/en
Publication of JPH01227128A publication Critical patent/JPH01227128A/en
Application granted granted Critical
Publication of JP2695424B2 publication Critical patent/JP2695424B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は液晶表示装置に関し、特にTFTアレイを用
いた液晶表示装置において、大面積化及び高解像度化を
行う際のゲート電極配線の断線欠陥、及びゲート電極配
線とソース電極配線との交差部分における短絡欠陥の低
減に関するものである。
Description: TECHNICAL FIELD The present invention relates to a liquid crystal display device, and in particular, in a liquid crystal display device using a TFT array, a disconnection defect of a gate electrode wiring when an area and a resolution are increased. , And reduction of short-circuit defects at the intersection of the gate electrode wiring and the source electrode wiring.

〔従来の技術〕 液晶表示装置は通常2枚の対向基板の間に液晶などの
表示材料が挟持され、この表示材料に電圧を印加する方
法で構成される。この際、少なくとも一方の基板にマト
リックス状に配列した画素電極を設け、これらの画素を
選択的に動作させるために各画素毎にFET(電界効果ト
ランジスタ)等の非線形特性を有する能動素子を設けて
いる。
[Prior Art] A liquid crystal display device is usually constructed by a method in which a display material such as liquid crystal is sandwiched between two opposed substrates and a voltage is applied to the display material. At this time, pixel electrodes arranged in a matrix are provided on at least one substrate, and an active element having a non-linear characteristic such as a FET (field effect transistor) is provided for each pixel in order to selectively operate these pixels. There is.

従来のこの種の装置としては、第5図,第6図,第7
図に示すようなものがあり、第5図は従来法により形成
した液晶表示装置のTFTアレイの部分平面図、第6図及
び第7図はそれぞれ第5図のD−D′部及びE−E′部
の断面図である。図において、1は透明絶縁基板、2は
ゲート電極及び配線、3はソース電極及び配線、4はド
レイン電極、5は画素電極、6はゲート絶縁膜、7は半
導体層、8はパッシベーション膜、9は遮光膜、10はド
レイン電極と画素電極とのコンタクト部、11は画素電極
と同時形成したゲート配線である。
Conventional devices of this type are shown in FIGS. 5, 6, and 7.
FIG. 5 is a partial plan view of a TFT array of a liquid crystal display device formed by a conventional method, and FIGS. 6 and 7 are DD ′ section and E- section in FIG. 5, respectively. It is sectional drawing of E'part. In the figure, 1 is a transparent insulating substrate, 2 is a gate electrode and wiring, 3 is a source electrode and wiring, 4 is a drain electrode, 5 is a pixel electrode, 6 is a gate insulating film, 7 is a semiconductor layer, 8 is a passivation film, 9 Is a light-shielding film, 10 is a contact portion between the drain electrode and the pixel electrode, and 11 is a gate wiring formed simultaneously with the pixel electrode.

一般に、液晶表示装置等に用いられるTFTアレイのゲ
ート電極は、通常、耐熱性の高いCr等の高融点金属が用
いられるが、大画面,高解像度化を行うには配線抵抗に
よる信号の減衰、遅れ等を防止するため、膜厚を厚く
し、低抵抗化を図る必要がある。しかし、膜厚を厚くす
るとCr等の高融点金属は膜の応力のためにクラックなど
の発生確率が高くなる。また、高解像化、大画面化にと
もなう微細配線化、配線長の増大のためにゴミ等による
パターニング不良等による断線が発生し、歩留りの低下
を招くといった欠点がある。このような欠点を克服する
ため、従来の液晶表示装置のTFTアレイでは、第5図,
第6図,第7図に示すように、最初の画素電極5形成時
に同時に透明導電膜からなる画素電極材料でゲート配線
11を形成し、次いで、ゲート配線11上にゲート配線11を
覆うように本来のゲート電極及び配線2を形成してゲー
ト配線を2層化する方法が行われてきた。
Generally, a gate electrode of a TFT array used in a liquid crystal display device or the like is usually made of a refractory metal such as Cr having high heat resistance, but in order to achieve a large screen and high resolution, signal attenuation due to wiring resistance, In order to prevent delay and the like, it is necessary to increase the film thickness and reduce the resistance. However, when the film thickness is increased, refractory metal such as Cr has a high probability of cracking due to the stress of the film. Further, there is a defect that disconnection occurs due to patterning failure due to dust or the like due to high resolution, fine wiring accompanying screen enlargement, and increase in wiring length, leading to a reduction in yield. In order to overcome such drawbacks, the conventional TFT array of the liquid crystal display device is shown in FIG.
As shown in FIGS. 6 and 7, at the same time when the first pixel electrode 5 is formed, the gate electrode is made of the transparent conductive film and the gate wiring is formed.
A method has been performed in which 11 is formed, and then the original gate electrode and the wiring 2 are formed on the gate wiring 11 so as to cover the gate wiring 11 to form the gate wiring into two layers.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

従来の液晶表示装置は上述のように、ゲート配線を2
層化し、ゲート配線とソース配線の交差部分に画素電極
材料によるゲート配線が存在するように構成しているの
で、画素電極材料中のゴミや段差部分等の影響によりゲ
ート配線とソース配線との短絡が発生し、歩留りの低下
を招くといった問題点があった。
As described above, the conventional liquid crystal display device has two gate wirings.
Since the gate wiring made of the pixel electrode material exists at the intersection of the gate wiring and the source wiring by layering, the short circuit between the gate wiring and the source wiring due to the influence of dust in the pixel electrode material or the step However, there is a problem in that the yield occurs and the yield decreases.

この発明は上記のような問題点を解消するためになさ
れたもので、ソース配線とゲート配線との交差部におけ
るゲート配線とソース配線との線間短絡欠陥を増加させ
ることなく、ゲート配線の断線欠陥を低減できるTFTア
レイを有する液晶表示装置を提供することを目的とす
る。
The present invention has been made in order to solve the above problems, and disconnection of the gate wiring without increasing the line short-circuit defects between the gate wiring and the source wiring at the intersections of the source wiring and the gate wiring. An object of the present invention is to provide a liquid crystal display device having a TFT array capable of reducing defects.

〔課題を解決するための手段〕[Means for solving the problem]

この発明に係る液晶表示装置は、TFTアレイ基板のゲ
ート電極配線を、ゲート電極配線とソース電極配線との
交差部分を除く部分においては画素電極と同一平面上に
形成された透明導電膜と本来のゲート電極配線材料の導
電膜の2層構造とし、かつ、ゲート電極配線とソース電
極配線との交差部分においては導電膜の単層構造とした
ものである。
In the liquid crystal display device according to the present invention, the gate electrode wiring of the TFT array substrate is provided with a transparent conductive film formed on the same plane as the pixel electrode except for the intersection of the gate electrode wiring and the source electrode wiring. It has a two-layer structure of a conductive film of a gate electrode wiring material, and has a single-layer structure of a conductive film at the intersection of the gate electrode wiring and the source electrode wiring.

〔作用〕[Action]

この発明の液晶表示装置においては、ゲート配線とソ
ース配線との交差部分以外の部分においてゲート配線が
画素電極と同一平面上に形成された透明導電膜と導電膜
の2層構造となり、また、ゲート配線とソース配線との
交差部分では本来のゲート配線による導電膜の単層構造
となるので、ゲート配線とソース配線との交差部分での
ゲート配線とソース配線との線間短絡を増加させること
なくゲート配線の断線を低減させることが可能となり、
歩留りが向上する。
In the liquid crystal display device according to the present invention, the gate wiring has a two-layer structure of a transparent conductive film and a conductive film which are formed on the same plane as the pixel electrode except the intersection of the gate wiring and the source wiring. Since the single layer structure of the conductive film by the original gate wiring is formed at the intersection of the wiring and the source wiring, there is no increase in short circuit between the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring. It is possible to reduce disconnection of gate wiring,
The yield is improved.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例による液晶表示装置のTFT
アレイの部分平面図、第2図,第3図及び第4図は第1
図のA−A′部,B−B′部,及びC−C′部の断面図を
各々示している。図におて、第5図と同一符号は同一部
分を示し、11はゲート配線とソース配線との交差部分以
外の部分に画素電極と同時形成したゲート配線である。
FIG. 1 is a TFT of a liquid crystal display device according to an embodiment of the present invention.
Partial plan views of the array, FIGS. 2, 3, and 4 are first
The cross-sectional views of the AA 'portion, the BB' portion, and the CC 'portion of the drawing are respectively shown. In the figure, the same reference numerals as those in FIG. 5 indicate the same portions, and 11 is a gate wiring formed at the same time as the pixel electrode in a portion other than the intersection of the gate wiring and the source wiring.

以下、本実施例の製造方法について説明する。 Hereinafter, the manufacturing method of this embodiment will be described.

まず、ガラス等の透明絶縁基板1上にITO(Indium Ti
n Oxide;酸化インジウムスズ膜)などの透明導電膜をEB
(Electron Beam)蒸着法等で堆積する。この後、ホト
リソグラフィー等の方法で画素電極5と、ゲート配線2
とソース配線3との交差部分のこれより少し幅広の部分
を除く部分にアイランド状のゲート配線11を形成する。
次にスパッタ等の方法で、Cr等の金属を堆積し、ゲート
電極及びゲート配線2を前記ITOによるゲート配線11上
にこれより大きく形成する。次にゲート絶縁膜6となる
シリコン窒化膜またはシリコン酸化膜等、及び半導体層
7となる水素化アモルファスシリコン(a−Si;H)等を
連続してプラズマCVD法等により全面に堆積する。次い
で、半導体層7をアイランド状に形成し、ゲート絶縁膜
6に画素電極5を接続するためのコンタクトホールの形
成を行う。次にAlなどの金属膜を堆積し、ソース電極及
びソース配線3とドレイン電極4を形成する。次に、パ
ッシベーション膜8としてシリコン窒化膜またはシリコ
ン酸化膜等を堆積する。そして一括して画素電極5上の
ゲート絶縁膜6及びパッシベーション膜8を除去する。
次に半導体層7を形成した部分の上方にAl等を堆積して
遮光膜9を形成する。
First, on a transparent insulating substrate 1 such as glass, ITO (Indium Ti
n Oxide; transparent conductive film such as indium tin oxide film)
(Electron Beam) Deposited by a vapor deposition method or the like. Then, the pixel electrode 5 and the gate wiring 2 are formed by a method such as photolithography.
An island-shaped gate wiring 11 is formed at a portion other than a portion slightly wider than the intersection between the gate wiring 11 and the source wiring 3.
Next, a metal such as Cr is deposited by a method such as sputtering to form the gate electrode and the gate wiring 2 on the gate wiring 11 made of ITO in a larger size. Next, a silicon nitride film or a silicon oxide film to be the gate insulating film 6 and hydrogenated amorphous silicon (a-Si; H) to be the semiconductor layer 7 are continuously deposited on the entire surface by plasma CVD or the like. Next, the semiconductor layer 7 is formed in an island shape, and a contact hole for connecting the pixel electrode 5 to the gate insulating film 6 is formed. Next, a metal film such as Al is deposited to form the source electrode and the source wiring 3 and the drain electrode 4. Next, a silicon nitride film, a silicon oxide film, or the like is deposited as the passivation film 8. Then, the gate insulating film 6 and the passivation film 8 on the pixel electrode 5 are removed collectively.
Then, Al or the like is deposited above the portion where the semiconductor layer 7 is formed to form the light shielding film 9.

このようにして形成したTFTアレイ基板と、透明導電
膜及びカラーフィルム等を有する対向基板との間に液晶
等の表示材料を挟持し、本発明の液晶表示装置を完成す
る。
A display material such as liquid crystal is sandwiched between the TFT array substrate thus formed and a counter substrate having a transparent conductive film, a color film, etc., to complete the liquid crystal display device of the present invention.

上記構成のTFTアレイを備えた液晶表示装置は、ゲー
ト配線2とソース配線3との交差部分以外のすべての部
分において、ゲート配線を2層化しており、しかもパタ
ーニングを別々に行っているため、いずれかの配線にク
ラックあるいはゴミ等によるパターニング不良が発生し
たとしても他方の配線で接続がなされており、断線欠陥
は生じない。しかもゲート配線2とソース配線3との交
差部分は従来のゲート配線2の単層構造となっているた
め、ゲート配線11上のゴミなどによるゲート電極配線と
ソース電極配線との短絡欠陥も生じない。従って、本発
明では極めて表示欠陥の少ない、大面積、高解像度の液
晶表示装置を、高歩留りで得ることができる。
In the liquid crystal display device including the TFT array having the above-described configuration, the gate wiring is formed into two layers at all portions except the intersection of the gate wiring 2 and the source wiring 3, and patterning is performed separately. Even if a patterning defect occurs due to cracks, dust, or the like in any of the wirings, the connection is made in the other wiring, and a disconnection defect does not occur. Moreover, since the intersection of the gate wiring 2 and the source wiring 3 has the single-layer structure of the conventional gate wiring 2, short-circuit defects between the gate electrode wiring and the source electrode wiring due to dust on the gate wiring 11 do not occur. . Therefore, according to the present invention, it is possible to obtain a large-area, high-resolution liquid crystal display device with extremely few display defects with high yield.

なお、上記実施例では半導体層7には水素化アモルフ
ァスシリコン膜を用いたが、これは多結晶シリコン膜で
もよい。
Although the hydrogenated amorphous silicon film is used for the semiconductor layer 7 in the above-mentioned embodiment, it may be a polycrystalline silicon film.

また、上記実施例では、ゲート電極配線2の導電膜と
してはCrを用いたが、これはCrの他に、Ta,Ti,Ni−Cr,M
o,Al−Si等からなる金属でもよい。
Further, in the above-mentioned embodiment, Cr is used as the conductive film of the gate electrode wiring 2. However, in addition to Cr, Ta, Ti, Ni-Cr, M
A metal composed of o, Al-Si or the like may be used.

また、上記実施例ではソース電極配線3とゲート電極
配線2との交差部近傍にはTFTからなる半導体層7を1
つ設けるように構成したが、複数個の並列に設けるよう
に構成してもよい。
Further, in the above embodiment, the semiconductor layer 7 made of TFT is formed in the vicinity of the intersection of the source electrode wiring 3 and the gate electrode wiring 2.
Although it is configured to provide one, a plurality of may be provided in parallel.

〔発明の効果〕〔The invention's effect〕

以上のように本発明の液晶表示装置によれば、ゲート
配線とソース配線との交差部分以外の部分にアイランド
状に透明導電膜からなる画電極材料でゲート配線を形成
し、次いで、導体膜により本来のゲート電極及び配線を
形成することにより、ゲート配線とソース配線との交差
部分以外の部分においてはゲート配線を2層構造、ま
た、ゲート配線とソース配線との交差部分においてはゲ
ート配線を単層構造としたので、ゲート配線とソース配
線との交差部分の線間短絡を防止でき、しかも、ゲート
配線の断線を低減でき、高歩留りを実現できる効果があ
る。
As described above, according to the liquid crystal display device of the present invention, the gate wiring is formed in the island-shaped image electrode material made of the transparent conductive film in a portion other than the intersection of the gate wiring and the source wiring, and then the conductive film is used. By forming the original gate electrode and wiring, the gate wiring has a two-layer structure in the portion other than the intersection of the gate wiring and the source wiring, and the gate wiring has a single layer in the intersection of the gate wiring and the source wiring. Since it has a layered structure, it is possible to prevent short-circuiting between lines at the intersection of the gate wiring and the source wiring, reduce the disconnection of the gate wiring, and achieve high yield.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例による液晶表示装置のTFTア
レイの部分平面図、第2図は第1図のA−A′部の断面
図、第3図は第1図のB−B′部の断面図、第4図は第
1図のC−C′部の断面図、第5図は従来の液晶表示装
置のTFTアレイの部分平面図、第6図は第5図のD−
D′部の断面図、第7図は第5図のE−E′部の断面図
である。 1は透明絶縁性基板、2はゲート電極及び配線、3はソ
ース電極及び配線、4はドレイン電極、5は画素電極、
6はゲート絶縁膜、7は半導体層、8はパッシベーショ
ン膜、9は遮光膜、10はドレイン電極と画素電極とのコ
ンタクト部分、11は画素電極と同時形成したゲート配線
である。 なお図中同一符号は同一又は相当部分を示す。
FIG. 1 is a partial plan view of a TFT array of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA ′ in FIG. 1, and FIG. 3 is a cross section taken along the line BB in FIG. 4 is a sectional view taken along line CC 'of FIG. 1, FIG. 5 is a partial plan view of a TFT array of a conventional liquid crystal display device, and FIG. 6 is a sectional view taken along line D- of FIG.
FIG. 7 is a sectional view of the section D ', and FIG. 7 is a sectional view of the section EE' in FIG. 1 is a transparent insulating substrate, 2 is a gate electrode and wiring, 3 is a source electrode and wiring, 4 is a drain electrode, 5 is a pixel electrode,
Reference numeral 6 is a gate insulating film, 7 is a semiconductor layer, 8 is a passivation film, 9 is a light-shielding film, 10 is a contact portion between the drain electrode and the pixel electrode, and 11 is a gate wiring formed simultaneously with the pixel electrode. In the drawings, the same reference numerals indicate the same or corresponding parts.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 前島 太郎 兵庫県尼崎市塚口本町8丁目1番1号 三菱電機株式会社材料研究所内 (72)発明者 羽山 昌宏 兵庫県尼崎市塚口本町8丁目1番1号 三菱電機株式会社材料研究所内 (56)参考文献 特開 昭64−29819(JP,A) 特開 昭63−9977(JP,A) 特開 昭62−288882(JP,A) 特開 昭62−205390(JP,A) 特開 昭62−65468(JP,A) 特開 昭61−105582(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Taro Maejima 8-1-1 Tsukaguchi Honcho, Amagasaki City, Hyogo Prefecture Mitsubishi Electric Corporation Material Research Laboratory (72) Inventor Masahiro Hayama 8-1-1 Tsukaguchi Honmachi, Amagasaki City, Hyogo Prefecture No. 1 Mitsubishi Electric Corp. Material Research Laboratory (56) Reference JP-A 64-29819 (JP, A) JP-A 63-9977 (JP, A) JP-A 62-288882 (JP, A) JP-A 62-205390 (JP, A) JP-A-62-65468 (JP, A) JP-A-61-105582 (JP, A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】透明絶縁性基板上に、 複数のゲート電極配線と、 該ゲート電極配線と交差するように形成された複数のソ
ース電極配線と、 上記ゲート電極配線とソース電極配線との交差部の近傍
に配置された、少なくとも1個の非線型特性を持つ薄膜
トランジスタ(以下、TFTと略す)と、 該TFTのドレイン電極に接続された透明導電膜である表
示電極とを備えてなるTFTアレイ基板を有するととも
に、 透明導電膜を有する対向電極基板と、 上記TFTアレイ基板と対向電極基板との間に狭持された
液晶材料とを有する液晶表示装置において、 上記TFTアレイ基板のゲート電極配線は、該ゲート電極
配線と上記ソース電極配線との交差部分を除く部分にお
いては、上記表示電極と同一平面上に形成された透明導
電膜と、該透明導電膜上及び上記透明絶縁性基板上に連
続的に形成された導体膜との2層構造とし、かつ上記ゲ
ート電極配線とソース電極配線との交差部分において
は、該導体膜の単層構造としたことを特徴とする液晶表
示装置。
1. A plurality of gate electrode wirings, a plurality of source electrode wirings formed so as to intersect with the gate electrode wirings, and an intersection portion of the gate electrode wirings and the source electrode wirings on a transparent insulating substrate. TFT array substrate including at least one thin film transistor (hereinafter abbreviated as TFT) having a non-linear characteristic, which is disposed in the vicinity of the TFT, and a display electrode which is a transparent conductive film connected to the drain electrode of the TFT. And a liquid crystal display device having a counter electrode substrate having a transparent conductive film, and a liquid crystal material sandwiched between the TFT array substrate and the counter electrode substrate, wherein the gate electrode wiring of the TFT array substrate is The transparent conductive film formed on the same plane as the display electrode, and the transparent conductive film and the transparent insulating film are formed on a portion other than the intersection of the gate electrode wiring and the source electrode wiring. A liquid crystal having a two-layer structure with a conductor film continuously formed on a flexible substrate, and having a single-layer structure of the conductor film at the intersection of the gate electrode wiring and the source electrode wiring. Display device.
JP5340188A 1988-03-07 1988-03-07 Liquid crystal display Expired - Fee Related JP2695424B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5340188A JP2695424B2 (en) 1988-03-07 1988-03-07 Liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5340188A JP2695424B2 (en) 1988-03-07 1988-03-07 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPH01227128A JPH01227128A (en) 1989-09-11
JP2695424B2 true JP2695424B2 (en) 1997-12-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP5340188A Expired - Fee Related JP2695424B2 (en) 1988-03-07 1988-03-07 Liquid crystal display

Country Status (1)

Country Link
JP (1) JP2695424B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07113726B2 (en) * 1989-01-10 1995-12-06 富士通株式会社 Method of manufacturing thin film transistor matrix
JPH03118520A (en) * 1989-09-29 1991-05-21 Sharp Corp Thin film transistor array
JP2585465B2 (en) * 1990-11-21 1997-02-26 株式会社東芝 Matrix array substrate
JP2012191008A (en) * 2011-03-10 2012-10-04 Sony Corp Display device and electronic apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105582A (en) * 1984-10-29 1986-05-23 富士通株式会社 Manufacture of thin film transistor matrix
JPS6265468A (en) * 1985-09-18 1987-03-24 Toshiba Corp Display device
JPS62205390A (en) * 1986-03-06 1987-09-09 株式会社東芝 Substrate for display unit
JPS62288882A (en) * 1986-06-09 1987-12-15 アルプス電気株式会社 Manufacture of thin film transistor
JPS639977A (en) * 1986-07-01 1988-01-16 Citizen Watch Co Ltd Thin-film transistor

Also Published As

Publication number Publication date
JPH01227128A (en) 1989-09-11

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