JPH06244600A - Inspection equipment for integrated circuit chip levitation - Google Patents
Inspection equipment for integrated circuit chip levitationInfo
- Publication number
- JPH06244600A JPH06244600A JP5054809A JP5480993A JPH06244600A JP H06244600 A JPH06244600 A JP H06244600A JP 5054809 A JP5054809 A JP 5054809A JP 5480993 A JP5480993 A JP 5480993A JP H06244600 A JPH06244600 A JP H06244600A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- lead frame
- image
- floating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Length Measuring Devices By Optical Means (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Supply And Installment Of Electrical Components (AREA)
- Die Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、リードフレーム上に接
着された集積回路チップの当該リードフレームからの浮
き上がり量を検査するための集積回路チップ浮き上がり
検査装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit chip floating inspection device for inspecting an amount of floating of an integrated circuit chip adhered on a lead frame from the lead frame.
【0002】[0002]
【従来の技術】一般に、ダイボンダーにより集積回路ウ
エハーから切り出された集積回路チップ(ベアチップ)
を接着用樹脂が塗布されたリードフレーム上に搭載し、
リードフレームと集積回路チップ間に介在する接着用樹
脂で接着するダイボンディング工程においては、リード
フレームに対する集積回路チップの浮き上がりが問題と
なる。図4はリードフレーム1上に集積回路チップ2を
ダイボンダーによって搭載した所であり、図5はリード
フレーム1に対する集積回路チップ2の接着が適正に行
われて浮き上がり量が実質的に零の場合、図6はリード
フレーム1と集積回路チップ2間の接着用樹脂3が偏在
して浮き上がり量Zが許容範囲を越えて過大となってい
る状態を示す。2. Description of the Related Art Generally, an integrated circuit chip (bare chip) cut out from an integrated circuit wafer by a die bonder.
Mounted on a lead frame coated with adhesive resin,
In the die bonding process of bonding with the bonding resin interposed between the lead frame and the integrated circuit chip, the floating of the integrated circuit chip with respect to the lead frame becomes a problem. 4 shows a place where the integrated circuit chip 2 is mounted on the lead frame 1 by a die bonder, and FIG. 5 shows a case where the integrated circuit chip 2 is properly adhered to the lead frame 1 and the floating amount is substantially zero. FIG. 6 shows a state in which the adhesive resin 3 between the lead frame 1 and the integrated circuit chip 2 is unevenly distributed, and the lift amount Z exceeds the allowable range and becomes excessive.
【0003】上述の集積回路チップ2の浮き上がりの問
題のため、ワイヤーボンディング工程等の後工程を実行
する前に、リードフレーム1に対する集積回路チップ2
の浮き上がり量が許容範囲内であるか否かを検査する必
要がある。従来は、ダイボンディング工程における集積
回路チップの浮き上がり量検査は、検査員の目視により
実施されていた。Due to the floating problem of the integrated circuit chip 2 described above, the integrated circuit chip 2 with respect to the lead frame 1 is processed before the post-process such as the wire bonding process is performed.
It is necessary to inspect whether the floating amount of is within the allowable range. Conventionally, the inspection of the lifted amount of the integrated circuit chip in the die bonding process has been performed visually by an inspector.
【0004】[0004]
【発明が解決しようとする課題】ところで、検査員の目
視による検査では、検査能率の向上に限度があり、かつ
集積回路チップの浮き上がり量の定量的な管理が難しい
問題があった。本発明は、上記の点に鑑み、ダイボンデ
ィング工程における集積回路チップのリードフレームか
らの浮き上がり量検査の自動化を可能にし、かつ浮き上
がり量の定量的な管理を可能とした集積回路チップ浮き
上がり検査装置を提供することを目的とする。By the way, the visual inspection by the inspector has a problem that there is a limit to the improvement of the inspection efficiency and it is difficult to quantitatively control the floating amount of the integrated circuit chip. In view of the above points, the present invention provides an integrated circuit chip lift inspection device that enables automation of lift amount inspection from a lead frame of an integrated circuit chip in a die bonding process and that enables quantitative management of the lift amount. The purpose is to provide.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明の集積回路チップ浮き上がり検査装置は、リ
ードフレーム上に接着された集積回路チップの当該リー
ドフレームからの浮き上がり量を検査する場合におい
て、前記集積回路チップの両側に、当該集積回路チップ
を挟んで傾斜した反射面が相互に対向する如く少なくと
も一対の反射鏡を配設し、それら一対の反射鏡のうちの
一方の反射鏡に照明手段を対向配置するとともに、他方
の反射鏡に撮像手段を対向配置し、前記照明手段から照
射された光が一方の反射鏡で反射されて前記集積回路を
側方から照らすようにして前記撮像手段にて前記集積回
路チップの影像を撮像し、前記集積回路チップの上辺に
相当する影像部分の少なくとも2点の位置から前記集積
回路チップの前記リードフレームからの浮き上がり量を
検出する構成としている。In order to achieve the above-mentioned object, the integrated circuit chip lift inspection apparatus of the present invention is used for inspecting the lift amount of an integrated circuit chip bonded on a lead frame from the lead frame. In the above, at least a pair of reflecting mirrors are arranged on both sides of the integrated circuit chip so that inclined reflecting surfaces sandwiching the integrated circuit chip face each other, and one reflecting mirror of one of the pair of reflecting mirrors is provided. The imaging means is arranged so that the illuminating means is opposed to the other reflecting mirror, and the light emitted from the illuminating means is reflected by the one reflecting mirror to illuminate the integrated circuit from the side. Means captures an image of the integrated circuit chip, and the image of the integrated circuit chip is picked up from at least two positions of the image portion corresponding to the upper side of the integrated circuit chip. It is configured to detect the floating amount of the lead frame.
【0006】[0006]
【作用】本発明の集積回路チップ浮き上がり検査装置に
おいては、反射鏡の配置を工夫することによって、照明
手段から照射された光が一方の反射鏡で反射されて集積
回路チップを側方から照らすようにして撮像手段にて集
積回路チップの影像を正確に撮像できる。そして、集積
回路チップの上辺に相当する影像部分の少なくとも2点
の位置を画像処理により検出することで、リードフレー
ムからの集積回路チップの浮き上がり量を認識すること
ができ、該浮き上がり量が許容範囲内であるか否かを判
別できる。In the apparatus for inspecting the lift of the integrated circuit chip of the present invention, by devising the arrangement of the reflecting mirrors, the light emitted from the illuminating means is reflected by one reflecting mirror to illuminate the integrated circuit chip from the side. Then, the image of the integrated circuit chip can be accurately taken by the imaging means. Then, by detecting the positions of at least two points of the image portion corresponding to the upper side of the integrated circuit chip by image processing, the amount of lift of the integrated circuit chip from the lead frame can be recognized, and the amount of lift is within an allowable range. It can be determined whether or not it is within.
【0007】[0007]
【実施例】以下、本発明に係る集積回路チップ浮き上が
り検査装置の実施例を図面に従って説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an integrated circuit chip floating inspection device according to the present invention will be described below with reference to the drawings.
【0008】図1において、被検査物は、リードフレー
ム1上に集積回路チップ(ベアチップ)2を載置し、接
着用樹脂で接着したものである。撮像手段としてのテレ
ビカメラ4及び照明手段としての照明器5は、被検査
物、すなわちリードフレーム1及び集積回路チップ2の
上方位置で水平面内で回転するように支持された回転ス
テージ6にそれぞれ下向きに取り付けられている。集積
回路チップ2の側方よりみた集積回路チップ2のリード
フレーム1からの浮き上がり量を測定するために集積回
路チップ2を取り囲む如く反射器10が配置される。In FIG. 1, an object to be inspected is one in which an integrated circuit chip (bare chip) 2 is placed on a lead frame 1 and bonded with an adhesive resin. The television camera 4 as the image pickup means and the illuminator 5 as the lighting means face downward on the rotary stage 6 supported so as to rotate in a horizontal plane above the object to be inspected, that is, the lead frame 1 and the integrated circuit chip 2. Is attached to. A reflector 10 is arranged so as to surround the integrated circuit chip 2 in order to measure the amount of lift of the integrated circuit chip 2 from the lead frame 1 as viewed from the side of the integrated circuit chip 2.
【0009】図2の如く、反射器10は正四角錐状の凹
面を成すように4個の平面鏡(完全反射平面鏡)11を
反射面が傾斜状態で対向するように4個組み合わせ一体
化したものであり、各平面鏡11の反射面はリードフレ
ーム上面に対して45度よりも僅かに大きな角度をなし
ている。As shown in FIG. 2, the reflector 10 is formed by combining four plane mirrors (completely reflecting plane mirrors) 11 so as to form a regular quadrangular pyramid-shaped concave surface so that the reflecting surfaces face each other in an inclined state. The reflecting surface of each plane mirror 11 forms an angle slightly larger than 45 degrees with the upper surface of the lead frame.
【0010】測定時において、前記照明器5は集積回路
チップ2を挟んで対向する一対の平面鏡11の一方のも
のの真上に位置し、テレビカメラ4は他方のものの真上
に位置する。テレビカメラ4の出力であるビデオ信号
は、画像処理装置20に入力されるようになっている。At the time of measurement, the illuminator 5 is located directly above one of the pair of plane mirrors 11 that face each other with the integrated circuit chip 2 in between, and the television camera 4 is located directly above the other. The video signal output from the television camera 4 is input to the image processing device 20.
【0011】前記回転ステージ6はX,Y,Z方向に移
動自在で、回転中心Sを持つものである。したがって、
ステージ6が90度毎回転することで、テレビカメラ4
は、4個の平面鏡11でそれぞれ反射された画像を順次
取り込むことができる。なお、反射器10は上下手段に
より支えられており、測定時以外では上昇位置となって
被検査物の搬送の妨げとならないようになっている。The rotary stage 6 is movable in X, Y and Z directions and has a rotation center S. Therefore,
By rotating the stage 6 every 90 degrees, the TV camera 4
Can sequentially capture images reflected by the four plane mirrors 11. The reflector 10 is supported by the up-and-down means so as not to interfere with the conveyance of the object to be inspected at the raised position except during measurement.
【0012】この実施例の構成において、照明器5から
下方に照射された光は、一方の平面鏡11でリードフレ
ーム1に沿った横方向に反射されて集積回路チップ2を
通過する透過光となり、該透過光はさらに他方の平面鏡
11で反射されてテレビカメラ4の光軸Rと同軸方向
(上方)に進行する。この結果、テレビカメラ4では横
方向の透過光で照射された集積回路チップ2及びその周
辺を正確に撮像することができる。その際、各平面鏡1
1の反射面は、リードフレーム上面に対して45度より
も僅かに大きな角度をなしているから、集積回路チップ
2の下部を通過する光も発生でき、集積回路チップ2の
下部の画像も良好に取り込むことができる。画像処理装
置20では、テレビカメラ4のビデオ信号を2値化又は
多値化処理することで、図3(A),(B)に示すよう
にリードフレーム1上の集積回路チップ2の影像Q1,
Q2を認識でき、さらに予め既知のカメラ視野の上辺か
ら集積回路チップ2の上辺に相当した影像Q1,Q2の
上辺に至る距離a,b及び|a−b|をそれぞれ計測す
ることができる。In the structure of this embodiment, the light emitted downward from the illuminator 5 is reflected by one of the plane mirrors 11 in the lateral direction along the lead frame 1 and becomes the transmitted light passing through the integrated circuit chip 2. The transmitted light is further reflected by the other plane mirror 11 and travels in the direction coaxial with the optical axis R of the television camera 4 (upward). As a result, the television camera 4 can accurately capture an image of the integrated circuit chip 2 and its periphery illuminated by the transmitted light in the lateral direction. At that time, each plane mirror 1
Since the reflection surface of No. 1 makes an angle of slightly larger than 45 degrees with respect to the upper surface of the lead frame, light passing through the lower part of the integrated circuit chip 2 can also be generated and the image under the integrated circuit chip 2 is also good. Can be taken into. In the image processing device 20, the image signal Q1 of the integrated circuit chip 2 on the lead frame 1 is processed as shown in FIGS. ,
Q2 can be recognized, and the distances a, b and | a−b | from the known upper side of the camera visual field to the upper sides of the images Q1 and Q2 corresponding to the upper side of the integrated circuit chip 2 can be measured in advance.
【0013】前記距離a,bを利用した浮き上がり量の
判定は、例えば距離a,b共に一定値以上で(リードフ
レーム1の上面からの浮き上がり量が一定値以内)、|
a−b|が一定値以内(集積回路チップの傾きが一定角
度以下)であるか否かによって行うことができる。図3
(A)は距離a<bで、距離aが過小であり、換言すれ
ば、リードフレーム1上面を基準とした集積回路チップ
2の浮き上がり量が許容範囲を越えて過大であり、ダイ
ボンディングが不良であることを示している。また、図
3(B)は距離a≒bであって、距離a,b共に適正値
であり、換言すれば、リードフレーム1上面を基準とし
た集積回路チップ2の浮き上がり量が許容範囲内であ
り、ダイボンディングが良好であることを示している。The determination of the amount of floating using the distances a and b is, for example, when the distances a and b are both above a certain value (the amount of floating above the lead frame 1 is within a certain value), |
It can be determined by whether or not ab | is within a certain value (the inclination of the integrated circuit chip is less than a certain angle). Figure 3
(A) is a distance a <b, and the distance a is too small. In other words, the lift amount of the integrated circuit chip 2 with reference to the upper surface of the lead frame 1 is excessive beyond the allowable range, and the die bonding is defective. Is shown. Further, FIG. 3B shows a distance a≈b, and both distances a and b are proper values. In other words, the floating amount of the integrated circuit chip 2 with the upper surface of the lead frame 1 as a reference is within an allowable range. Yes, it indicates that the die bonding is good.
【0014】上記浮き上がり量の計測及び良否判定は、
前記回転ステージ6が90度毎回転することで集積回路
チップ2の4側面について順次実施でき、4側面全部に
ついて浮き上がり量の計測を行い、良否判別を行った
後、最終的な良否判別を行うことができる。すなわち、
1側面でも不良と判定されたものは、他の側面の測定に
おいて良品であると判定されても最終的に不良と判定す
る。The measurement of the amount of floating and the quality judgment are as follows.
By rotating the rotating stage 6 every 90 degrees, the four side surfaces of the integrated circuit chip 2 can be sequentially performed, and the lift amount is measured on all the four side surfaces, and the quality determination is performed, and then the final quality determination is performed. You can That is,
Those that are determined to be defective on one side are finally determined to be defective even if they are determined to be non-defective in the measurement of the other side.
【0015】以上本発明の実施例について説明してきた
が、本発明はこれに限定されることなく請求項の記載の
範囲内において各種の変形、変更が可能なことは当業者
には自明であろう。Although the embodiment of the present invention has been described above, it is obvious to those skilled in the art that the present invention is not limited to this and various modifications and changes can be made within the scope of the claims. Let's do it.
【0016】[0016]
【発明の効果】以上説明したように、本発明の集積回路
チップ浮き上がり検査装置によれば、反射鏡の配置を工
夫することにより、リードフレームからの集積回路チッ
プの浮き上がり量を正確に認識でき、この結果、ダイボ
ンディング工程終了後の検査の自動化を図ることがで
き、外観検査人員の省力化を図り得る。さらに、検査結
果をダイボンディング工程を実行するダイボンダーにフ
ィードバックすることにより、製品の品質向上を図るこ
とが可能となる。As described above, according to the integrated circuit chip floating inspection apparatus of the present invention, the amount of floating of the integrated circuit chip from the lead frame can be accurately recognized by devising the arrangement of the reflecting mirror. As a result, the inspection after the die bonding process can be automated, and the labor of the visual inspection personnel can be reduced. Further, by feeding back the inspection result to the die bonder that executes the die bonding process, it is possible to improve the quality of the product.
【図1】本発明に係る集積回路チップ浮き上がり検査装
置の実施例を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of an integrated circuit chip floating inspection device according to the present invention.
【図2】実施例で用いる反射器の平面図である。FIG. 2 is a plan view of a reflector used in an example.
【図3】集積回路チップの影像の例を示す説明図であ
る。FIG. 3 is an explanatory diagram showing an example of an image of an integrated circuit chip.
【図4】ダイボンディング工程によりリードフレーム上
に集積回路チップを搭載した所を示す平面図である。FIG. 4 is a plan view showing a place where an integrated circuit chip is mounted on a lead frame by a die bonding process.
【図5】リードフレーム上に集積回路チップを搭載した
状態であって浮き上がり量が実質的に零である場合を示
す側面図である。FIG. 5 is a side view showing a case where an integrated circuit chip is mounted on a lead frame and a floating amount is substantially zero.
【図6】リードフレーム上に集積回路チップを搭載した
状態であって浮き上がり量が過大である場合を示す側面
図である。FIG. 6 is a side view showing a case where an integrated circuit chip is mounted on a lead frame and the amount of floating is excessive.
1 リードフレーム 2 集積回路チップ 3 接着用樹脂 4 テレビカメラ 5 照明器 6 回転ステージ 10 反射器 11 平面鏡 20 画像処理装置 Q1,Q2 影像 1 Lead Frame 2 Integrated Circuit Chip 3 Adhesive Resin 4 TV Camera 5 Illuminator 6 Rotating Stage 10 Reflector 11 Plane Mirror 20 Image Processing Device Q1, Q2 Image
Claims (1)
チップの当該リードフレームからの浮き上がり量を検査
する集積回路チップ浮き上がり検査装置において、前記
集積回路チップの両側に、当該集積回路チップを挟んで
傾斜した反射面が相互に対向する如く少なくとも一対の
反射鏡を配設し、それら一対の反射鏡のうちの一方の反
射鏡に照明手段を対向配置するとともに、他方の反射鏡
に撮像手段を対向配置し、前記照明手段から照射された
光が一方の反射鏡で反射されて前記集積回路チップを側
方から照らすようにして前記撮像手段にて前記集積回路
チップの影像を撮像し、前記集積回路チップの上辺に相
当する影像部分の少なくとも2点の位置から前記集積回
路チップの前記リードフレームからの浮き上がり量を検
出することを特徴とする集積回路チップ浮き上がり検査
装置。1. An integrated circuit chip lift inspection device for inspecting a lift amount of an integrated circuit chip adhered on a lead frame from the lead frame, wherein the integrated circuit chip is tilted on both sides of the integrated circuit chip. At least a pair of reflecting mirrors are arranged so that the reflecting surfaces face each other, and the illuminating means is arranged facing one of the pair of reflecting mirrors, and the imaging means is arranged facing the other reflecting mirror. Then, the light emitted from the illuminating means is reflected by one of the reflecting mirrors to illuminate the integrated circuit chip from the side, and the image pickup means captures an image of the integrated circuit chip. The floating amount of the integrated circuit chip from the lead frame is detected from the positions of at least two points in the image portion corresponding to the upper side of the. Integrated circuit chip floating inspection device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05480993A JP3398754B2 (en) | 1993-02-20 | 1993-02-20 | Integrated circuit chip lift inspection system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05480993A JP3398754B2 (en) | 1993-02-20 | 1993-02-20 | Integrated circuit chip lift inspection system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06244600A true JPH06244600A (en) | 1994-09-02 |
JP3398754B2 JP3398754B2 (en) | 2003-04-21 |
Family
ID=12981054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05480993A Expired - Fee Related JP3398754B2 (en) | 1993-02-20 | 1993-02-20 | Integrated circuit chip lift inspection system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3398754B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6580501B2 (en) | 1998-10-19 | 2003-06-17 | Ersa Gmbh | Apparatus and method for the visual inspection in particular of concealed soldered joints |
JP2016021514A (en) * | 2014-07-15 | 2016-02-04 | キヤノンマシナリー株式会社 | Semiconductor chip posture detecting apparatus and semiconductor chip posture detecting method |
-
1993
- 1993-02-20 JP JP05480993A patent/JP3398754B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6580501B2 (en) | 1998-10-19 | 2003-06-17 | Ersa Gmbh | Apparatus and method for the visual inspection in particular of concealed soldered joints |
DE19847913B4 (en) * | 1998-10-19 | 2005-09-22 | Ersa Gmbh | Apparatus and method for optical inspection, in particular concealed solder joints |
EP1123525B2 (en) † | 1998-10-19 | 2007-02-14 | Ersa GmbH | Device and method for the optical inspection of concealed soldered connections |
JP2016021514A (en) * | 2014-07-15 | 2016-02-04 | キヤノンマシナリー株式会社 | Semiconductor chip posture detecting apparatus and semiconductor chip posture detecting method |
Also Published As
Publication number | Publication date |
---|---|
JP3398754B2 (en) | 2003-04-21 |
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