JPH06244301A - Package for containing semiconductor element - Google Patents
Package for containing semiconductor elementInfo
- Publication number
- JPH06244301A JPH06244301A JP5025192A JP2519293A JPH06244301A JP H06244301 A JPH06244301 A JP H06244301A JP 5025192 A JP5025192 A JP 5025192A JP 2519293 A JP2519293 A JP 2519293A JP H06244301 A JPH06244301 A JP H06244301A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- insulating substrate
- recess
- capacitive element
- connection pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関し、より詳細には
内部に収容する半導体素子への電源ノイズの悪影響を有
効に防止するようになした半導体素子収納用パッケージ
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element accommodating package for accommodating semiconductor elements, and more particularly to a semiconductor for effectively preventing adverse effects of power source noise on semiconductor elements accommodated inside. The present invention relates to an element storage package.
【0002】[0002]
【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは図3に示すように、酸化アル
ミニウム質焼結体から成り、上面に半導体素子10を収容
するための凹部11a 及び該凹部11a 周辺から下面にかけ
て導出するタングステン、モリブデン、マンガン等の高
融点金属粉末から成るメタライズ配線層12を有する絶縁
基体11と、半導体素子10の各電極を外部電気回路に接続
するために前記メタライズ配線層12に銀ロウ等のロウ材
を介し取着された外部リード端子13と、蓋体14とから構
成されており、絶縁基体11の凹部11a 底面に半導体素子
10をガラス、樹脂、ロウ材等の接着剤を介して接着固定
するとともに各電極をメタライズ配線層12にボンディン
グワイヤ15を介して電気的に接続し、しかる後、絶縁基
体11の上面に蓋体14をガラス、樹脂、ロウ材等の封止材
を介して接合させ、絶縁基体11と蓋体14とから成る容器
内部に半導体素子10を気密に封入することによって製品
として半導体装置となる。2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor element accommodating package for accommodating a semiconductor element is made of an aluminum oxide sintered body and has a concave portion 11a for accommodating the semiconductor element 10 and an upper surface thereof. An insulating substrate 11 having a metallized wiring layer 12 made of a refractory metal powder such as tungsten, molybdenum, or manganese, which is led out from the periphery of the recess 11a to the lower surface, and the metallized wiring for connecting each electrode of the semiconductor element 10 to an external electric circuit. It is composed of an external lead terminal 13 attached to the layer 12 via a brazing material such as silver solder, and a lid 14, and the semiconductor element is provided on the bottom surface of the recess 11a of the insulating base 11.
10 is adhered and fixed through an adhesive such as glass, resin, or a brazing material, and each electrode is electrically connected to the metallized wiring layer 12 through a bonding wire 15, and thereafter, a lid is provided on the upper surface of the insulating base 11. A semiconductor device is obtained as a product by bonding 14 together with a sealing material such as glass, resin, a brazing material, etc., and hermetically sealing the semiconductor element 10 inside a container composed of the insulating base 11 and the lid 14.
【0003】尚、かかる従来の半導体素子収納用パッケ
ージは絶縁基体11の上面に内部に収容される半導体素子
10の電源電極及び接地電極に接続される接続パッド16が
形成されており、該接続パッド16にチタン酸バリウム磁
器を誘電体とした容量素子17が半田等のロウ材を介して
直接取着され、半導体素子10の電源電極と接地電極の間
に容量素子17を接続することによって半導体素子10への
電源ノイズの悪影響を有効に防止するようになってい
る。Incidentally, such a conventional semiconductor element housing package is a semiconductor element housed inside the upper surface of the insulating base 11.
A connection pad 16 connected to the power supply electrode 10 and the ground electrode 10 is formed, and a capacitor element 17 having a barium titanate porcelain as a dielectric is directly attached to the connection pad 16 via a brazing material such as solder. By connecting the capacitive element 17 between the power supply electrode and the ground electrode of the semiconductor element 10, the adverse effect of power supply noise on the semiconductor element 10 is effectively prevented.
【0004】しかしながら、この従来の半導体素子収納
用パッケージは半導体素子10を収容する絶縁基体11が酸
化アルミニウム質焼結体から成り、その熱伝導率が15W/
m ・K と低いこと及び近時、半導体素子10は高密度化、
高集積化が急激に進み、半導体素子10の単位面積、単位
体積当たりの発熱量が増大してきたこと等から絶縁基体
11の凹部11a 内に半導体素子10を収容し、半導体装置と
なした後、半導体素子10を作動させると半導体素子10が
該素子10自身の発する熱膨張係数によって高温となり、
半導体素子10に熱破壊を起こさせたり、特性に熱変化を
来し、誤動作させるという欠点を有していた。However, in this conventional semiconductor element housing package, the insulating substrate 11 for housing the semiconductor element 10 is made of an aluminum oxide sintered body, and its thermal conductivity is 15 W /
It is as low as m · K, and recently, the semiconductor element 10 has a higher density,
Due to the rapid progress of high integration, the amount of heat generated per unit area and unit volume of the semiconductor element 10 has increased.
After the semiconductor element 10 is housed in the recess 11a of 11 to form a semiconductor device, when the semiconductor element 10 is operated, the semiconductor element 10 has a high temperature due to the thermal expansion coefficient of the element 10 itself,
The semiconductor element 10 has the drawback of causing thermal breakdown or causing a thermal change in its characteristics to cause a malfunction.
【0005】そこで上記欠点を解消するために絶縁基体
11を酸化アルミニウム質焼結体に変えて熱伝導率が50W/
m ・K 以上と極めて熱を伝えやすい窒化アルミニウム質
焼結体で形成し、半導体素子10の発する熱を絶縁基体11
を介して大気中に良好に放散させることが考えられる。Therefore, in order to solve the above-mentioned drawbacks, an insulating substrate
11 is replaced with aluminum oxide sintered body and the thermal conductivity is 50 W /
The heat generated by the semiconductor element 10 is formed by an aluminum nitride sintered body that is extremely easy to transfer heat at m.
It is thought that it can be satisfactorily diffused into the atmosphere via.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、窒化ア
ルミニウム質焼結体で絶縁基体11を形成した場合、窒化
アルミニウム質焼結体の熱膨張係数は4 〜5 ×10-6/ ℃
であり、容量素子17を構成するチタン酸バリウム磁器の
熱膨張係数(10 〜11×10-6/ ℃) と大きく相違するため
窒化アルミニウム質焼結体から成る絶縁基体11に設けた
接続パッド16に容量素子17をロウ材を介して取着させる
際、絶縁基体11と容量素子17との間に両者の熱膨張係数
の相違に起因する大きな熱応力が発生し、これが絶縁基
体11と接続パッド16の接合部に内在して絶縁基体11と接
続パッド16との接合強度を低下させるという欠点を有し
ていた。そのためこのパッケージでは容量素子17に外力
が印加されると該外力によって容量素子17が接続パッド
16とともに絶縁基体11より容易に外れ、容量素子17によ
って半導体素子10への電源ノイズの悪影響を有効に防止
することができなくなるという欠点が誘発する。However, when the insulating substrate 11 is formed of an aluminum nitride sintered body, the thermal expansion coefficient of the aluminum nitride sintered body is 4 to 5 × 10 -6 / ° C.
And the thermal expansion coefficient (10 to 11 × 10 −6 / ° C.) of the barium titanate porcelain constituting the capacitive element 17 is greatly different, and therefore the connection pad 16 provided on the insulating substrate 11 made of an aluminum nitride sintered body is used. When the capacitive element 17 is attached to the insulating substrate 11 via the brazing material, a large thermal stress is generated between the insulating base 11 and the capacitive element 17 due to the difference in the thermal expansion coefficient between the two. There is a drawback that the bonding strength between the insulating substrate 11 and the connection pad 16 is reduced by being inherent in the bonding portion of 16. Therefore, in this package, when an external force is applied to the capacitive element 17, the capacitive element 17 is connected to the connection pad by the external force.
This causes a defect that it easily comes off from the insulating substrate 11 together with 16, and the capacitive element 17 cannot effectively prevent the adverse effect of power source noise on the semiconductor element 10.
【0007】[0007]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は半導体素子への熱の影響及び電源ノイ
ズの影響を有効に防止し、半導体素子を長期間にわたり
正常、且つ安定に作動させることができる半導体素子収
納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent the influence of heat and power supply noise on a semiconductor element, and to keep the semiconductor element normal for a long period of time, and An object of the present invention is to provide a package for accommodating semiconductor devices, which can be operated stably.
【0008】[0008]
【課題を解決するための手段】本発明は内部に半導体素
子を収容するための空所を有する窒化アルミニウム質焼
結体から成る絶縁容器に、内部に収容する半導体素子の
電源電極及び接地電極に接続される接続パッドを形成す
るとともに該接続パッドに容量素子を取着して成る半導
体素子収納用パッケージであって、前記絶縁容器の外表
面に容量素子を収容する凹部を設けるとともに該凹部底
面に接続パッドがその一部を絶縁容器中に埋入させた状
態で形成されていることを特徴とするものである。SUMMARY OF THE INVENTION The present invention provides an insulating container made of an aluminum nitride sintered body having a cavity for accommodating a semiconductor element therein, and a power supply electrode and a ground electrode of the semiconductor element accommodated therein. A package for accommodating a semiconductor element, comprising a connection pad to be connected and a capacitance element attached to the connection pad, wherein a recess for accommodating the capacitance element is provided on the outer surface of the insulating container, and a bottom surface of the recess is provided. The connection pad is formed in a state where a part of the connection pad is embedded in an insulating container.
【0009】[0009]
【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁容器を窒化アルミニウム質焼結体で形成したこ
とから半導体素子の作動時に発する熱は容器を介して大
気中に良好に放散され、その結果、容器内部に収容され
る半導体素子は常に低温となり、半導体素子を長期間に
わたり正常、且つ安定に作動させることができる。According to the package for accommodating a semiconductor element of the present invention, since the insulating container is made of the aluminum nitride sintered body, the heat generated during the operation of the semiconductor device is well dissipated into the atmosphere through the container. As a result, the semiconductor element housed inside the container is always at a low temperature, and the semiconductor element can be operated normally and stably for a long period of time.
【0010】また絶縁容器の外表面に設けた凹部内に容
量素子を収容し、且つ接続パッドの一部を絶縁容器内に
埋入させたことから容量素子に外力が印加されるのが有
効に防止されるとともに接続パッドと絶縁容器との接合
が補強されて強固となり、、その結果、絶縁容器に容量
素子が強固に取着され、該容量素子によって半導体素子
への電源ノイズの悪影響を有効に防止することができ
る。Further, since the capacitive element is housed in the concave portion provided on the outer surface of the insulating container, and a part of the connection pad is embedded in the insulating container, it is effective that external force is applied to the capacitive element. In addition, the joint between the connection pad and the insulating container is reinforced and strengthened, and as a result, the capacitive element is firmly attached to the insulating container, and the capacitive element effectively prevents the adverse effect of power supply noise on the semiconductor element. Can be prevented.
【0011】[0011]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。The present invention will now be described in detail with reference to the accompanying drawings.
【0012】図1 及び図2 は本発明の半導体素子収納用
パッケージの一実施例を示し、1 は絶縁基体、2 は蓋体
である。この絶縁基体1 と蓋体2 とで半導体素子3 を収
容するための容器4 が構成される。前記絶縁基体1 は窒
化アルミニウム質焼結体から成り、その上面に半導体素
子3を収容する空所を形成するための凹部1aを有し、該
凹部1a底面には半導体素子3 がガラス、樹脂、ロウ材等
の接着剤を介して接着固定される。1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 form a container 4 for housing the semiconductor element 3. The insulating substrate 1 is made of an aluminum nitride sintered body, and has a concave portion 1a for forming a space for accommodating the semiconductor element 3 on the upper surface thereof, and the semiconductor element 3 is made of glass, resin or the like on the bottom surface of the concave portion 1a. It is adhesively fixed through an adhesive such as a brazing material.
【0013】前記窒化アルミニウム質焼結体から成る絶
縁基体1 は例えば、窒化アルミニウム(AlN) 、イットリ
ア(Y2 O 3 ) 、カルシア(CaO) 、マグネシア(MgO) 等の
原料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状
となすとともにこれを従来周知のドクターブレード法や
カンレンダーロール法等を採用することによってセラミ
ックグリーンシート( セラミック生シート) を得、しか
る後、前記セラミックグリーンシートに適当な打ち抜き
加工を施すとともに複数枚積層し、高温( 約1800℃) で
焼成することによって製作される。The insulating substrate 1 made of the aluminum nitride sintered body is, for example, an organic solvent suitable for a raw material powder such as aluminum nitride (AlN), yttria (Y 2 O 3 ), calcia (CaO), magnesia (MgO). A ceramic green sheet (ceramic green sheet) is obtained by adding and mixing a solvent to form a slurry, and adopting the conventionally known doctor blade method, canender roll method, etc. It is manufactured by performing appropriate punching, stacking multiple sheets, and baking at high temperature (about 1800 ℃).
【0014】前記窒化アルミニウム質焼結体から成る絶
縁基体1 はその熱伝導率が50W/m ・K 以上であり、熱を
伝え易いことから半導体素子3 が作動時に多量の熱を発
生したとしてもその熱は絶縁基体1 を介して大気中に良
好に放散され、その結果、半導体素子3 は該素子3 自身
の発する熱によって高温になることは一切なく、半導体
素子3 に熱破壊や特性に熱変化を来し、誤動作を起こさ
せることはなくなる。Since the insulating substrate 1 made of the aluminum nitride sintered body has a thermal conductivity of 50 W / m · K or more and is easy to transfer heat, even if the semiconductor element 3 generates a large amount of heat during operation. The heat is satisfactorily dissipated into the atmosphere through the insulating substrate 1, and as a result, the semiconductor element 3 never rises in temperature due to the heat generated by the element 3 itself, and the semiconductor element 3 is not destroyed by thermal destruction or characteristics. It will not change and cause malfunctions.
【0015】また前記絶縁基体1 は凹部1a周辺から下面
にかけて複数個のメタライズ配線層5 が被着形成されて
おり、該メタライズ配線層5 の凹部1a周辺部には半導体
素子3 の各電極( 電源電極、接地電極、信号電極) がボ
ンディングワイヤ6 を介して電気的に接続され、また絶
縁基体1 の下面に導出された部位には外部電気回路と接
続される外部リード端子7 が銀ロウ等のロウ材を介して
取着されている。A plurality of metallized wiring layers 5 are deposited on the insulating substrate 1 from the periphery of the recess 1a to the lower surface, and the electrodes of the semiconductor element 3 (power supply) are formed in the periphery of the recess 1a of the metallized wiring layer 5. (Electrode, ground electrode, signal electrode) are electrically connected via the bonding wire 6, and the external lead terminal 7 connected to an external electric circuit is connected to an external electric circuit at a portion led out to the lower surface of the insulating substrate 1. It is attached via brazing material.
【0016】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当な有機溶剤、溶
媒を添加混合して得た金属ペーストを絶縁基体1 となる
セラミックグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から下面にかけて被着され
る。The metallized wiring layer 5 is made of tungsten,
A metal paste made of a refractory metal powder such as molybdenum or manganese, which is obtained by adding and mixing an appropriate organic solvent or a solvent to the refractory metal powder such as tungsten is previously known to the ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by the screen printing method, the insulating substrate 1 is deposited from around the recess 1a to the lower surface.
【0017】尚、前記メタライズ配線層5 はその露出表
面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ
性の良い金属をメッキ法により1.0 乃至20.0μm の厚み
に層着させておくとメタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 への外部リード端子の取着を強固となすことができ
る。従って、メタライズ配線層5 の酸化腐食を防止し、
メタライズ配線層5 とボンディングワイヤ6 及び外部リ
ード端子7 との取着を強固とするにはメタライズ配線層
5 の露出表面にニッケル、金等を1.0 乃至20.0μm の厚
みに層着させておくことが好ましい。The metallized wiring layer 5 is formed by depositing a metal such as nickel and gold, which has excellent corrosion resistance and has a good wettability with a brazing material, on the exposed surface by plating to a thickness of 1.0 to 20.0 μm. The metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
And bonding wire 6 and metallized wiring layer
It is possible to firmly attach the external lead terminal to 5. Therefore, the oxidation corrosion of the metallized wiring layer 5 is prevented,
To strengthen the attachment of the metallized wiring layer 5 to the bonding wires 6 and the external lead terminals 7, the metallized wiring layer
It is preferable to deposit nickel, gold or the like on the exposed surface of layer 5 in a thickness of 1.0 to 20.0 μm.
【0018】また前記メタライズ配線層5 に銀ロウ等の
ロウ材を介して取着される外部リード端子7 はコバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケル合金) 等の金属材料から成り、外部リード端子
7 を外部電気回路に接続することによって絶縁基体1 の
凹部1a内に収容される半導体素子3 の各電極はメタライ
ズ配線層5 及び外部リード端子7 を介して外部電気回路
に電気的に接続されることとなる。The external lead terminals 7 attached to the metallized wiring layer 5 via a brazing material such as silver braze are metal materials such as Kovar metal (iron-nickel-cobalt alloy) and 42 alloy (iron-nickel alloy). Consisting of an external lead terminal
Each electrode of the semiconductor element 3 housed in the recess 1a of the insulating substrate 1 by connecting 7 to the external electric circuit is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. It will be.
【0019】前記外部リード端子7 はコバール金属等の
インゴット( 塊) を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の形状
に形成される。The external lead terminal 7 is formed in a predetermined shape by adopting a conventionally known metal working method such as a rolling working method or a punching working method for an ingot (lump) of Kovar metal or the like.
【0020】また前記外部リード端子7 はその露出表面
にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性
の良い金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと外部リード端子7 の酸化腐食を有効に
防止することができるとともに外部リード端子7 を半田
等のロウ材を介し外部電気回路に強固に接続することが
可能となる。従って、前記外部リード端子7 はその露出
表面にニッケル、金等を1.0 乃至20.0μm の厚みに層着
させておくことが好ましい。Further, when the external lead terminal 7 is formed by depositing a metal such as nickel or gold, which has excellent corrosion resistance and has good wettability with the brazing material, to a thickness of 1.0 to 20.0 μm by plating. Oxidation and corrosion of the external lead terminals 7 can be effectively prevented, and the external lead terminals 7 can be firmly connected to an external electric circuit via a brazing material such as solder. Therefore, it is preferable that the exposed surface of the external lead terminal 7 is layered with nickel, gold or the like in a thickness of 1.0 to 20.0 μm.
【0021】前記絶縁基体1 はまたその上面に図2 に示
す如く凹部1bが形成されており、該凹部1bの底面には絶
縁基体1 の内部から延出し、半導体素子3 の電源電極及
び接地電極に電気的に接続されている接続パッド5aが形
成されている。The insulating base 1 also has a recess 1b formed on the upper surface thereof as shown in FIG. 2, and the bottom surface of the recess 1b extends from the inside of the insulating base 1 to provide a power electrode and a ground electrode for the semiconductor element 3. A connection pad 5a electrically connected to is formed.
【0022】前記絶縁基体1 の凹部1bには容量素子8 が
その電極を接続パッド5aに半田等のロウ材を介し接合さ
せることによって取着収容され、これによって容量素子
8 が半導体素子3 の電源電極と接地電極の間に接続され
ることとなる。The capacitive element 8 is attached and housed in the concave portion 1b of the insulating substrate 1 by joining its electrode to the connection pad 5a via a brazing material such as solder.
8 is connected between the power supply electrode and the ground electrode of the semiconductor element 3.
【0023】前記容量素子8 は絶縁基体1 の凹部1b内に
収容されることから容量素子8 に外力が印加されること
は殆どなく、外力印加によって容量素子8 が接続パッド
5aより外れることが有効に防止される。Since the capacitance element 8 is housed in the recess 1b of the insulating substrate 1, almost no external force is applied to the capacitance element 8, and the capacitance element 8 is connected to the connection pad by the external force application.
It is effectively prevented from deviating from 5a.
【0024】また前記容量素子8 が接合される接続パッ
ド5aは絶縁基体1 より延出し、一部が絶縁基体1 内に埋
入されていることから接続パッド5aに容量素子8 をロウ
材を介して取着させる際、絶縁基体1 と容量素子8 との
間に両者の熱膨張係数の相違に起因する大きな熱応力が
発生し、これが絶縁基体1 と接続パッド8 の接合部に内
在して絶縁基体1 と接続パッド8 との接合強度が低下し
たとしてもその接合強度は補強されて極めて強固なもの
となり、その結果、容量素子8 に外力が印加されても容
量素子8 が接続パッド5aとともに絶縁基体1 より外れる
ことはなく、容量素子8 によって半導体素子3 への電源
ノイズの悪影響を有効に防止することができる。Further, the connection pad 5a to which the capacitance element 8 is joined extends from the insulating base 1 and is partially embedded in the insulating base 1, so that the capacitance element 8 is connected to the connection pad 5a via a brazing material. When they are attached together, a large thermal stress is generated between the insulating base 1 and the capacitive element 8 due to the difference in the thermal expansion coefficient between them, and this causes internal insulation at the joint between the insulating base 1 and the connection pad 8. Even if the bonding strength between the base 1 and the connection pad 8 is reduced, the bonding strength is reinforced and becomes extremely strong. As a result, even if an external force is applied to the capacitive element 8, the capacitive element 8 is insulated together with the connection pad 5a. It does not come off from the base 1, and the capacitive element 8 can effectively prevent the adverse effect of power source noise on the semiconductor element 3.
【0025】尚、前記容量素子8 を収容する凹部1bは絶
縁基体1 と成るセラミックグリーンシートに予め打ち抜
き加工法により穴を形成しておくことによって絶縁基体
1 の上面に形成され、また接続パッド5aはタングステ
ン、モリブデン、マンガン等の高融点金属粉末より成
り、メタライズ配線層5 と同様の方法によって絶縁基体
1の凹部1b底面に所定形状に形成される。The concave portion 1b for accommodating the capacitive element 8 is formed by forming a hole in the ceramic green sheet to be the insulating substrate 1 in advance by a punching method.
1 is formed on the upper surface, and the connection pad 5a is made of a refractory metal powder such as tungsten, molybdenum, or manganese.
It is formed in a predetermined shape on the bottom surface of the concave portion 1b of 1.
【0026】また前記接続パッド5aに取着される容量素
子8 は例えば、チタン酸バリウム磁器内に対向電極を多
数埋設して形成され、該容量素子8 は半導体素子3 の誤
動作の原因となる供給電源電圧の変動に起因する電源ノ
イズを除去する作用を為し、これによって半導体素子3
は電源ノイズの悪影響から保護され、長期間にわたり正
常、且つ安定に作動することが可能となる。The capacitive element 8 attached to the connection pad 5a is formed, for example, by embedding a large number of counter electrodes in a barium titanate porcelain, and the capacitive element 8 supplies the semiconductor element 3 causing malfunction. It acts to eliminate power supply noise caused by fluctuations in the power supply voltage, which allows the semiconductor element 3
Is protected from the adverse effects of power supply noise and can operate normally and stably for a long period of time.
【0027】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部1a底面に半導体素子3 を
ガラス、樹脂、ロウ材等の接着剤を介して接着固定する
とともに半導体素子3 の各電極をメタライズ配線層5 に
ボンディングワイヤ6 を介して電気的に接続し、しかる
後、絶縁基体1 の上面に蓋体2 をガラス、樹脂、ロウ材
等から成る封止材を介して接合させ、絶縁基体1 と蓋体
2 とから成る容器4 内部に半導体素子3 を気密に収容す
ることによって製品としての半導体装置が完成する。Thus, according to the package for accommodating semiconductor elements of the present invention, the semiconductor element 3 is adhered and fixed to the bottom surface of the concave portion 1a of the insulating substrate 1 through an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 3 is attached. Are electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is bonded to the upper surface of the insulating substrate 1 via a sealing material made of glass, resin, brazing material, etc. Base 1 and lid
A semiconductor device as a product is completed by hermetically housing the semiconductor element 3 in a container 4 composed of 2 and.
【0028】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.
【0029】[0029]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁容器を窒化アルミニウム質焼結体で形成し
たことから半導体素子の作動時に発する熱は容器を介し
て大気中に良好に放散され、その結果、容器内部に収容
される半導体素子は常に低温となり、半導体素子を長期
間にわたり正常、且つ安定に作動させることができる。According to the package for housing a semiconductor device of the present invention, since the insulating container is made of an aluminum nitride sintered material, the heat generated during the operation of the semiconductor device is well dissipated into the atmosphere through the container. As a result, the temperature of the semiconductor element housed inside the container is always low, and the semiconductor element can be operated normally and stably for a long period of time.
【0030】また絶縁容器の外表面に設けた凹部内に容
量素子を収容し、容量素子に外力が印加されるのを有効
に防止するとともに容量素子が接続される接続パッドの
一部を絶縁容器内に埋入させ接続パッドと絶縁容器の接
合を補強したことから容量素子に外力が印加され、容量
素子が接続パッドとともに絶縁容器より外れることは皆
無となり、その結果、容量素子によって半導体素子への
電源ノイズの悪影響を有効に防止することができる。Further, the capacitive element is housed in the concave portion provided on the outer surface of the insulating container to effectively prevent the external force from being applied to the capacitive element, and a part of the connection pad to which the capacitive element is connected is insulated from the insulating container. Since the connection between the connection pad and the insulating container was reinforced by embedding it in the inside, external force was applied to the capacitive element, and the capacitive element and the connection pad did not come off from the insulating container at all. It is possible to effectively prevent the adverse effect of power supply noise.
【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.
【図2】図1に示すパッケージの要部拡大断面図であ
る。FIG. 2 is an enlarged cross-sectional view of a main part of the package shown in FIG.
【図3】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.
1・・・・絶縁基体 1b・・・凹部 2・・・・蓋体 3・・・・半導体素子 4・・・・容器 5・・・・メタライズ配線層 5a・・・接続パッド 7・・・・外部リード端子 8・・・・容量素子 1 ... Insulating substrate 1b ... Recess 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallized wiring layer 5a ... Connection pad 7 ...・ External lead terminal 8 ・ ・ ・ ・ Capacitance element
Claims (1)
有する窒化アルミニウム質焼結体から成る絶縁容器に、
内部に収容する半導体素子の電源電極及び接地電極に接
続される接続パッドを形成するとともに該接続パッドに
容量素子を取着して成る半導体素子収納用パッケージで
あって、前記絶縁容器の外表面に容量素子を収容する凹
部を設けるとともに該凹部底面に接続パッドがその一部
を絶縁容器中に埋入させた状態で形成されていることを
特徴とする半導体素子収納用パッケージ。1. An insulating container made of an aluminum nitride sintered body having a cavity for housing a semiconductor element therein.
A package for storing a semiconductor element, which is formed by forming a connection pad connected to a power electrode and a ground electrode of a semiconductor element housed inside and mounting a capacitance element on the connection pad, the package being provided on an outer surface of the insulating container A package for storing a semiconductor element, characterized in that a concave portion for accommodating a capacitive element is provided and a connection pad is formed on a bottom surface of the concave portion with a part thereof embedded in an insulating container.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5025192A JPH06244301A (en) | 1993-02-15 | 1993-02-15 | Package for containing semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5025192A JPH06244301A (en) | 1993-02-15 | 1993-02-15 | Package for containing semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06244301A true JPH06244301A (en) | 1994-09-02 |
Family
ID=12159106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5025192A Pending JPH06244301A (en) | 1993-02-15 | 1993-02-15 | Package for containing semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06244301A (en) |
-
1993
- 1993-02-15 JP JP5025192A patent/JPH06244301A/en active Pending
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