JP2777016B2 - Package for storing semiconductor elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.

[0002]

2. Description of the Related Art Heretofore, as a semiconductor device housing package for housing a semiconductor device, a package having a capacitor for removing power supply noise has been used. As shown in FIG. 2, the conventional package for housing a semiconductor element mainly includes an insulating base 21, a capacitor 22, and a lid 23.
It is composed of

The insulating base 21 is made of an electrically insulating material such as alumina ceramics, and has a recess 21A for forming a cavity for accommodating a semiconductor element formed substantially at the center of the upper surface thereof. Metallized wiring layers 24 and recesses 21A extending from the upper part to the outer peripheral part of the upper surface
A capacitor element connection pad 25 is formed on the bottom surface and electrically connected to a part of the metallized wiring layer 24.

The capacitive element 22 is, for example, a flat plate capacitor using barium titanate porcelain as a dielectric material. The capacitive element 22 has an upper electrode 22a and a lower part 22b on upper and lower surfaces thereof. It is attached to the bottom of the concave portion 21A of the insulating base 21 through the intermediary. Thus, the lower electrode 22b of the capacitance element 22 is electrically connected to the capacitance element connection pad 25 of the insulating base 21.

A semiconductor element 27 is attached and fixed to the upper surface of the capacitive element 22 via an adhesive such as glass, resin, solder or the like. Each electrode of the semiconductor element 27 is connected to a metallized wiring layer via a bonding wire 28. 24 is electrically connected.

A part of the bonding wire 28 is connected to the upper electrode 22a of the capacitive element 22, and the capacitive element 22 is connected to the semiconductor element 22 via the bonding wire 28 in parallel.

However, in this conventional package for accommodating a semiconductor element, the thermal expansion coefficient of each of the alumina ceramics constituting the insulating base and the barium titanate porcelain constituting the capacitive element is about 6.5 × 10 ^-6 / ° C. About 11.0
Since it is × 10 ⁻⁶ / ° C., which is a great difference, heat is applied to the insulating base and the capacitive element when the capacitive element is attached to the bottom of the concave portion of the insulating base or when the semiconductor element housed inside is operated. As a result, the capacitive element expands more than the insulating base, and as a result, a stress is generated between the insulating base and the capacitive element due to the difference in the amount of thermal expansion, and the stress causes the capacitive element to expand. This has the disadvantage that the film is more peeled off and cracks, chips, cracks and the like are generated in the capacitor.

Accordingly, the present inventors have proposed that a capacitor having a thermal expansion coefficient of about 6.5 × 10 ⁻⁶ / ° C. be attached to an insulating substrate.
And a capacitor having a substrate made of tantalum (Ta) having substantially the same thermal expansion coefficient as alumina ceramics constituting an insulating substrate, and a dielectric layer made of tantalum oxide formed on the surface of the substrate by anodization. It was investigated.

However, the tantalum is used as a base,
When a capacitor having a dielectric layer made of tantalum oxide formed on its surface by anodization, the capacitor is attached and fixed to the bottom of the concave portion of the insulating base via a high melting point brazing material such as silver brazing. Oxygen in the dielectric layer diffuses into the substrate due to heat at the time of fixing, resulting in a disadvantage that the insulation resistance of the capacitor is reduced.

[0010]

SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to prevent the capacitive element from being peeled off from the insulating base, and the capacitive element from being chipped, cracked or cracked. Another object of the present invention is to provide a package for housing a semiconductor element which incorporates a capacitor without lowering the insulation characteristics of the capacitor.

[0011]

According to the present invention, there is provided a semiconductor device housing package comprising a cover and an insulating base having a recess for housing a semiconductor element. And a capacitor having a dielectric layer made of tantalum oxide formed on the surface thereof by anodization, and fixed by a brazing material or a conductive resin having a melting point of 400 ° C. or less.

[0012]

According to the semiconductor device housing package of the present invention, the thermal expansion coefficient of tantalum constituting the capacitive element is about 6.5 × 1.
0 ⁻⁶ / ° C., which substantially coincides with the coefficient of thermal expansion of the alumina ceramics constituting the insulating substrate, so that stress due to the difference in the coefficient of thermal expansion between the two hardly occurs. Also, since the capacitive element is attached to the insulating base with a low melting point brazing material or a conductive resin having a melting point of 400 ° C. or less, when attaching the capacitive element to the insulating base, it is attached and fixed at a low temperature of about 400 ° C. or less. Therefore, a large thermal stress is not applied to the capacitor.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention. 1 is an insulating base, 2 is a capacitor, and 3 is a lid. The insulating base 1 and the lid 3 constitute a container 4 for housing the semiconductor element 5.

The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, and has a concave portion 1A for forming a space for accommodating a semiconductor element at a substantially central portion of the upper surface. The capacitive element 2 and the semiconductor element 5 are attached and fixed to the bottom surface.

A plurality of metallized wiring layers 6 made of a refractory metal such as tungsten or molybdenum are formed on the insulating substrate 1 from the periphery of the concave portion 1A to the outer peripheral portion of the upper surface, and the concave portion 1A of the metallized wiring layer 6 is formed. In the periphery, each electrode of the semiconductor element 5 is electrically connected via a bonding wire 8.
An external lead terminal 7 connected to an external electric circuit is attached via a brazing material such as silver brazing to a portion leading to the outer peripheral portion of the upper surface.

Further, the insulating base 1 is electrically connected to a part of the metallized wiring layer 6 and is a pad for connecting a capacitive element made of a refractory metal powder such as tungsten or molybdenum, which is exposed on the bottom surface of the recess 1A of the insulating base 1. 9a and 9b are formed.

The capacitive element connecting pad 9a is formed in a frame shape on the outer periphery of the bottom surface of the concave portion 1A of the insulating base 1, and the capacitive element connecting pad 9b is electrically independent from the capacitive element connecting pad 9a. In this state, it is formed in a rectangular shape at the center of the concave bottom surface 1A of the insulating base 1. The electrodes of the capacitive element 2 are electrically connected to the capacitive element connecting pads 9a and 9b.

The exposed surfaces of the metallized wiring layer 6 and the capacitor element connecting pads 9a and 9b are coated with a metal having excellent corrosion resistance such as nickel or gold and a good conductivity by 1.0 to 20 by a plating method. If the metallized wiring layer 6 and the capacitor element connection pad 9 are layered to a thickness of 0.0 μm.
a, 9b can be effectively prevented from being oxidized and corroded, and the connection between the metallized wiring layer 6 and the external lead terminal 7 and the connection between the metallized wiring layer 6 and the bonding wire 8 can be effectively prevented.
And the connection between the capacitive element connection pads 9a and 9b and the capacitive element 2 becomes extremely strong. Therefore, the metallized wiring layer 6 and the capacitor element connection pads 9a,
9b has excellent corrosion resistance of nickel, gold, etc. on its exposed surface,
In addition, a metal having good conductivity is used in an amount of 1.0 to 20.
It is preferable to apply a layer to a thickness of 0 μm.

When the insulating substrate 1 having the metallized wiring layer 6 and the pads 9a and 9b for connecting capacitance elements is made of, for example, a sintered body of aluminum oxide, alumina (Al) is used.
₂ O ₃ ), silica (SiO ₂ ), calcia (CaO), magnesia (MgO), and other suitable powders are mixed with a suitable binder and solvent to form a slurry, which is then formed into a slurry by a well-known doctor blade method or calendar. A plurality of ceramic green sheets (ceramic green sheets) are obtained by employing a roll method or the like.
(Approximately 1600 ° C.), and the metallized wiring layer 6 and the capacitor connecting pads 9a and 9b formed on the insulating substrate 1 are made of an organic binder suitable for a high melting point metal powder such as tungsten or molybdenum. A metal paste obtained by adding and mixing a solvent is applied to a ceramic green sheet serving as the insulating substrate 1 in a predetermined shape by applying a known thick film method such as a screen printing method in advance to a predetermined shape on the insulating substrate 1. It is formed into a pattern.

The capacitor element connection pads 9 on the insulating base 1
The electrodes of the capacitive element 2 are electrically connected to the electrodes a and 9b via the low melting point brazing material 10, whereby the electrode of the capacitive element 2 is connected between the power supply electrode and the ground electrode of the semiconductor element. That is, the capacitive element 2 removes power supply noise caused by the fluctuation of the supply power supply voltage which causes the malfunction of the semiconductor element.

The capacitive element 2 is formed by depositing a dielectric layer 2b made of tantalum oxide having a thickness of 1000 to 7000 angstroms on the lower surface of a rectangular flat base 2a made of tantalum and having a thickness of 0.1 to 1.0 mm. It is configured.

Since the capacitance element 2 has a base 2a made of tantalum having a thermal expansion coefficient of about 6.5 × 10 ⁻⁶ / ° C., the thermal expansion coefficient of the alumina ceramic constituting the insulating base 1 is 6.5 × 10 ^-6 / ° C.
A stress due to a difference in thermal expansion coefficient between the two hardly acts.

The dielectric layer 2b is formed by anodizing the lower surface of the base 2a made of tantalum. Specifically, the base 2a made of tantalum and a platinum plate are immersed in an electrolyte such as citric acid. And the substrate 2
a is connected to the anode of the DC power supply, the platinum plate is connected to the cathode,
Next, 100 to 350 V is applied between the base 2a and the platinum plate.
Is applied to oxidize the surface of the base 2a. In this case, if the lower surface of the base 2a is set to have a center line average roughness (Ra) of Ra <50 nm, the base 2
The dielectric layer 2b having a substantially uniform thickness can be formed on the lower surface of the capacitor a. As a result, it is possible to improve the withstand voltage characteristic and the insulation characteristic of the capacitor element 2 and obtain a large capacitance. Therefore, it is preferable that the surface roughness of the base 2a made of tantalum be Ra <50 nm on the lower surface in terms of center line average roughness (Ra).

The thickness of the dielectric layer 2b varies depending on the capacitance value desired for the capacitance element. If the thickness is less than 1000 Å, the withstand voltage characteristic and the insulation characteristic of the capacitance element 2 tend to deteriorate. Therefore, the dielectric layer 2b
It is preferable that the thickness be 1000 Å or more.

The capacitive element 2 has an inner electrode layer 2c and an outer electrode having a two-layer structure of a first metal layer made of nickel-chromium and a second metal layer made of gold on the lower surface of the dielectric layer 2b. The layers 2d are formed at predetermined intervals.

The inner electrode layer 2c and the outer electrode layer 2d have shapes corresponding to the capacitive element connecting pads 9a and 9b of the insulating substrate 1, and the outer electrode 2d is
Is electrically connected to the base 2a.

The inner electrode layer 2c and the outer electrode 2d
Between the inner electrode layer 2c and the outer electrode 2d, via the low melting point brazing material 10, the capacitive element connection pads 9 of the insulating base 1.
a and 9b, respectively.

The first metal layer made of nickel-chromium constituting the inner electrodes 2c and 2d is applied to a thickness of 100 to 2000 angstroms by a conventionally known vapor deposition method, and the second metal layer made of gold is used. The metal layer is deposited to a thickness of 1000 to 4000 angstroms by a well-known plating method.

The low melting point brazing material 10 for attaching and bonding the capacitive element 2 to the insulating base 1 is a brazing material having a melting point of 400 ° C. or more, specifically, a gold-tin alloy, a gold-germanium alloy, It is made of a low melting point alloy such as a gold-silicon alloy. For example, when it is made of a gold-tin alloy, its melting point is about 280 ° C.

Further, in order to attach the capacitive element 2 to the insulating base 1 using the low melting point brazing material 10 made of the gold-tin alloy, it is necessary to use a gold having a shape corresponding to the shape of the capacitive element connection pads 9a and 9b. Preparing a brazing filler metal preform (sheet-like molded body) made of a tin alloy, placing the brazing filler metal preform on the capacitive element connection pads 9a and 9b, and further placing the capacitive element 2 thereon; Is heated to a temperature of about 300 ° C. to melt the brazing material preform. At this time, the brazing material 1 made of the gold-tin alloy is used.
0 has a low melting point of about 280 ° C. or less,
It is not necessary to apply a high temperature when the capacitive element 2 is bonded to the insulating base 1, and therefore, there is almost no deterioration in the insulating characteristics of the capacitive element 2.

A semiconductor element 5 is also provided on the upper surface of the capacitive element.
Are fixedly attached via an adhesive such as solder or resin, and each electrode of the semiconductor element 5 is electrically connected to the metallized wiring layer 6 via a bonding wire 8.

On the other hand, external lead terminals 7 are provided on the upper surface of the metallized wiring layer 6 of the insulating substrate 1 to which the above-mentioned capacitance element is fixed.
The external lead terminal 7 is formed of a metal such as Kovar metal (Fe-Ni-Co alloy) or 42 alloy (Fe-Ni alloy), and one end thereof is used as a wiring conductor of an external electric circuit board. The semiconductor element 5 housed therein is electrically connected to an external electric circuit by connecting via a conductive adhesive such as solder.

The external lead terminal 7 is formed by plating a metal having excellent corrosion resistance such as nickel and gold and having excellent wettability with solder to a thickness of 1.0 to 20.0 μm on the outer surface thereof by plating. By doing so, it is possible to effectively prevent the external lead terminals 7 from being oxidized and corroded, and the connection of the external lead terminals 7 to the external electric circuit board becomes extremely strong. Therefore, in order to effectively prevent the external lead terminal 7 from being oxidized and corroded and to make the connection of the external lead terminal 7 to the external electric circuit board firm, the external lead terminal 7 is made of nickel, It is preferable that a metal such as gold having excellent corrosion resistance and excellent wettability with solder is layered to a thickness of 1.0 to 20.0 μm by plating.

The external lead terminal 7 is formed in a predetermined plate shape by employing a conventionally known metal working method such as rolling or pressing an ingot made of Kovar metal or the like.

Further, a lid 3 made of metal such as Kovar or ceramics similar to the insulating base 1 is provided on the upper surface of the insulating base 1.
Are bonded via a sealing material such as solder or resin, whereby the space formed by the recess 3A of the lid 3 and the insulating base 1 is hermetically sealed.

Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 5 is attached and fixed via an adhesive to the upper surface of the capacitor element 2 attached to the bottom surface of the concave portion 1A of the insulating base 1. 5 are connected to the metallized wiring layer 6 via bonding wires 8, and finally the lid 3 is joined to the upper surface of the insulating base 1 via a sealing material such as solder or resin, thereby forming a semiconductor therein. A semiconductor device for hermetically sealing the element 5 is obtained.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Although the low-melting point brazing material is used for attachment to the substrate, a conductive resin such as silver-polyimide may be used instead of the low-melting point brazing material.

[0038]

According to the package for housing a semiconductor element of the present invention, the base of the capacitor is made of tantalum having a coefficient of thermal expansion close to that of the alumina ceramic constituting the insulating base of the package for housing the semiconductor element. Therefore, even if heat is applied to both of the capacitors after attaching and fixing the capacitors to the insulating base, there is almost no stress between the two due to the difference in the coefficient of thermal expansion. Can always be firmly fixed to the insulating base, and cracks, chips, and cracks can be eliminated from the capacitance element.

In the package for housing a semiconductor element according to the present invention, the capacitor is attached to the insulating base through a low melting point brazing material having a melting point of 400 ° C. or less. The thermal stress applied to the capacitance element is small, and therefore, it hardly causes the deterioration of the insulation characteristics of the capacitance element.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

FIG. 2 is a cross-sectional view illustrating a conventional semiconductor element storage package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Capacitance element 2a ... Base 2b ... Dielectric 2c ... Inner electrode 2d ... Outer electrode 3 ... Lid 5 ... Semiconductor element 6 ... Metallized wiring layer 9a, 9b... Pads for connecting capacitive elements

Claims (1)

(57) [Claims] 1. A semiconductor element housing package comprising an insulating base having a recess for housing a semiconductor element and a lid, wherein the insulating base has a bottom surface made of tantalum and a surface made of tantalum oxide. A package for housing a semiconductor element, wherein a capacitive element having a dielectric layer formed by anodization is attached and fixed with a brazing material or a conductive resin having a melting point of 400 ° C. or less.