JPH06208131A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To correct a line defect perfectly even in the case where a short circuit and a disconnection is generated at an intersection part of a scanning signal line and an image signal line by providing a bypass in the scanning signal line, which also works as a gate electrode of a thin film transistor, for each picture element. CONSTITUTION:A bypass GBP is provided in a scanning signal line GL per each picture element, and this bypass GBP is divided from the scanning signal line GL in the upstream side of a first intersection part SH1 of the scanning signal line GL and the image signal line DL, and combined with the scanning signal line GL in the downstream side of a second intersection part SH2 of the bypass GBP and the image signal line DL and a thin film transistor TFT. Since the bypass GBP is provided in the scanning signal line GL per each picture element and the scanning signal line GL and the bypass GBP form a closed loop, which is connected to an external circuit, per each picture element, in the case where a short circuit is generated in the closed loop, connection to the external circuit is secured even in the case where any part of the closed loop is cut by laser or the like, and a line defect can be corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device having a thin film transistor and a pixel electrode as a constituent element of one pixel, and more particularly, to display by short circuit or disconnection by providing a bypass to a signal line. The present invention relates to a technology capable of correcting a screen defect.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal display device. Then it is becoming an indispensable technology. A typical example of the switching element is a thin film transistor (TFT).

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, "12.5 type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics, p.
No. 210, December 15, 1986, published by Nikkei McGraw-Hill, Inc., and JP-A-61-151516.

In the liquid crystal display unit (liquid crystal display panel), a thin film transistor, a transparent pixel electrode, a protective film for the thin film transistor, and a lower alignment film for setting the orientation of liquid crystal molecules are sequentially provided on a lower transparent glass substrate with a liquid crystal layer as a reference. The lower transparent substrate and the upper transparent glass substrate, on which the black matrix, the color filter, the protective film for the color filter, the common transparent pixel electrode, and the upper alignment film are sequentially provided on the upper transparent glass substrate, are stacked so that their alignment films face each other In addition, both substrates are adhered by a sealing material arranged around the edges of the substrates, liquid crystal is sealed between both substrates, and a polarizing plate is installed or attached on the outside of both substrates. A backlight is arranged on one of the substrates.

Further, the liquid crystal display portion extends in the horizontal direction,
And a plurality of scanning signal lines arranged in the vertical direction, a plurality of video signal lines extending in the vertical direction and arranged in the horizontal direction, and two adjacent scanning signal lines adjacent to each other. It has a thin film transistor and a pixel electrode respectively arranged in the intersection region with the video signal line, and the thin film transistor and the pixel electrode are constituent elements of one pixel.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention A crossing portion of a scanning signal line and a video signal line which intersect each other vertically, or a portion where the scanning signal line and the video signal line are superposed (that is, in the thin film transistor portion, the scanning signal line The gate electrode integrated with the video signal line and the drain electrode integrated with the video signal line are overlapped), the scanning signal line and the video signal line or the gate electrode and the source or drain electrode through the insulating layer. Are insulated, but due to pinholes, foreign matter, steps, etc. in the insulating film, the scan signal line and the video signal line, the gate electrode and the source or drain electrode are short-circuited, or the video signal line and the scan signal are There is a problem that line breakage occurs and vertical and horizontal cross-shaped line defects occur on the display screen. The short circuit in the latter part, that is, the short circuit between the gate electrode and the source or drain electrode of the thin film transistor section, by cutting both sides of the short circuit section with a laser, it is not possible to correct the line defect into a point defect. However, a line defect due to a short circuit or disconnection at the intersection of the scanning signal line and the video signal line cannot be corrected.

A bypass (sub path) is provided in the original signal line of the scanning signal line or the video signal line so as to be able to correct when a short circuit or disconnection occurs, and when a short circuit occurs, the original signal line or bypass A structure has been proposed in which any one of the appropriate portions is cut to electrically separate the short-circuited portion to correct the line defect. If a disconnection occurs in either the signal line or the bypass, the signal flows through the line that is not disconnected, so no correction is necessary. These are disclosed, for example, in JP-A-61-249078, JP-A-63-221325, Jpn.
134341, JP-A-1-134342, JP-A 1-1
34343, JP-A-1-134344, JP-A 1-13
4345, JP-A-1-284831, and JP-A-2-48831.
No. 2521. However, all these devices do not have a storage capacitor element. The storage capacitor element can reduce the direct current component added to the liquid crystal at the time of switching the thin film transistor, which causes the shortening of the life of the liquid crystal and the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched. In addition, the storage capacitor element also has the effect of prolonging the discharge time, and stores the image information for a long time after the thin film transistor is turned off.

Further, Japanese Patent Laid-Open No. 64-62617 discloses a device provided with a bypass and a storage capacitor element. However, in this device, the storage capacitor element is not provided in the bypass portion. Therefore, when a short circuit occurs in the storage capacitor element portion, the short circuit portion cannot be corrected, and since the structure does not serve as both the bypass and the storage capacitor element, the aperture ratio is low.

An object of the present invention is to provide a liquid crystal display device capable of completely correcting a line defect even if a short circuit or a disconnection occurs at any intersection of a scanning signal line and a video signal line or at an overlapping portion. To do.

Another object of the present invention is to provide a storage capacitor element that can reduce the direct current component that causes the shortening of the life of the liquid crystal and image sticking of the screen and can prolong the discharge time, and also provide a storage capacitor element portion. An object of the present invention is to provide a liquid crystal display device capable of correcting a short circuit that has occurred.

Still another object of the present invention is to provide a liquid crystal display device which can improve the aperture ratio by using both the bypass and the storage capacitor element.

[0012]

In order to solve the above-mentioned problems, the present invention provides a bypass for each scanning pixel line that also serves as a gate electrode of the above-mentioned thin film transistor, and provides the scanning signal line and the bypass. By forming a closed loop connected to an external circuit for each pixel, the video signal line intersects with the closed loop at a plurality of points, and the pixel electrode is one electrode, and the bypass of the adjacent pixel is the other. There is provided a liquid crystal display device in which a storage capacitor element serving as the electrode is formed to serve as both the bypass and the storage capacitor element.

The present invention also provides a liquid crystal display device in which the source electrode is arranged in the same direction as the drain electrode integrated with the video signal line in the thin film transistors of all the pixels.

[0014]

In the present invention, since the scanning signal line also serves as the gate electrode of the thin film transistor, the aperture ratio can be improved.

A bypass is provided for each pixel in the scanning signal line, and a closed loop connected to an external circuit is formed for each pixel by the scanning signal line and the bypass. Therefore, when a short circuit occurs in the closed loop, a laser or the like is used. You can fix line defects by connecting to an external circuit wherever you close the loop. Even if a disconnection occurs in the scanning signal line forming the closed loop, the scanning signal passes through the bypass and no line defect occurs.
Further, even if a disconnection occurs in the bypass forming the closed loop, the scanning signal passes through the main path of the scanning signal line, and no line defect occurs.

Since the video signal line intersects with the closed loop at a plurality of points, intersections of the scanning signal line and the video signal line at a plurality of points or overlapping portions (that is, in the thin film transistor portion, integrated with the scanning signal line). Even if a short circuit occurs in any part of a part where a certain gate electrode and a drain electrode integrated with a video signal line are overlapped, the line defect can be completely corrected by cutting the closed loops on both sides of the short circuit part. .

Since the storage capacitor element having the pixel electrode as one electrode and the bypass of the adjacent pixel as the other electrode is formed, when a short circuit occurs in the storage capacitor element portion, the bypass on both sides of the short circuit portion is disconnected. By doing so, the short-circuited portion is electrically separated, and the point defect due to the short-circuiting of the storage capacitor element portion can be corrected.

Since the bypass serves also as the storage capacitor, the aperture ratio can be improved.

In the thin film transistors of all the pixels, since the source electrode is arranged in the same direction as the drain electrode integrated with the video signal line, misalignment of the mask for forming the thin film transistor in the horizontal direction or the vertical direction. Even if occurs, the change in the overlapping state of the source or drain electrode of the thin film transistor is the same for all pixels, so that the variation in the characteristics of the thin film transistor can be prevented.

[0020]

【Example】

(Active Matrix Liquid Crystal Display Device) An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

FIG. 1 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line 3-3 of FIG. 3 is a sectional view taken along section line 4-4 of FIG. Further, FIG. 4 shows a plan view when a plurality of pixels shown in FIG. 1 are arranged.

(Pixel Arrangement) In FIG. 1, TFT is a thin film transistor, ITO1 is a transparent pixel electrode, GL is a scanning signal line, GBP is a bypass (sub path) of the scanning signal line GL,
DL is a video signal line, SH1, SH2, SH3 are portions where short circuit (or disconnection) is likely to occur and line defects are likely to occur (referred to as short circuit occurrence portion), and SH1 is a signal line between the scanning signal line GL and the video signal line DL. The first intersecting portion, SH2 is the second intersecting portion where the bypass GBP of the scanning signal line GL and the video signal line DL intersect, SH3 is the scanning signal line GL and the video signal line DL.
And the gate electrode GT integrated with the scanning signal line GL and the drain electrode SD1 integrated with the video signal line DL in the thin film transistor TFT. RTL1, R
TL2 and RTL3 are laser trimming portions that are cut by using a laser. Note that, in FIG. 1, for easy understanding, the scanning signal line GL is provided with a diagonal line rising to the right, and the video signal line DL is provided with a diagonal line descending to the right.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And an adjacent two video signal lines (drain signal line or vertical signal line) DL are intersected with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd (described in detail later). Scan signal line G
L extends in the column direction and a plurality of L's are arranged in the row direction.
The video signal lines DL extend in the row direction and a plurality of video signal lines DL are arranged in the column direction.

In this embodiment, as shown in FIG. 1, a scanning signal line GL is provided with a bypass GBP for each pixel, and this bypass GBP is at a first intersection between the scanning signal line GL and the video signal line DL. It branches from the scanning signal line GL on the upstream side of SH1 and joins the scanning signal line GL on the downstream side of the second intersection SH2 of the bypass GBP and the video signal line DL and the thin film transistor TFT.

That is, in this embodiment, as shown in FIG. 1, the scanning signal line GL and the gate electrode GT of the thin film transistor TFT are used in common, so that the aperture ratio can be improved.

Since a bypass GBP is provided for each pixel on the scanning signal line GL and a closed loop connected to an external circuit is formed for each pixel by the scanning signal line GL and the bypass GBP, when a short circuit occurs in the closed loop, No matter where the closed loop is cut using a laser or the like, the line is connected to an external circuit and a line defect can be repaired. In addition, the scanning signal line G forming the closed loop
Even if a disconnection occurs in L, the scanning signal passes through the bypass GBP and no line defect occurs. Further, even if a disconnection occurs in the bypass GBP forming the closed loop, the scanning signal passes through the main path of the scanning signal line GL and no line defect occurs.

Since the video signal line DL intersects with the closed loop at two points, the intersection of the two points of the scanning signal line GL and the video signal line DL or the overlapped portion (that is, the scanning signal in the thin film transistor TFT section). The closed loop on both sides of the short-circuited portion should be cut even if a short-circuit occurs in any part of a portion where the gate electrode GT integrated with the line GL and the drain electrode SD1 integrated with the video signal line DL are overlapped). The line defect can be completely corrected by.

That is, first, when a short circuit between the scanning signal line GL and the video signal line DL occurs at the first intersection SH1, both sides of the first intersection SH1 (first intersection SH).
By cutting the scanning signal lines GL (upstream side and downstream side of 1) using a laser as shown by laser trimming portions RTL1 and RTL2, the short-circuit portion is electrically disconnected, and the scanning signal bypasses the bypass GBP. Yes, line defects can be fixed. Further, even if a disconnection occurs at the first intersection SH1, the scanning signal passes through the bypass GBP and the line defect does not occur.

Secondly, when a short circuit occurs between the scanning signal line GL and the video signal line DL at the second intersection SH2, both sides of the second intersection SH2 (upstream of the second intersection SH2). Side and downstream) bypass GBP is cut using a laser as shown by laser trimming portions RTL3, RTL4, the short-circuit portion is electrically cut off, and the scanning signal passes through the main path of the scanning signal line GL. Yes, line defects can be fixed. Further, even if a disconnection occurs at the second intersection SH2, the scanning signal passes through the main path of the scanning signal line GL and no line defect occurs.

Thirdly, in the thin film transistor TFT, when a short circuit occurs between the gate electrode GT integrated with the scanning signal line GL and the drain electrode SD1 integrated with the video signal line DL, the first crossing portion The scanning signal lines GL on both sides of the SH1 and the thin film transistor TFT (upstream side of the first intersection SH1 and downstream side of the thin film transistor TFT) are processed by using a laser, for example, a laser trimming portion RTL.
1, by cutting as shown by RTL5, the short-circuited portion (thin film transistor TFT) is electrically separated, and the scanning signal passes through the bypass GBP, and the point defect of the pixel having the short-circuited thin film transistor TFT is eliminated. Defects can be repaired into point defects.

The gate electrode GT which is integral with the scanning signal line GL and the source electrode S which is not integral with the video signal line DL.
When a short circuit occurs in the portion where D2 is overlapped, a point defect of the pixel having the short-circuited thin film transistor TFT is sufficient.

In this way, the scanning signal lines GL and the video signal lines DL intersect, and the gate electrode GT and the drain electrode SD are formed.
Even when a short circuit or a disconnection occurs in the portions SH1, SH2, SH3 where 1 overlaps, a line defect can be corrected, a display screen without a line defect can be obtained, and the yield of the liquid crystal display device can be improved. It is possible to improve and reduce the manufacturing cost. It is to be noted that there is a low probability that a short circuit or a wire break will occur at both of the two first intersections SH1 and the second intersection SH2 of the scanning signal line GL and the video signal line DL or the bypass GBP.

Since the storage capacitor element Cadd having the pixel electrode ITO1 as one electrode and the bypass GBP of the adjacent pixel as the other electrode is formed, when a short circuit occurs in the storage capacitor element Cadd, both sides of the short circuit portion are formed. By disconnecting the bypass GBP of the above, the short-circuited portion is electrically separated, and the point defect due to the short-circuiting of the holding capacitance element Cadd portion can be corrected. Further, since the storage capacitor element Cadd is provided, it is possible to reduce the direct current component added to the liquid crystal at the time of switching the thin film transistor TFT, which causes the shortening of the life of the liquid crystal and the so-called burn-in that the previous image remains when the liquid crystal display screen is switched.
Further, the storage capacitor element Cadd also has a function of prolonging the discharge time, and stores the image information for a long time after the thin film transistor TFT is turned off.

Since the bypass GBP is also used as the storage capacitor Cadd, the aperture ratio can be improved.

Thin film transistor TFT of all pixels
In other words, in the thin film transistors TFT of all pixels, the source electrode SD is different from the drain electrode SD1 integrated with the video signal line DL in all the pixels.
Since 2 are arranged in the same direction, even if the mask for forming the thin film transistor TFT is misaligned in the horizontal direction or the vertical direction, a change in the overlapping state of the source or drain electrodes SD1 and SD2 of the thin film transistor TFT is caused in all pixels. Since it becomes the same, the thin film transistor T
Variations in FT characteristics can be prevented. For example, when the thin film transistors are arranged such that the direction of the source electrode with respect to the drain electrode integrated with the video signal line of the thin film transistor is staggered for each scanning signal line (that is, it also serves as the drain electrode of the thin film transistor of the pixel of a certain scanning signal line). When the video signal line is on the left side of the pixel and the video signal line that also serves as the drain electrode of the thin film transistor of the pixel of the scanning signal line of the next stage is on the right side), when the thin film transistor forming mask is displaced in the horizontal direction, The change in the overlapping state of the source or drain electrodes of the thin film transistors is reversed for each scanning signal line, and variations in the characteristics of the thin film transistors occur. However, in this embodiment, all thin film transistor TFTs have the same orientation, so this is prevented. it can.

FIG. 4 is a partial plan view of a liquid crystal display section in which a plurality of pixels shown in FIG. 1 are arranged. As shown in FIG. 4, a plurality of pixels of the liquid crystal display unit are arranged in the same horizontal direction as the direction in which the scanning signal lines GL extend, and the pixel columns Y _i ,
Each of Y _{i + 1} , Y _{i + 2} , Y _{i + 3} ,.
Each pixel of each pixel column Y _i , Y _{i + 1} , Y _{i + 2} , Y _{i + 3} , ... Has a thin film transistor TFT and a transparent pixel electrode IT.
The arrangement positions of O1 are the same. That is, in each pixel of the pixel columns Y _i , Y _{i + 2} , ..., The thin film transistor TFT is arranged on the right side and the transparent pixel electrode ITO1 is arranged on the left side. Further, each pixel of the pixel rows Y _{i + 1} , Y _{i + 3} , ... In the next stage is line-symmetric with respect to each pixel of the pixel rows Y _i , Y _{i + 2} ,. It is composed of arranged pixels. That is, in each pixel of the pixel columns Y _{i + 1} , Y _{i + 3} , ..., The thin film transistor TFT is arranged on the left side, and the transparent pixel electrode ITO1 is arranged on the right side (in the thin film transistor TFT of all pixels, the video signal is The source electrode S with respect to the drain electrode SD1 integrated with the line DL
D2 is arranged in the same direction). Then, the pixel row Y
_{i + 1, Y i + 3} , ... Each of the pixels of the pixel row Y _i,
The pixels Y _{i + 2} , ... Are arranged so as to be shifted by a half pixel interval in the horizontal direction. That is, assuming that the pixel spacing of each pixel row is 1.0 (1.0 pitch), the pixel spacing of the next row is 1.0 with each pixel spacing being 0.5 in the horizontal direction with respect to the pixel row of the preceding row. Pixel spacing (0.5 pitch) is offset.
The video signal line DL extending vertically between the pixels is configured to extend in the horizontal direction by a half pixel interval (0.5 pitch) between the pixel columns.

By arranging the pixel rows in the liquid crystal display section in this way, as shown in FIG. 5 (a partial plan view showing only the color filter layer), a predetermined color filter of the preceding pixel row is formed. Pixels (for example, pixels in which the red filter R of the pixel column Y _{i + 2} is formed) and pixels in which the same color filter of the next pixel column is formed (for example, the pixel column Y _{i + 3}
The pixel on which the red color filter R is formed) can be separated by 1.5 pixels (1.5 pitch). That is, the pixel in the preceding pixel row is always separated from the pixel in the nearest neighboring pixel row in the next pixel row in which the same color filter is formed by 1.5 pixel intervals. It forms a triangular arrangement structure. Since this structure can improve the color mixture of each color, the resolution of the color image can be improved. The video signal line DL is
Since each pixel column extends in the horizontal direction only by the half pixel interval, it does not intersect with the adjacent video signal line DL. Therefore, the routing of the video signal line DL is eliminated,
The occupied area can be reduced, the detour of the video signal line DL can be eliminated, and the multilayer wiring structure can be eliminated.

(Overall Structure of Display Section) As shown in FIG. 2, a thin film transistor TFT and a transparent pixel electrode ITO1 are provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
On the upper transparent glass substrate SUB2 side, a color filter FIL and a light-shielding black matrix pattern B are formed.
M is formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. Further, a silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Therefore, the transparent glass substrates SUB1 and SUB
Even if there are sharp scratches on the surface of 2, the sharp scratches can be covered with the silicon oxide film SIO, so that the film quality of the scanning signal line GL, the light shielding film BM, and the like deposited thereon can be kept uniform. .

Although not shown, a sealant is formed so as to seal the liquid crystal LC along the entire periphery of the transparent glass substrates SUB1 and SUB2 excluding the liquid crystal inlet. The sealing material is made of epoxy resin, for example. Upper transparent glass substrate S
The common transparent pixel electrode ITO2 on the UB2 side is connected to an external lead wire formed on the lower transparent glass substrate SUB1 side by a silver paste material at at least one place. The external lead wiring is formed in the same manufacturing process as the gate terminal GTM and the drain terminal DTM described later.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and the respective layers are formed inside the sealing material. Polarizing plates POL1, P
The OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI that sets the orientation of liquid crystal molecules.
1 and the upper alignment film ORI2, and is sealed by a sealing material. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and then the lower transparent glass substrate SUB1.
And the upper transparent glass substrate SUB2 are overlapped with each other, and the liquid crystal LC is sealed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

(Thin Film Transistor TFT) The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel includes a gate electrode GT, a gate insulating film GI, an i type (intrinsic, intrinsic
c, an i-type semiconductor layer AS made of amorphous silicon (Si which is not doped with conductivity determining impurities), a pair of source electrodes, and drain electrodes SD1 and SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

The directions of the thin film transistors TFT of all the pixels are the same as shown in FIG. That is, in the thin film transistor TFT of all pixels,
The source electrode SD2 is arranged in the same direction as the drain electrode SD1 integrated with the video signal line DL. Therefore, even if the mask for forming the thin film transistor TFT is misaligned in the horizontal direction or the vertical direction, the source or drain electrode SD of the thin film transistor TFT may be misaligned.
Since the change in the degree of overlap between 1 and SD2 is the same for all pixels, it is possible to prevent variations in the characteristics of the thin film transistors TFT.

In this embodiment, one thin film transistor TFT is provided for each pixel as shown in FIG. 1, but each pixel has substantially the same size (channel length and channel width are the same). Two thin film transistors (referred to as TFT1 and TFT2) may be arranged side by side (three or more may be arranged). In this case, the transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT1 and the source electrode SD1 of the thin film transistor TFT2. As a result, even if one of the thin film transistors TFT1 and TFT2 is defective,
If the defect causes a side effect such as occurrence of a line defect on the display screen, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor is operating normally and may be left. It is rare that defects occur simultaneously in the two thin film transistors TFT1 and TFT2, and the probability of point defects or line defects can be extremely reduced by such a redundancy system.

(Gate Electrode GT) The gate electrode GT projects so as to extend beyond the active region of the thin film transistor TFT. The gate electrode GT of the thin film transistor TFT is integrally configured (as a common gate electrode) and is formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2.
The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering, and is formed to have a film thickness of about 1000 to 5500 Å. An Al anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIG. 2, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque Al becomes a shadow, and the i-type semiconductor layer AS is not exposed to the backlight light. The conduction phenomenon due to light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the minimum required to extend between the source electrode SD1 and the drain electrode SD2 (including the alignment margin between the gate electrode GT, the source electrode SD1 and the drain electrode SD2). ) Has a width and its depth length that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm. It depends on what you do. The size of the gate electrode GT in this liquid crystal display device is, of course, larger than the original size described above.

(Scan signal line GL and bypass GBP)
The scanning signal line GL and its bypass GBP are composed of the second conductive film g2. The scanning signal line GL and the second conductive film g2 of the bypass GBP are formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT and are integrally formed. In addition, the scanning signal line GL and the bypass GBP
An Al anodic oxide film AOF is also provided on the top.

(Insulating Film GI) The insulating film GI is used as a gate insulating film of the thin film transistor TFT. Insulation film G
I is formed in the upper layer of the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is used, and 1200 to 2700Å
Film thickness (in this liquid crystal display device, a film thickness of about 2000 Å).

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region of the thin film transistor TFT. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a film thickness of 200 to 2200Å (in this liquid crystal display device, a film thickness of about 2000Å).

The i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and the same plasma CVD apparatus as the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the composition of the supply gas. It is formed without being exposed to the outside from the CVD device. Further, phosphorus (P) for ohmic contact is doped with 2.5% of N (+) type semiconductor layer d.
0 (FIG. 2) is also continuously formed with a film thickness of 200 to 500 Å (in this liquid crystal display device, a film thickness of about 300 Å). After that, the lower transparent glass substrate SUB1 is CV
It is taken out from the D device and is N (+) by the photo processing technology.
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent islands as shown in FIG.

The i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Transparent pixel electrode ITO1) Transparent pixel electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is composed of a first conductive film d1, and the first conductive film d1 is a transparent conductive film (Indium-Tin-Oxide I) formed by sputtering.
(TO: Nesa film), and is formed with a film thickness of 1000 to 2000Å (in this liquid crystal display device, a film thickness of about 1400Å).

(Source electrode SD1, drain electrode SD
2) The source electrode SD1 and the drain electrode SD2 of the thin film transistor TFT are provided separately on the i-type semiconductor layer AS, as shown in FIG.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially superposing the second conductive film d2 and the third conductive film d3 from the lower layer side in contact with the N (+) type semiconductor layer d0. The second conductive film d2 of the source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is a chromium (Cr) film formed by sputtering and is formed to have a film thickness of 500 to 1000 Å (in this liquid crystal display device, a film thickness of about 600 Å).
Since the stress increases when the Cr film is formed thicker, the Cr film is formed within the range of about 2000 Å.
The Cr film has good contact with the N (+) type semiconductor layer d0.
The Cr film constitutes a so-called barrier layer that prevents Al of the third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used instead of the Cr film.

The third conductive film d3 is formed by sputtering Al and has a thickness of 3000 to 5000 Å (in this liquid crystal display device,
The film thickness is about 4000Å). The Al film has less stress than the Cr film, can be formed to have a thick film thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing silicon or copper (Cu) as an additive may be used in addition to the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 has the i-type semiconductor layer AS step difference (thickness of the second conductive film g2, thickness of the anodic oxide film AOF, thickness of the i-type semiconductor layer AS, and thickness of the N (+) type semiconductor layer d0. It is configured along a step corresponding to the added film thickness). Specifically, the source electrode SD1 is the second conductive film d2 formed along the step of the i-type semiconductor layer AS.
And the third conductive film d formed on the second conductive film d2.
3 and 3. The third conductive film d3 of the source electrode SD1 cannot be formed thick due to the increased stress of the Cr film of the second conductive film d2 and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 thick. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 2) does not enter the i-type semiconductor layer AS used as a channel formation region, and the light-shielding film BM is a substantially transparent pixel electrode. The pattern is such that ITO1 is excluded.

Therefore, i of the thin film transistor TFT
The type semiconductor layer AS is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel, that is, the light shielding film BM.
Are formed in a lattice shape (black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the contour of each pixel is made clear by the light-shielding film BM,
The contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Further, since the portion (not shown) facing the edge portion of the transparent pixel electrode ITO1 on the root side in the rubbing direction is shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain is Since it is not visible, the display characteristics do not deteriorate.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

(Color Filter FIL) The color filter FIL is constructed by coloring a dye base material made of a resin material such as acrylic resin with a dye. Color filter F
ILs are arranged and formed in a triangular shape as described above at positions and shapes facing the pixels (FIG. 5) and are dyed separately (FIG. 5 shows only the color filter FIL corresponding to FIG. , R, G color filters FIL
Are parallel vertical lines, with 45 ° and 135 ° hatches, respectively). The color filter FIL is a transparent pixel electrode I
The light-shielding film B is formed to be large so as to cover the entire TO1.
M is a color filter FIL and a transparent pixel electrode ITO1
Is formed inside the peripheral portion of the transparent pixel electrode ITO1 so as to overlap the edge portion thereof.

The color filter FIL can be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

(Protective Film PSV2) In the protective film PSV2, the liquid crystal L is a dye in which the color filter FIL is dyed in different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the liquid crystal LC is in an optical state of each pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. The common voltage Vcom is an intermediate potential between the low level drive voltage Vdmin and the high level drive voltage Vdmax applied to the video signal line DL.

(Gate Terminal) FIG. 6 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM. (A) is a plane and (B) is B of (A). -B shows a cross section taken along the line B. It should be noted that this figure shows the substrate SUB based on the matrix of FIG.
1 shows the vicinity of the left end of 1.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the conductive portion therebelow is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. As described above, the mask pattern AO does not intersect the scanning line GL with a single straight line, but is bent in a crank shape and intersects with it.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM is composed of a silicon oxide SIO layer and a Cr layer g1 having a good adhesive property, and a transparent conductive layer d1 having the same level (same layer, simultaneously formed) as the pixel electrode ITO1 for protecting the surface thereof. There is. In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end is formed.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically, and the left end of the gate terminal in the figure is
During the manufacturing process, it is extended and shorted beyond the cut area of the substrate. Such a short circuit in the manufacturing process is useful for supplying power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

(Drain Terminal DTM) FIG. 7 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM, (A) shows the plane, and (B) shows B- of (A).
A cross section taken along line B is shown. This figure shows the upper end portion and the lower end portion of the substrate SUB1 based on the matrix of FIG. 4, and although the direction is changed for convenience, the left end direction is the substrate S.
It corresponds to the upper end or the lower end of UB1.

TSTd is an inspection terminal and no external circuit is connected to it. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure. Further extended beyond the cutting line of the substrate SUB1,
During the manufacturing process, all of them are short-circuited to each other to prevent electrostatic breakdown. In the figure, the video signal line D in which the inspection terminal TSTd exists
The drain connection terminal DTM is connected to the opposite side across the matrix of L, and conversely the inspection terminal is connected to the opposite side across the matrix of the video signal line DL where the drain connection terminal DTM exists. For the same reason as the above-mentioned gate terminal GTM, it is formed of two layers of the Cr layer g1 and the ITO layer d1, and is connected to the video signal line DL at the portion where the gate insulating film GI is removed. Gate insulating film G
The semiconductor layer AS formed on the end portion of I is the gate insulating film G
It is for etching the edge of I in a tapered shape.
A protective film P is formed on the terminal DTM to connect to an external circuit.
SV1 has, of course, been removed. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is covered in the part not covered in this figure. This pattern is not directly relevant as it does not exist.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the bypass GBP of the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. . As is clear from FIG. 3, this overlapping is performed by the transparent pixel electrode I.
TO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used.
A storage capacitor element (electrostatic capacitor element) Cadd having the bypass GBP of the other electrode PL1 is configured. The dielectric film of the storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodized film AOF.

As is apparent from FIG. 1, the storage capacitor element Cadd is formed in the portion of the second conductive film g2 of the bypass GBP of the scanning signal line GL. The video signal line DL
The second conductive film g2 at a portion intersecting with is thinned in order to reduce the probability of short circuit with the video signal line DL. Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the defect is caused by the island region formed by the second conductive film d2 and the third conductive film d3 formed so as to cross the step. Is compensated. This island region is formed as small as possible so as not to reduce the aperture ratio.

Further, since the storage capacitor Cadd having the pixel electrode ITO1 as one electrode and the bypass GBP of the adjacent pixel as the other electrode is formed, when a short circuit occurs in the storage capacitor Cadd portion, the short circuit portion is generated. Both sides of the bypass GBP
By disconnecting, the short circuit part is electrically separated,
A point defect due to a short circuit of the storage capacitor element Cadd can be corrected. Further, since the bypass GBP is also used as the storage capacitor Cadd, the aperture ratio can be improved.

(Whole Equivalent Circuit of Display Device) FIG. 8 shows a wiring diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X (subscript omitted) means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device that displays information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. It is a circuit including a circuit for exchanging information for use.

(Equivalent Circuit of Retaining Capacitance Element Cadd and Its Operation) FIG. 9 shows an equivalent circuit of the pixel shown in FIG. Figure 9
In, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO1
It is a liquid crystal capacitance formed between (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is the liquid crystal LC, the protective film PSV1 and the alignment film ORI.
1 and ORI2. Vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This can be expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents the change in the midpoint potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. In addition, the storage capacitor element C
The add also has the effect of lengthening the discharge time, and accumulates image information for a long time after the thin film transistor TFT is turned off. The reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, so that the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Cadd
By providing the above, this demerit can be eliminated.

The holding capacitance of the holding capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

(Method of connecting the storage capacitor element Cadd electrode wire)
The scanning signal line GL (Y ₀ ) at the first stage used only as the storage capacitor electrode line is connected to the common transparent pixel electrode ITO2 (Vcom) as shown in FIG. Since the common transparent pixel electrode ITO2 of the substrate SUB2 is connected to the external lead wiring of the substrate SUB1 by the silver paste material in the peripheral portion of the liquid crystal display device as described above, the scanning signal line GL (Y ₀ ) of the first stage is It suffices to connect it to the external lead wiring on the substrate SUB1 side. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is connected to the scanning signal line Yend in the final stage and is connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. You may connect to receive.

(Manufacturing Method) Next, a manufacturing method for the substrate SUB1 side of the above-described liquid crystal display device will be described with reference to FIGS.
Will be described with reference to. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 2, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage after the photo process is finished and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 10 A silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by a dip treatment, and then baked at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line (not shown) connecting the gate terminal GTM, the bus line (not shown) short-circuiting the drain terminal DTM, and the anode connected to the anodized bus line. Form an oxide pad (not shown).

Step B, FIG. 10 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 10 After photographic processing (after forming the above-mentioned anodic oxidation mask AO), 3
Substrate SUB1 is immersed in an anodizing solution consisting of a solution prepared by diluting 1% of tartaric acid with ammonia to pH 6.25 ± 0.05 with ethylene glycol solution, and the formation current density is 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized,
An anodic oxide film AOF having a film thickness of 1800Å is formed on the scanning signal line GL, the gate electrode GT, and the electrode PL1 Step D, FIG. 11 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to make the film thickness A 2000 Å Si nitride film is provided, and silane gas and hydrogen gas are introduced into the plasma CVD device to form an i-type amorphous Si film with a film thickness of 2000 Å, then hydrogen gas and phosphine gas are introduced into the plasma CVD device. Then, an N (+) type amorphous Si film having a film thickness of 300Å is provided.

Step E, FIG. 11 After photoprocessing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 11 After the photographic process, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 12 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 12 A second conductive film d2 made of Cr and having a film thickness of 600 Å is provided by sputtering.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 12 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a film thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

(Modification) In the above-mentioned embodiment, the photoresist pattern on the Al gate wiring is formed in a crank shape, but the shape is not limited to this shape. In short, when peeling occurs in the hot pattern and progresses, it may be formed of a rectangle, a triangle, a circle, a trapezoid, or the like alone or in combination as long as it stops the peeling.

(Scope of Application) The invention made by the present inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-mentioned embodiments, and does not depart from the scope of the invention. Needless to say, various changes can be made in.

For example, the scanning signal line GL and its bypass G
It goes without saying that the pattern shape, position, number, etc. of the BP, the video signal line DL, the thin film transistor TFT, etc. are not limited to those shown in FIG. Further, in the embodiment of FIG. 1, only one bypass GBP of the scanning signal line GL is provided for each pixel, but two or more bypass GBPs may be provided. Further, although the pixels and the color filters FIL are arranged in a triangular (triangle) arrangement structure as shown in FIGS. 4, 5, and 1 in the above-described embodiment, a stripe arrangement structure may be used.

Furthermore, for example, the liquid crystal display device in which the greatest mass production effect can be expected in the above-mentioned embodiment has been described.
The present invention is not limited to this, and can be applied to a thin film device such as a contact photosensor using a thin film transistor and an electroluminescent display device.

[0105]

As described above, in the liquid crystal display device of the present invention, since the scanning signal line also serves as the gate electrode of the thin film transistor, the aperture ratio can be improved. A bypass is provided for each pixel in the scanning signal line, and a closed loop connected to an external circuit is formed for each pixel by the scanning signal line and the bypass.Therefore, when a short circuit occurs in the closed loop, a closed loop using a laser or the like is used. No matter where you disconnect, you can connect to an external circuit and fix line defects. Since the video signal line intersects with the closed loop at a plurality of points, even if a short circuit occurs at any of the intersections of the scanning signal line and the video signal line or the overlapped portions, the closed loops on both sides of the short circuit portion The line defect can be completely repaired by cutting. Since the storage capacitor element having the pixel electrode as one electrode and the bypass of the adjacent pixel as the other electrode is formed, by disconnecting the bypass on both sides of the short circuit portion when a short circuit occurs in the storage capacitor element portion. The short-circuit portion is electrically separated, and the point defect due to the short-circuit of the storage capacitor element portion can be corrected. Since the bypass serves also as the storage capacitor, the aperture ratio can be improved.
Furthermore, in the thin film transistor of all pixels,
Since the source electrode is arranged in the same direction as the drain electrode integrated with the video signal line, even if the mask for forming the thin film transistor is misaligned in the horizontal or vertical direction, the source or drain electrode of the thin film transistor overlaps. Since the change in the condition is the same for all pixels, it is possible to prevent variations in the characteristics of the thin film transistors. As a result, it is possible to obtain a bright and good-quality display screen without line defects, improve the yield of the liquid crystal display device, and reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a main part plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one pixel and its periphery under the section line 3-3 in FIG.

FIG. 3 is a cross-sectional view of the additional capacitance Cadd taken along section line 4-4 of FIG.

4 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

5 is a plan view of an essential part showing only a color filter layer of the pixel array shown in FIG.

FIG. 6 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate line GL to which the present invention is applied.

FIG. 7 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 8 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 9 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 10 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 11 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps D to F on the substrate SUB1 side.

FIG. 12 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps GI on the side of the substrate SUB1.

[Explanation of symbols]

GL ... Scan signal line, GBP ... Bypass, DL ... Video signal line, TFT ... Thin film transistor, GT ... Gate electrode, S
D1 ... Drain electrode integrated with video signal line, SD2
Source electrode, ITO1, transparent pixel electrode, Cadd, storage capacitor element, SH1-3, short-circuit occurrence portion, RTL1-5, laser trimming portion.

Claims (2)

[Claims] 1. A scanning signal line extending horizontally and a plurality of scanning signal lines vertically arranged, and a video signal line extending vertically and a plurality of video signal lines horizontally arranged adjacent to each other. A thin film transistor and a pixel electrode, each of which is arranged in an intersecting region between the two scanning signal lines and the two adjacent video signal lines, and the thin film transistor and the pixel electrode are constituent elements of one pixel. In an active matrix type liquid crystal display device, a bypass is provided for each pixel in the scanning signal line that also serves as the gate electrode of the thin film transistor, and a closed loop connected to an external circuit by the scanning signal line and the bypass is provided for each pixel. The video signal line intersects with the closed loop at a plurality of points, and the pixel electrode serves as one electrode, and the bypass of the adjacent pixel serves as the other electrode. The liquid crystal display device which forms a storage capacitor element, characterized in that also serves the above bypass and the retention capacitor that. 2. The liquid crystal display device according to claim 1, wherein in each of the thin film transistors of all the pixels, a source electrode is arranged in the same direction as a drain electrode integrated with the video signal line.