JP3125411B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to an active matrix liquid crystal display using thin film transistors.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using thin film transistors is disclosed in, for example,
No. 9921.

An active matrix type liquid crystal display device has a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. The liquid crystal is sealed and sealed in the gap between the upper and lower substrates to form an integrated cell. In the module assembling process, the cell side terminal and the tape carrier package TCP side terminal are connected using the anisotropic conductive film ACF. Conventionally, an Al pattern is used for ultrasonic cleaning after assembling into an integrated cell and terminal cleaning work before TCP crimping in a module assembling process.
There was a problem that the protective film (PSV1) on the substrate was peeled off. It has been found that the peeling of the protective film causes electrical corrosion between terminals after the high-temperature and high-humidity test. If there is a portion where the conductor pattern is exposed between the protective film and TAB, the epoxy resin E
It has been found that even if PX or silicone resin SIL is applied, it is not sufficient in reliability and causes electrolytic corrosion between terminals. For this reason, it has become necessary to define the position of the Al pattern and the position of the protective film in the terminal lead portion.

On the signal line side, a video signal or a digital signal is constantly input and the duty is high.
A better reliability design is needed. Even in the high-temperature and high-humidity test results, in many cases, electric corrosion occurred on the signal line side and there was no abnormality on the scanning line side in many cases. Therefore, the present invention is particularly effective on the signal line side.

[0005]

SUMMARY OF THE INVENTION One object of the present invention is to provide a highly reliable liquid crystal display device.

Another object of the present invention is to provide a liquid crystal display device which is capable of preventing a failure of interelectrode corrosion after a high-temperature and high-humidity test, which becomes more remarkable since a terminal pitch becomes smaller with higher definition. It is to be.

[0007]

According to one embodiment of the present invention, in a liquid crystal display device in which a terminal is connected to a video signal line via oblique wiring, the position of an Al pattern in a terminal lead-out portion is a secret. A liquid crystal display device is provided in which the protective film PSV1 extends under the TCP and covers the terminal lead portion.

[0008]

According to such a liquid crystal display device, even if a mechanical stress is applied in a liquid crystal assembling process or a module process, peeling is prevented because the Al material having a weak adhesion and the protective film are present in the seal. In addition, since all the lead-out wirings are covered with the protective film, there is no exposed conductor pattern, it is difficult to directly contact the outside air, and the high-temperature high-humidity test reliability is good.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings, in which: FIG.

(Active matrix liquid crystal display device)
Hereinafter, an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device to which the present invention is applied and the periphery thereof. FIG.
FIG. 3 is a cross-sectional view taken along the section line 2 in FIG.
It is sectional drawing in a cutting line. FIG. 4 is a plan view when a plurality of pixels shown in FIG. 1 are arranged.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And two adjacent video signal lines (drain signal lines or vertical signal lines) DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction.

As shown in FIG. 2, a thin film transistor TFT is provided on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC.
In addition, a transparent pixel electrode ITO1 is formed, and a color filter FIL and a light shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. Also, the transparent glass substrates SUB1, S
A silicon oxide film SIO formed by dipping or the like is provided on both surfaces of UB2. For this reason, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the sharp scratches can be covered with the silicon oxide film SIO, so that the scanning signal lines G deposited on them can be covered.
L, the film quality of the light shielding film BM and the like can be kept uniform.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and an upper alignment film ORI2 are sequentially laminated.

FIG. 16 shows a display panel PNL including upper and lower glass substrates SUB1 and SUB2.
17 is a plan view of a main part around the matrix (AR), FIG. 17 is a plane in which the periphery is further exaggerated, and FIG. 18 is a plan view of FIGS.
FIG. 7 is an enlarged plan view of the vicinity of a seal portion SL corresponding to the upper left corner of the panel 7. FIG. 19 is a diagram showing a cross section taken along the line 19a-19a in FIG. 18 on the left side and a cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected on the right side, with the cross section of FIG. is there. FIG. 2
0 is an external connection terminal G to which a scanning circuit is to be connected on the left side.
It is a figure showing a section near TM, and a section near a seal part where there is no external connection terminal on the right side.

[0016] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. FIGS. 16 to 18 show examples of the latter, and FIGS. 16 and 17 both show the upper and lower substrates SUB.
FIG. 18 shows a state before cutting the substrates SUB1 and SUB2, and FIG. 18 shows a state before cutting the substrates. LN indicates an edge of both substrates before cutting, and CT1 and CT2 indicate positions where the substrates SUB1 and SUB2 are to be cut, respectively. In any case, in the completed state, the external connection terminal group T
g, Td (subscripts omitted) (upper and lower sides and left side in the figure)
In the portions, the size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so as to expose them. The terminal groups Tg and Td are respectively provided with a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which are described later, and their leading wiring portions of a tape carrier package TCP (FIGS. 20 and 21) on which an integrated circuit chip CHI is mounted. The unit is named plurally. The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the terminals DTM and GTM of the display panel PNL are matched with the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal filling opening INJ, the liquid crystal LC
Is formed to seal the sealing pattern SL. The sealing material is made of, for example, an epoxy resin. In at least one place, the common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead wiring INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at the four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as the later-described gate terminal GTM and drain terminal DTM.

The layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are each a lower transparent glass substrate SUB
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed above the SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

(Thin Film Transistor TFT) The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases.

The thin film transistor TFT of each pixel is divided into two (a plurality) in the pixel, and includes thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is a gate electrode GT, a gate insulating film GI, and an i-type semiconductor made of i-type (intrinsic, intrinsic, not doped with a conductivity type determining impurity) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1, and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are switched during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

(Gate electrode GT) The gate electrode GT is shown in FIG.
As shown in FIG. 1 (a plan view depicting only the second conductive film g2 and the i-type semiconductor layer AS in FIG. 1), the projection is configured to protrude in the vertical direction (upward in FIGS. 1 and 5) from the scanning signal line GL. (Branched into a T-shape). The gate electrode GT protrudes beyond the respective active areas of the thin film transistors TFT1 and TFT2. The respective gate electrodes G of the thin film transistors TFT1 and TFT2
T is integrally formed (as a common gate electrode) and is formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of a single-layer second conductive film g2. As the second conductive film g2, for example, an aluminum (Al) film formed by sputtering is used,
It is formed with a thickness of about 0 °. An anodic oxide film AOF of Al is provided on the gate electrode GT.

As shown in FIGS. 1, 2 and 5, this gate electrode GT is formed larger than the i-type semiconductor layer AS so as to completely cover it (as viewed from below).
Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque Al becomes a shadow, and the i-type semiconductor layer AS is not irradiated with the backlight. In addition, the conductive phenomenon due to light irradiation, that is, the deterioration of the off characteristic of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary to extend between the source electrode SD1 and the drain electrode SD2 (including the margin for positioning between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). ) Has a width, and the depth length that determines the channel width W is determined by the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the transconductance gm. It depends on what you do. The gate electrode G in this liquid crystal display device
The size of T is, of course, made larger than the original size described above.

(Scanning Signal Line GL) The scanning signal line GL is
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. An anodic oxide film AOF of Al is also provided on the scanning signal line GL.

(Insulating Film GI) The insulating film GI is used as a gate insulating film of each of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using a silicon nitride film formed by, for example, plasma CVD and having a thickness of 1200 to 2700 ° (about 2000 ° in this liquid crystal display device). As shown in FIG. 18, the gate insulating film GI is formed so as to surround the whole of the matrix part AR, and the peripheral part is provided with the external connection terminals DTM, G.
Removed to expose TM.

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel formation region of each of the thin-film transistors TFT1 and TFT2 divided as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film.
Å (in this liquid crystal display device, about 2000 膜厚).

The i-type semiconductor layer AS is formed in the same plasma CVD apparatus by changing the components of the supply gas and continuously forming an insulating film GI used as a gate insulating film made of Si ₃ N ₄ using the same plasma CVD apparatus. It is formed without being exposed to the outside from the CVD apparatus. Also, an N (+) type semiconductor layer d doped with 2.5% of phosphorus (P) for ohmic contact.
0 (FIG. 2) is similarly formed continuously with a film thickness of 200 to 500 ° (about 300 ° in this liquid crystal display device). Then, the lower transparent glass substrate SUB1 is CV
It is taken out of the D device and N (+)
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent island shapes as shown in FIGS.

As shown in FIGS. 1 and 5, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Transparent Pixel Electrode ITO1) Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T1.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut off by a laser beam or the like, and if not, the other thin film transistor operates normally. You can leave it. It is rare that defects occur simultaneously in the two thin film transistors TFT1 and TFT2, and the probability of a point defect or a line defect can be extremely reduced by such a redundant system. Transparent pixel electrode ITO
Reference numeral 1 denotes a first conductive film d1.
The conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering.
A film thickness of 00 to 2000 ° (14 in this liquid crystal display device)
(Thickness of about 00 °).

(Source electrode SD1, drain electrode SD
2) Thin-film transistors TFT1, TF divided into a plurality
Source electrode SD1 and drain electrode SD of T2
2 is provided separately on the i-type semiconductor layer AS as shown in FIGS. 1, 2 and 6 (a plan view depicting only the first to third conductive films d1 to d3 in FIG. 1). Have been.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower side in contact with the N (+) type semiconductor layer d0. Second conductive film d2 of source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is formed by using a chromium (Cr) film formed by sputtering and having a thickness of 500 to 1000 ° (about 600 ° in this liquid crystal display device).
Since the stress increases when the Cr film is formed to have a large thickness, the Cr film is formed within a range not exceeding about 2000 °.
The Cr film has good contact with the N (+) type semiconductor layer d0.
The Cr film forms a so-called barrier layer that prevents Al of a third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr film.

The third conductive film d3 has a thickness of 3000 to 5000 ° by sputtering of Al (in this liquid crystal display device,
(A film thickness of about 4000 °). The Al film has a smaller stress than the Cr film and can be formed with a large thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing silicon or copper (Cu) as an additive may be used in addition to the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask or using the second conductive film d2 and the third conductive film d3 as a mask, an N (+) type The semiconductor layer d0 is removed. That is,
N (+)-type semiconductor layer d0 remaining on i-type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so as to remove all of its thickness, the surface of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 has an i-type semiconductor layer AS step (the thickness of the second conductive film g2, the thickness of the anodic oxide film AOF, the thickness of the i-type semiconductor layer AS, and the thickness of the N (+)-type semiconductor layer d0. (A step corresponding to the added film thickness). Specifically, the source electrode SD1 is formed of a second conductive film d2 formed along a step of the i-type semiconductor layer AS.
And a third conductive film d formed on the second conductive film d2.
3 is comprised. Since the third conductive film d3 of the source electrode SD1 cannot form a thick Cr film of the second conductive film d2 due to an increase in stress and cannot cross the step shape of the i-type semiconductor layer AS, the third conductive film d3 crosses over the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 to be thick. Since the third conductive film d3 can be formed to be thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

(Protective Film PSV1) Thin Film Transistor TF
A protective film PSV1 is provided on T and the transparent pixel electrode ITO1. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like.
Use a material with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 18, the protective film PSV1 is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM.
Further, the common electrode COM of the upper substrate SUB2 is connected to the lower substrate SU.
The portion connected to the external connection terminal connection lead-out wiring INT of B1 with the silver paste AGP is also removed. Protective film PSV
Regarding the thickness relationship between 1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in the transconductance gm of the transistor. Therefore, as shown in FIG. 18, the protection film PSV1 having a high protection effect is formed larger than the gate insulating film GI so as to protect the peripheral portion as much as possible.

(Light shielding film BM) Upper transparent glass substrate SUB
On the second side, a light-shielding film BM is provided so that external light (light from above in FIG. 2) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern shown in FIG. FIG. 7 shows the first conductive film d made of the ITO film in FIG.
FIG. 1 is a plan view illustrating only a color filter FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property. In this liquid crystal display device, the chromium film is formed to a thickness of about 1300 ° by sputtering.

Therefore, the thin film transistors TFT1, TF
The i-type semiconductor layer AS of T2 is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT,
That portion is not exposed to external natural light or backlight light. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 7, that is, the light-shielding film BM is formed in a lattice shape (black matrix), and an effective display area of one pixel is partitioned by the lattice. . Therefore, the outline of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light-shielding film BM has two functions of light-shielding for the i-type semiconductor layer AS and black matrix.

Further, a portion (lower right portion in FIG. 1) of the transparent pixel electrode ITO1 facing the edge portion on the root side in the rubbing direction.
Are shielded from light by the light-shielding film BM, so that even if a domain is generated in the above-mentioned portion, the domain is not visible, so that the display characteristics do not deteriorate.

The backlight may be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 may be set to the observation side (exposed side).

The light-shielding film BM is also formed in a peripheral portion in a frame-shaped pattern as shown in FIG. 17, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. Have been. The light-shielding film BM in the peripheral portion is extended outside the seal portion SL as shown in FIGS. 17 to 20 to prevent leaked light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, the light shielding film BM is about 0.3 to 1..
The substrate SUB2 is formed so as to be kept inside by about 0 mm so as to avoid the cutting region of the substrate SUB2.

(Color Filter FIL) The color filter FIL is formed by coloring a dye on a dye base made of a resin material such as an acrylic resin. Color filter F
IL is formed in a stripe shape at a position facing the pixel (FIG. 8) and is dyed separately (FIG. 8 illustrates only the first conductive film d1, the light shielding film BM, and the color filter FIL in FIG. 4). B, R, G color filters FI
L is 45 °, 135 ° and cross hatched, respectively). The color filter FIL is formed to be large so as to cover all of the transparent pixel electrode ITO1 as shown in FIGS. 7 and 9, and the light shielding film BM of the transparent pixel electrode ITO1 is overlapped with the edge portion of the color filter FIL and the transparent pixel electrode ITO1. It is formed inside the periphery.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process.

(Protective Film PSV2) The protective film PSV2 is formed of a liquid crystal L which is a dye obtained by dyeing a color filter FIL into different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each pixel electrode ITO1. In response to a potential difference (electric field) between the pixel electrode and the common transparent pixel electrode ITO2. The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. In this embodiment, the common voltage Vcom is a low-level drive voltage Vdmin and a high-level drive voltage Vd applied to the video signal line DL.
Although it is set to an intermediate potential with dmax, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half, an AC voltage may be applied. The plan shape of the common transparent pixel electrode ITO2 should be referred to FIGS.

(Gate Terminal Section) FIGS. 9A and 9B are diagrams showing a connection structure from the scanning signal line GL of the display matrix to the external connection terminal GTM, where FIG. 9A is a plane view and FIG. 9B is a view B of FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the lower part of FIG. 18, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a mask pattern for photo processing, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but its locus remains because the oxide film AOF is selectively formed on the gate wiring GL as shown in the sectional view. In the plan view, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with reference to the boundary line AO of the photoresist. Anodized A
L layer g2 conductive portion of the lower formed its oxide the Al ₂ O ₃ film AOF on the surface volume decreases. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains. The mask pattern AO does not intersect the scanning line GL with a single straight line, but intersects by bending in a crank shape.

In the figure, the AL layer g2 is hatched for easy understanding, but the region that is not anodized is patterned in a comb shape. This is because, when the width of the Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and a plurality of these are bundled in parallel to prevent the generation of whiskers and disconnect the wires. The aim is to minimize the probability and conductivity sacrifice. Therefore, in this example, the portion corresponding to the root of the comb is also shifted along the mask AO.

The gate terminal GTM has a Cr layer g1 which has good adhesion to the silicon oxide SIO layer and has higher contact resistance than Al or the like;
Further, it is composed of a transparent conductive layer d1 having the same level (same layer, simultaneous formation) as the pixel electrode ITO1 for protecting the surface thereof.
Note that the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are formed in such regions that the conductive layers g2 and g1 are not etched together due to a pinhole or the like when the conductive layers d3 and d2 are etched. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 extending rightward beyond the gate insulating film GI is a thorough countermeasure.

As shown in FIG . 17 and FIG.
The child groups Tg and Td are provided around the matrix part AR.
However, in order to make the explanation easy to understand, in FIG.
The case where the matrix part AR is located on the side is shown. The gate insulating film GI has a protective film PS on the right side of the boundary line.
V1 is also formed in the right side from the boundary line, the external contact
The connection terminal GTM is located on the left side of the boundary line of the protective film PSV1.
It has an electrical connection portion exposed from the protective film PSV1 and capable of making electrical contact with an external circuit . Details will be described later.
However, the external circuit is a tape carrier package TCP.
Will be installed. The external connection terminal GTM is connected to the terminal where the conductive layer is exposed.
It consists of an air connection part and a part covered with the protective film PSV1.
However, the external connection terminal GTM is electrically connected to the exposed conductive layer.
The connection part and the part covered with the protective film PSV1
Carrier package TCP. In the figure, only one pair of the gate line GL and the gate terminal is shown,
Actually, a plurality of such pairs are vertically arranged as shown in FIG. 18 to constitute a terminal group Tg (FIGS. 17 and 18).
1 and is short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process is useful for power supply during anodization and prevention of electrostatic breakdown during rubbing of the alignment film ORI1 and the like.

(Drain Terminal DTM) FIGS. 10A and 10B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM. FIG. 10A shows the plane, and FIG.
4 shows a cross section taken along section line -B. 18 corresponds to the vicinity of the upper right of FIG. 18 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end (or lower end) of the substrate SUB1.

TSTd is an inspection terminal which is not connected to an external circuit, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a staggered manner in the vertical direction. The inspection terminals TSTd are terminated without reaching the end of the substrate SUB1 as shown in the figure.
Constitutes a terminal group Td (subscript omitted) as shown in FIG. 18 and is further extended beyond the cutting line CT1 of the substrate SUB1.
During the manufacturing process, all of them are short-circuited to each other by the wiring SHd to prevent electrostatic breakdown. A drain connection terminal is connected to the opposite side of the matrix of the video signal line DL where the inspection terminal TSTd exists, and the drain connection terminal DTM is conversely connected.
An inspection terminal is connected to the opposite side of the matrix of the video signal line DL in which is present.

The drain connection terminal DTM is made of the Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above.
And is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. Electrical contact to the conductive layer protective film PSV1 is removed for electrically connecting with an external circuit is exposed to the terminals DTM
A connection is provided. External connection terminal (gate end
D) Like the GTM, the drain connection terminal DTM is
The electric layer is covered with the exposed electric connection portion and the protective film PSV1.
With the tape carrier package TCP
It is. AO is the anodic oxidation mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side from the boundary line is covered with the mask. This pattern has no direct relevance.

The lead-out wiring from the matrix portion to the drain terminal portion DTM is as shown in FIG.
The structure is such that the layers d2 and d3 of the same level as the video signal line DL are stacked up to the middle of the seal pattern SL immediately above the layers d1 and g1 of the same level as the drain terminal portion DTM. Is minimized, and the Al layer d3 that is easily touched is protected as much as possible by the protective film PSV1 and the seal pattern SL.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap an adjacent scanning signal line GL at an end opposite to the end connected to the thin film transistor TFT. This superposition is shown in FIG.
As is clear from FIG. 3, a storage capacitance element (capacitance element) Cadd having the transparent pixel electrode ITO1 as one electrode PL2 and the adjacent scanning signal line GL as the other electrode PL1 is formed. The dielectric film of the storage capacitor Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As is apparent from FIG. 5, the storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive film g2 is increased. Note that the portion of the second conductive film g2 that intersects with the video signal line DL is thinned in order to reduce the probability of a short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 breaks at the step of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 are formed so as to extend over the step.
The defect is compensated for by the island region constituted by the conductive film d3.

(Equivalent Circuit of the Entire Display Device) FIG. 11 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y indicates the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP uses a TFT liquid crystal display device to transmit information for a CRT (cathode ray tube) from a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source or a host (upper processing unit). This is a circuit that includes a circuit that exchanges information for use.

(Equivalent Circuit of Storage Capacitor Cadd and Its Operation) FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film of the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO
1 (PIX) and a liquid crystal capacitance formed between the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal LC, a protective film PSV1, and an alignment film ORI.
1, ORI2. Vlc is a midpoint potential.

The storage capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg where ΔVlc represents a change in the midpoint potential due to ΔVg. The change ΔVlc causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. Further, the holding capacitance element C
The add function has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and can reduce so-called burn-in in which a previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the area of overlap with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cadd.

The storage capacitance of the storage capacitor Cadd is 4 to 8 times (4 · C) the liquid crystal capacitance Cpix due to the writing characteristics of the pixel.
pix <Cadd <8 · Cpix), 8 to 3 for the parasitic capacitance Cgs
The value is set to about twice (8 · Cgs <Cadd <32 · Cgs).

(Method of connecting the storage capacitor element Cadd electrode line)
The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is set to the same potential as the common transparent pixel electrode ITO2 (Vcom), as shown in FIG. In the example of FIG. 18, the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GT0, the lead line INT, the terminal DT0, and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the last-stage scanning signal line Yend, connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. May be connected to receive the same.

(Connection Structure with External Circuit) FIG. 21 shows an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuits He and Ho mounted on a flexible wiring board (TAB, Tape Automated Bonding). FIG. 22 is a cross-sectional view of a main part of a liquid crystal display panel, in this example, connected to a video signal circuit terminal DTM of the liquid crystal display panel.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. Electrically terminals of package TCP
TTM and external connection terminal DTM (GT
M) is electrically connected to the signal from the integrated circuit CHI.
Is supplied to the panel PNL. 9 and FIG.
As shown in the figure, the external connection terminal DTM (GTM)
The conductive layer is not only the exposed electrical connection but also the protective layer
PSV1 and the external connection terminal D
TM (GTM) is packaged via anisotropic conductive film ACF.
Electrical connection with terminal TTM of di-TCP and conductive layer exposed
Part and the part where the conductive layer is covered with the protective film PSV1.
Continued. As described above, the package TCP is connected to the panel so that the tip thereof covers the protection film PSV1 exposing the connection terminal DTM on the panel PNL side. Therefore, the external connection terminal DTM (GTM) is connected to the protection film PSV1. Since at least one of the package TCPs is covered, the package TCP is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

(Manufacturing Method) Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the characters at the center are abbreviations of the process names, and the left side shows the flow of processing viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for the process D, the processes A to I are classified according to the respective photographic processes, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 After a silicon oxide film SIO is provided on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a ceric ammonium nitrate solution as an etchant. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg for connecting the gate terminal GTM, the bus line SHd for short-circuiting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown) To form

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a thickness of 2800 °
Second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Is provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid.

Step C, FIG. 13 After photo processing (after the formation of the anodic oxidation mask AO described above), 3
The substrate SUB1 is immersed in an anodic oxidation solution consisting of a solution prepared by diluting a solution obtained by adjusting the pH of the solution to 6.25 ± 0.05% with ammonia by using an ethylene glycol solution at a ratio of 1: 9, and the formation current density is 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized to form an anodic oxide film AOF having a thickness of 1800 ° on the scanning signal line GL, the gate electrode GT, and the electrode PL1. Step D, FIG. After introducing a nitrogen gas, a 2000-nm thick Si nitride film is provided. A silane gas and a hydrogen gas are introduced into a plasma CVD apparatus to provide a 2000-cm thick i-type amorphous Si film. Hydrogen gas and phosphine gas are introduced into the CVD apparatus to form an N (+) type amorphous Si film having a thickness of 300 °.

Step E, FIG. 14 After photographic processing, SF ₆ , CC
Using l ₄ , N (+) type amorphous Si film, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step F, FIG. 14 After the photo processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form

Step H, FIG. 15 A second conductive film d2 made of Cr having a thickness of 600 .ANG. Is provided by sputtering, and a second conductive film d2 having a thickness of 4000 .ANG.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the step B, and the second conductive film d2 is etched with the same liquid as in the step A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. I do. Next, CCl ₄ and SF ₆ are introduced into a dry etching apparatus to form an N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique using SF ₆ as a dry etching gas.

(Modification) In the above embodiment, the protective film PS
Although V1 is formed over the entire matrix AR, in the matrix, the protective film PSV1 is formed in a dot shape so as to cover only the transistor portion, or just the light-shielding film is removed where only the pixel electrode ITO1 portion is removed in order to increase the voltage utilization rate. BM
May be formed in a lattice-like pattern similar to.

[0084]

According to the embodiment of the present invention, since the conductive layer d3 of the lead-out line to the external connection terminal portion DTM containing Al is fixed inside the seal portion SL, the external connection terminals DTM, Since the GTM is covered with at least one of the protective film PSV1 and the base film BF1, contact is unlikely to occur.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 2 is a cross-sectional view showing one pixel and a periphery thereof taken along a cutting line 2-2 in FIG. 1;

FIG. 3 is a sectional view of the additional capacitance Cadd taken along section line 3-3 in FIG. 1;

FIG. 4 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

FIG. 5 is a plan view illustrating only layers g2 and AS of the pixel illustrated in FIG. 1;

FIG. 6 is a plan view illustrating only layers d1, d2, and d3 of the pixel illustrated in FIG. 1;

FIG. 7 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG.

FIG. 8 is a plan view of an essential part showing only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG.

FIG. 9 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 10 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 11 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 12 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to F on the substrate SUB1 side.

FIG. 15 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes GI on the substrate SUB1 side.

FIG. 16 is a plan view illustrating a configuration of a matrix peripheral portion of a display panel.

FIG. 17 is a panel plan view for explaining in more detail the peripheral part of FIG. 16 in a slightly exaggerated manner.

FIG. 18 is an enlarged plan view of a corner portion of the display panel including an electrical connection portion of the upper and lower substrates.

FIG. 19 is a cross-sectional view showing the vicinity of a panel corner and the vicinity of a video signal terminal on both sides with the pixel portion of the matrix in the center.

FIG. 20 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 21 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 22 is a fragmentary cross-sectional view showing a state where the tape carrier package TCP is connected to a video signal circuit terminal DTM of the liquid crystal display panel PNL.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line GI: insulating film, GT: gate electrode, AS: i-type semiconductor layer SD: source electrode or drain electrode, PSV: protective film, BM: light shielding film LC: liquid crystal, TFT: thin film transistor, ITO: transparent pixel electrode g, d: conductive film, Cadd: storage capacitor element, AOF: anodized film AO: anodized mask, GTM: gate terminal, DTM ...
Drain terminal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-64-19324 (JP, A) JP-A-2-115825 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1345 G02F 1/1343 G02F 1/1362 G02F 1/1333

Claims (5)

(57) [Claims] 1. A pixel electrode, said pixel electrode and a thin film transistor
And a matrix portion formed with a plurality of pixels having
A first substrate, a second substrate facing the first substrate, a liquid crystal layer, and confining the liquid crystal layer between the first and second substrates.
Seal putters provided around the matrix section
And a plurality of external connection terminals provided on the periphery of the first substrate.
And a plurality of transistors for supplying a signal to the thin film transistor.Signal line
And the external connection terminal and theSignal lineMultiple connecting each of
Lead wiring and an external circuit connected to the external connection terminal and supplying the signal
And a road,The external circuit has a terminal portion connected to the external connection terminal.
Having a terminal end, The lead wiring is made of a first conductive layer, The liquid crystal layer is closed
Formed from inside to outside of the sealed seal pattern
Outside of the seal pattern, and the lead wiring is covered with a protective film.
The external connection terminal isA first conductive layer covered with the protective film;
A first connection part, and a second conductive layer on the first conductive layer.
A second connection portion where a certain transparent conductive film overlaps;Has,External connection terminal And the connection with the external circuit,The second connection part is connected to the terminal part of the external circuit.
And The first connection portion and the terminal end of the external circuit overlap each other.
To A liquid crystal display device characterized by the above-mentioned. 2. A first device comprising a pixel portion having a plurality of pixels.
A substrate, a second substrate facing the first substrate, a liquid crystal layer, a seal pattern provided around the pixel portion, and a plurality of external connection terminals provided around the first substrate.
A plurality of signal lines provided in the pixel portion; and a plurality of leads for connecting the external connection terminals and the signal lines.
Wiring, a flexible circuit board connected to the external connection terminal, and
ComprisingThe flexible circuit board is connected to the external connection terminals.
Terminal portion and a terminal portion end portion, The lead wiring is made of a first conductive layer, Seal pattern
Are formed on the pixel portion side and the external connection terminal side, the lead-out wiring is covered with a protective film on the external connection terminal side, and the external connection terminal isFirstThe conductive layer is covered with the above protective film.
WasA first connection part, a second conductive layer on the first conductive layer,
A second connection portion where a certain transparent conductive film overlaps;Has,External connection terminal And connection with the above flexible circuit board
IsThe second connection part is connected to the terminal part of the external circuit.
Re ,The first connection portion and the terminal end of the external circuit overlap each other.
To A liquid crystal display device characterized by the above-mentioned. 3. A pixel electrode, said pixel electrode and a thin film transistor
And a matrix portion formed with a plurality of pixels having
A first substrate, a second substrate facing the first substrate, a liquid crystal layer, and confining the liquid crystal layer between the first and second substrates.
Seal putters provided around the matrix section
And a plurality of external connection terminals provided on the periphery of the first substrate.
And a plurality of transistors for supplying a signal to the thin film transistor.Signal line
And the external connection terminal and theSignal lineMultiple connecting each of
Lead wiring and an external circuit connected to the external connection terminal and supplying the signal
And a flexible circuit board on which the circuit is mounted.
AndThe external circuit has a terminal portion connected to the external connection terminal.
Having a terminal end,  The lead wiring is composed of a first conductive layer and a second conductive layer.
Inside the seal pattern where the liquid crystal layer is confined.
And the first conductive material of the lead-out wiring outside the seal pattern.
The layer is covered with a protective film, and the external connection terminal is connected to the first conductive layer.LayerCovered with the above protective film
WasThe first connection and the top The first conductive layer and the second conductive layer
A second connection portion where a certain transparent conductive film overlaps;Has,External connection terminal And connection with the above flexible circuit board
IsThe second connection part and the terminal part of the flexible circuit board
Is connected to ,The first connection portion and a terminal portion of the flexible circuit board
Overlap with the end A liquid crystal display device characterized by the above-mentioned. 4. The integrated circuit according to claim 1, wherein said external circuit supplies a drive signal.
Consists of a tape carrier package with
The end of the external circuit is the end of the flexible circuit board
The liquid crystal display device according to claim 1, wherein: 5. The method according to claim 1, wherein the first conductive layer comprises a chromium layer.
4. The liquid crystal display device according to claim 1, wherein: 6. The flexible circuit board according to claim 6, wherein the external connection terminal is connected to the flexible circuit board.
The connection to the plate is made by an anisotropic conductive film, and the first connection portion
Overlaps with the end of the terminal part with an anisotropic conductive film in between.
4. The liquid crystal display device according to claim 1, wherein: