JPH06195235A - Controller and processor - Google Patents

Abstract

PURPOSE:To provide a highly reliable controller with multiplex processor constitution. CONSTITUTION:Plural processors l and 2 provided with an error detection circuit 3, an ECC circuit 5, an error detection circuit 4 and an ECC circuit 6, an error check circuit 7 executing a verification operation by comparing the states of the processors 1 and 2, an RISC normality/abnormality decision circuit 8 monitoring the generation frequency of the most preferential interruption in the processors 1 and 2 and monitoring the presence or absence of abnormality, a retry control circuit 9 reading the data loss protection circuit 10 of an information saving memory 9a at the time of an error, restoring the processors 1 and 2 to a state before the error and re-executing them and a data loss protection circuit 10 suppressing the writing of error data into a local memory 21 at the time of the error are provided for the controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control technique and a processor, and more particularly to a technique effectively applied to a controller having a multiprocessor structure used for data transfer control and the like, and a processor having a RISC architecture.

[0002]

2. Description of the Related Art For example, in an external storage device in an information processing system, in response to a request for improvement in data transfer rate, a higher speed control operation is required in a controller or the like which controls data transfer. Also, reliability of control operation is important as well as speeding up of operation.

Therefore, a control operation is performed by constructing a controller using multiple processors having a so-called RISC architecture (hereinafter simply referred to as RISC), which enables high-speed operation by simplifying an instruction set. It is conceivable to improve the operation speed and the operation reliability.

[0004] Conventionally, such duplexing of RISC is disclosed in, for example, "Intel, Multimedia and Supercomputing Processor (a torrent system by 80960MC and M82965)" issued in January 1990, P3 to P325. As described in the literature, an error detection circuit is provided in each duplicated RISC, and one of them is used as a master and the other is used as a checker. By switching the roles of the master and the checker for each cycle, A technique is disclosed that attempts to detect an error on the side as well.

[0005]

In the above-mentioned prior art, as measures against errors, (1) when an error is detected, the error is confined in a limited area.

(2) The error detection area is separated from the system.

Functions such as the above are provided. That is, RI
It judges whether the SC is normal or abnormal and invalidates the RISC (error detection circuit) on the error side.

However, in the case of the above-mentioned prior art,
If an error occurs on the checker side that verifies the operation on the master side, there is no method for verifying the error.

Further, no consideration is given to data protection when an error occurs. Further, error detection is performed by comparing the information of the master and the checker to perform error recovery processing, but when an error occurs, the function of restoring error data to correct data is not specifically shown.

An object of the present invention is to provide a more reliable control technique having a multiprocessor configuration, focusing on the above problems.

Another object of the present invention is to provide a control technique capable of realizing data protection when an error occurs.

Still another object of the present invention is to provide a control technique capable of realizing correction of error data.

Still another object of the present invention is to provide a processor having a highly reliable operation by autonomously correcting error data.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, in a control device having a plurality of processors each having a function equivalent to each other and each having a built-in error detection circuit, the control device is provided outside each processor, and the state matching between the processors is performed. A first check circuit for detecting an error by monitoring the mismatch is provided.

According to the present invention, in the control device according to the first aspect, an ECC circuit is built in each processor, and the first check circuit is the information between the error detection circuits or the information between the ECC circuits. An error is detected by monitoring the match / mismatch of information.

Further, according to the present invention, in the control device according to claim 1 or 2, the first check circuit detects an error and corrects error data by collating the parity in each processor. Is.

The present invention is the control device according to claim 1, 2 or 3, wherein the first check circuit is provided.
Non-maskable interrupts (NM
A second check circuit for detecting the presence / absence of an abnormality in each processor by monitoring at least one of the occurrence state of I) and the error detection state of the error detection circuit is provided, and the error by the second error check circuit is provided. At the time of detection, the operation of disconnecting the first check circuit and the abnormal processor is performed.

Further, according to the present invention, in the control device according to claim 1, 2, 3 or 4, an execution state storing means for storing at least a part of the execution state in the processor is provided inside, and when an error occurs, It is provided with a retry control circuit for returning the inside of the processor to the state before the occurrence of the error and re-execution.

Further, according to the present invention, in the control device according to claim 1, 2, 3, 4 or 5, when an error occurs,
The data loss protection circuit is provided for suppressing the output of the data obtained by the error to the outside.

Further, according to the present invention, in the control device according to claim 2, 3, 4, 5 or 6, when an error is detected,
The error data is corrected by the ECC circuit built in the processor.

The present invention also provides claims 1, 2, 3, 4,
In the control device described in 5, 6, or 7, a processor having a RISC architecture is used.

The present invention also provides an error detection circuit and an E in a processor having a RISC architecture.
It has a built-in CC circuit.

[0025]

According to the above-mentioned control device of the present invention, the presence or absence of an error in each processor can be surely grasped by the first check circuit provided outside the multiple processors, so that it is possible only between the processors. Error detection becomes more reliable as compared with the conventional case where error verification is performed, and the reliability of operation is improved.

Further, by monitoring at least one of the non-maskable interrupt (NMI) occurrence state in each processor and the error detection state in the error detection circuit (for example, error occurrence frequency), an abnormality in each processor is detected. Is provided with a second check circuit for detecting the presence or absence of
Since the check circuit and the abnormal processor are disconnected, the operation reliability is improved.

In addition, when the error is detected in the first or second check circuit, the retry control circuit is activated to enable the error recovery operation and improve the reliability of the operation.

Further, since the data loss protection circuit for suppressing the output of the data obtained by the error to the outside when the error occurs is provided, the data loss due to the writing of the error data can be surely prevented.

Further, by incorporating an ECC circuit in each processor, error data can be corrected when an error occurs.

Further, according to the processor of the present invention, since the ECC circuit is built in together with the error detection circuit, the error data can be corrected autonomously and the reliability of the operation is improved.

[0031]

First Embodiment A control device according to one embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of the control device of this embodiment.

The control device of this embodiment is, for example, a RISC.
A plurality of processors 1 and 2 having an architecture and performing equivalent operations are provided, and each is connected to a system bus 20. Further, the system bus 20 includes the processor 1 and the processor 2 concerned.
A local memory 21 that is accessed by is connected via a memory control unit 22. Further, the system bus 20 is also connected to an external interface control unit 23 that exchanges data with an external host device (not shown).

Inside each of the processors 1 and 2,
An error detection circuit 3 and an error detection circuit 4 for detecting an error in each processor 1 and 2 and an error in the information by adding an error correction code to information such as an address and data in each processor 1 and 2 An ECC circuit 5 and an ECC circuit 6 that perform detection and correction operations are provided, respectively.

An error check circuit 7, a RISC normal / abnormal determination circuit 8, a retry control circuit 9, and a data loss protection circuit 10 are provided outside the processors 1 and 2.

The error check circuit 7 has a control logic for verifying the operation of the processor 1 and the processor 2 by collating various information as will be described later between the processor 1 and the processor 2.

The RISC normality / abnormality determination circuit 8 includes the frequency of error detection in the error detection circuits 3 and 4 provided in the individual processors 1 and 2, and the processor 1
And 2 to monitor the occurrence frequency of the non-maskable highest-priority interrupt, and to monitor the presence or absence of abnormality in each of the processors 1 and 2.
If an abnormality is detected in any of the above, control logic is provided to perform an operation of disconnecting the processor 1 or 2 on the abnormal side and the error check circuit 7 from the system.

The retry control circuit 9 is internally provided with an information save memory 9a for saving information in the processors 1 and 2, and an error detection circuit 7 or error detection provided in each of the processors 1 and 2 is detected. When an error is detected in the circuits 3 and 4, it is provided with control logic for returning the states of the processors 1 and 2 to the states before the error occurrence and re-execution.

The data loss protection circuit 10 is connected to the system bus 20, and when an error is detected in the error check circuit 7 or the error detection circuits 3 and 4 provided inside each of the processors 1 and 2. In addition, for example, a control logic is provided that operates the memory control unit 22 to prevent error data from being directly written in the local memory 21 and avoids data loss.

Table 1, Table 2, Table 3, and Table 4 summarize an example of the operation of each unit as described above.

[0041]

[Table 1]

[0042]

[Table 2]

[0043]

[Table 3]

[0044]

[Table 4]

An example of the operation of the control device of this embodiment will be described below.

[Operation 1] First, the operation of each of the processors 1 and 2 is monitored by the error detection circuits 3 and 4 existing inside each of the processors 1 and 2. An error check circuit 7 provided externally compares the signals of the error detection circuits 3 and 4 in the processors 1 and 2, respectively.

At this time, at the same time, the RISC normal / abnormal determination circuit 8 monitors whether or not the highest priority interrupt (NMI) is generated in each of the processors 1 and 2, and, for example,
If the interrupt is input several times in succession, it is determined that an abnormality has occurred, and the processor 1 or 2 on the abnormal side and the error check circuit 7 are disconnected from the system.

In the retry control circuit 9, the information is executed inside the processors 1 and 2, and at the same time, the information is sequentially written in the information saving memory 9a.
The information saving memory 9a has a capacity capable of storing, for example, about 4 words, and the storage is performed by writing one word at a time. When the information saving memory 9a becomes full, for example, the storage location of the oldest data is overwritten.

When an error occurs, the writing to the information save memory 9a and the input of new data to the processors 1 and 2 are interrupted, and the latest data stored in the information save memory 9a is saved. The data is read out and input to the processors 1 and 2, and the processors 1 and 2 are returned to the state before the error occurred and re-executed.

In the data loss protection circuit 10, when the error detection circuits 3 and 4 built in the processors 1 and 2 or the external error check circuit 7 detect an error, the data processed in the process of the error is detected. Writing to the local memory 21 is suppressed. This operation, for example,
This is performed by issuing a write inhibition command to the memory control unit 22.

As a result, it is possible to reliably prevent the data loss due to the data in the local memory 21 being overwritten by the incorrect data when the error occurs.

[Operation 2] As an error checking method in the processors 1 and 2, as shown in FIG. 2, vertical parity (VRC) and horizontal parity (LRC) are set in addresses and data, and even parity or odd parity is set. An error is detected by checking whether it is parity. When vertical parity and horizontal parity are set, error data can be corrected to normal data.

In this case, the error check circuit 7 checks the parity of each of the processors 1 and 2 to detect an error.

The RISC normality / abnormality determination circuit 8 monitors the error detection frequency in the error detection circuits 3 and 4 incorporated in the processors 1 and 2, and the error detection circuits 3 and 4 detect an error several times. When it is detected continuously, it is judged to be abnormal, and the processors 1 and 2
By performing the operation of disconnecting the error check circuit 7 from the abnormal side and the error check circuit 7, the control function of the control device is maintained.

In this case, the retry control circuit 9 and the data loss protection circuit 10 operate in the same manner as in the case of the above action 1.

[Operation 3] Error detection in each processor is performed by the ECC circuit 5 and the ECC circuit 6 incorporated in each of the processor 1 and the processor 2.
That is, the ECC circuits 5 and 6 determine whether the data is normal or abnormal.

Further, the error check circuit 7 uses the ECC circuits 5 and E of the processors 1 and 2, respectively.
Perform an ECC compare check in the CC circuit 6,
The presence or absence of errors is also monitored externally.

Further, the RISC normal / abnormal judgment circuit 8 is
The retry control circuit 9 performs the operation described in the operation 1, and the data loss protection circuit 10 performs the operation described in the operation 1.

As described above, according to the control device of the present embodiment, not only the verification operation by the error detection circuit 3 and the error detection circuit 4 provided in the processor 1 and the processor 2 having the functions equivalent to each other, Since the verification operation by the state comparison of the processor 1 and the processor 2 is performed by the error check circuit 7 provided externally, the reliability of the operation in the control device in which the processors 1 and 2 are multiply provided is improved.

Further, processor 1 and processor 2
The RISC normal / abnormality determination circuit 8 for monitoring the occurrence frequency of the highest priority interrupt in the above and the error frequency in the error detection circuits 3 and 4 is provided. Can be separated from multiple processors 1
And the reliability of the operation in the control device provided with the processor 2 is improved.

Further, the retry control circuit 9 can retry the operation of the processor 1 and the processor 2 when an error occurs, and the error recovery performance is improved.

Further, by providing the data loss protection circuit 10, the processor 1 and the processor 2 can be operated at the time of error.
The loss of data due to the writing of erroneous data output from the local memory 21 is avoided, and the operation reliability and error recovery performance in the control device are improved.

[0063]

Second Embodiment FIG. 3 is a conceptual diagram showing the configuration of a processor which is an embodiment of the present invention.

The processor 30 of this embodiment has a RISC architecture and has an error detection circuit 31 and an ECC circuit 32 built therein.

As a result, the ECC circuit 32 can autonomously correct the error data at the time of error, and the reliability of the operation of the processor 30 is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first embodiment, the control device in the case where the multiplicity of the processors is 2 has been described as an example. However, the control device may have three or more processors.

[0068]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the control device of the present invention, it is possible to further improve the reliability of the control device having the multiprocessor structure.

Further, according to the control device of the present invention, it is possible to obtain the effect that, in the control device having the multiprocessor structure, it is possible to protect the data when an error occurs.

Further, according to the control device of the present invention, it is possible to obtain the effect that correction of error data can be realized in a control device having a multiprocessor structure.

According to the processor of the present invention, it is possible to obtain the effect that the reliability of the operation is improved by autonomously correcting the error data.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a control device that is an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a parity setting method in a processor that constitutes a control device that is an embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a configuration of a processor that is an embodiment of the present invention.

[Explanation of symbols]

1 processor 2 processor 3 error detection circuit 4 error detection circuit 5 ECC circuit 6 ECC circuit 7 error check circuit (first check circuit) 8 RISC normal / abnormal determination circuit (second check circuit) 9 retry control circuit 9a information save Memory 10 Data loss protection circuit 20 System bus 21 Local memory 22 Memory control unit 23 External interface control unit 30 Processor 31 Error detection circuit 32 ECC circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Kurosu 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. Microelectronics Device Development Laboratory

Claims (9)

[Claims] 1. A control device having multiple processors each having a function equivalent to each other and each having an error detection circuit built therein, the control device being provided outside each of the processors, and matching of states between the processors. -A control device comprising a first check circuit for detecting an error by monitoring a mismatch. 2. An EC within each of the processors is provided.
The C (Error Correting Code) circuit is built in, and the first
2. The control device according to claim 1, wherein the check circuit detects the error by monitoring whether or not the information between the error detection circuits or the information between the ECC circuits matches. 3. The control device according to claim 1, wherein the first check circuit detects an error and corrects error data by collating a parity in each processor. 4. A non-maskable interrupt (NM) in each of the processors together with the first check circuit.
By monitoring at least one of the occurrence state of I) and the error detection state in the error detection circuit,
A second check circuit for detecting whether or not there is an abnormality in each of the processors is provided, and when an error is detected by the second error check circuit, an operation of disconnecting the first check circuit and the abnormal processor is performed. The control device according to claim 1, 2, or 3. 5. A retry is provided which internally stores at least a part of an execution state of the processor, and when an error occurs, returns the internal state of the processor to the state before the error and performs the retry. A control circuit is provided, Claim 1, 2, 3 or 4 characterized by the above-mentioned.
The control device described. 6. A data loss protection circuit for suppressing the output of the data obtained by the error to the outside when the error occurs.
4. The control device according to 4 or 5. 7. The control device according to claim 2, wherein the error data is corrected by the ECC circuit incorporated in the processor when an error is detected. 8. The processor is a RISC (Reduced)
5. A processor having an Instruction Set Computer architecture.
Control device according to 4, 5, 6 or 7. 9. A processor having a RISC architecture, which incorporates an error detection circuit and an ECC circuit.