JPH06176074A - Data processor - Google Patents

Abstract

PURPOSE:To improve the availability of an internal memory by storing only the selection/projection results of the input file data into the internal memory. CONSTITUTION:When a selection/projection input command is given to an operational processor 16 from a host computer 10, an engine control processor 162 sends the selecting conditions and the projecting designation included in the input command to an engine interface processor 161 together with the address of an input buffer of a large capacity memory 163 for execution of the input projecting. The processor 161 secures the input buffers IB1 and IB2 in its own local memory 168 to input the file data, i.e., the subject of selection/projection to one of both buffers and also to apply the selection subject to the selecting conditions and the projection subject to the projecting designation against the data already supplied to the other buffer. Then the processor 161 outputs these selection and projection results to the designated input buffer of the memory 163.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises an arithmetic processing unit for executing arithmetic processing such as sorting or relational algebraic arithmetic on file data to be arithmetically operated in response to a request from a host device, and particularly to selection and projection processing. The present invention relates to a data processing device suitable for.

[0002]

2. Description of the Related Art Generally, a computer system is provided with a dedicated database arithmetic processing unit for performing sort processing, relational database search processing, and the like at high speed. This database arithmetic processing device is provided with an arithmetic circuit called a hardware sorter, and by using this arithmetic circuit, sorting, relational algebraic arithmetic and the like according to arithmetic processing requests from the host device are executed at high speed.

Conventionally, in this type of database arithmetic processing device, the input process, the selection process, and the projection process are performed independently of each other. Specifically, first, all the target file data are input to the internal memory of the database arithmetic processing device. Next, a selection process is performed on the file data input to the internal memory, a projection process is further performed on the selection process result, and the result is output to the secondary storage device or the internal memory. It

However, in such a processing method, although only the result of the selection and the projection is originally required, all the file data is input to the internal memory,
There is a drawback that the storage area of the internal memory is additionally consumed. According to this method, when the total of the file data size and the selection / projection result size exceeds the size of the internal memory, there is no other processing method than using the work file on the secondary storage device as a special process. , There were more serious problems. This problem has been fatal for a database arithmetic processing device whose primary purpose is to improve performance.

[0005]

As described above, conventionally, since all the file data to be selected / projected are input to the internal memory of the database arithmetic processing unit, the utilization efficiency of the internal memory is significantly reduced, as a result,
There is a problem that the overall processing performance of the database arithmetic processing device is also reduced.

The present invention has been made in consideration of such a point, and a selection process and a projection process are simultaneously executed in parallel during the input process of file data to select / select.
It is an object of the present invention to provide a data processing device capable of storing only a projection result in an internal memory, thereby improving the utilization efficiency of the internal memory and dramatically improving the processing performance of the entire database arithmetic processing device.

[0007]

The present invention has a host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device. In a data processing device comprising a calculation processing device (database calculation processing device) for executing a predetermined calculation process on the file data to be calculated in response to a request from a host device,

Input means for inputting file data to be calculated from the secondary storage device via the above-mentioned path in accordance with a calculation request from the host device, and a selection projection input command including selection conditions and projection designation is given from the host device. In the case where the operation target file data is input from the secondary storage device, the input means for performing the selection / projection process according to the above selection condition and the projection specification on the file data, and the input operation target An operation processing means for performing sorting or relational algebraic operation on the file data or the result of the selection / projection processing, and an inside for storing the operation target file data or the selection / projection processing result and the operation result by the operation processing means A memory and an output means for outputting the operation result to the secondary storage device are provided in the database operation processing device. The database operation processing device is configured to execute the input of the operation target file data and the selection / projection process for the same data in parallel by using the input means in accordance with the selection projection input command from the host device. And

As described above, when the input means in the database arithmetic processing device is provided with the selection / projection processing function and the selection projection input command is given from the host device, the input data is being processed by the input means. In addition, by the selection / projection processing function of the input means, by executing the selection processing according to the selection condition included in the selection projection input command and the projection processing according to the projection specification on the input data at the same time, It is possible to store only the result of the selection / projection process in the internal memory instead of the input file data. This improves the utilization efficiency of the internal memory, and facilitates the securing of the buffer area on the internal memory that is required by the other arithmetic processing that is continued after the above-mentioned input processing. It becomes possible to dramatically improve the total performance of the database arithmetic processing device, by eliminating the process of using the file.

Further, according to the present invention, a multiprocessor configuration including first to third processors is adopted for the database arithmetic processing device, and data input / output between the database arithmetic processing device and the secondary storage device is performed. , When a selection projection input command is given, the selection processing according to the selection condition in the command and the projection processing according to the projection designation are performed in parallel with the input processing by the first processor, and the calculation processing using the calculation circuit is performed. The second characteristic is that the functions of the second processor and the overall control are distributed to the third processor.

In this configuration, the load is efficiently distributed by the first to third processors, and the first processor
The parallel processing of the data input / output by the processor and the selection / projection processing by the same processor in parallel with the input processing by the same processor and the arithmetic processing by the second processor are enabled, and the parallel operation is performed by the third processor. By controlling the execution, it is possible to sufficiently improve the operation performance of the database arithmetic processing device.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall system configuration of a data processing apparatus according to an embodiment of the present invention. This data processing device includes a host computer 10 and a database arithmetic processing device (database engine; DBE).
16 and an external storage device, for example, a magnetic disk device 17.

The host computer 10 includes a CPU 11,
Main memory 12, first and second channel devices 14,
It is composed of 15. The CPU 11, main storage device 12, and channel devices 14 and 15 are interconnected via a system bus 13.

The host computer 10 and the database processing unit 16 are connected by a channel unit 14,
The host computer 10 and the magnetic disk device 17 are connected by a channel device 15. Furthermore, the database arithmetic processing unit 16 and the magnetic disk unit 17 are connected via a dedicated access path 18.

The CPU 11 controls the host computer 10 as a whole, and requests the database arithmetic processing unit 16 to execute various arithmetic processes such as sorting and relational algebraic operations, and also to create an index file. To do. The main memory 12 has a database operation processing device 1
A command group for instructing the calculation target file and the calculation contents for 6 is stored. This command group includes a selection projection input command for inputting file data and requesting selection / projection processing for the same data.
This selection projection input command has a selection condition and a projection specification.

Database processing unit (DBE) 16
Is for executing arithmetic processing on the data of the arithmetic target file based on a command from the CPU 11,
The magnetic disk device 17 is directly accessed via the path 18 in order to input the calculation target file and output the calculation result.

This database arithmetic processing unit (DBE)
16 is an engine interface processor (EIP)
161, engine control processor (ECP) 162, large capacity memory (EBDM) 163, hardware (HW)
It is composed of a sorter control processor (ECAM) 164, a parallel sorting module (PSOM) 165, and a parallel relational algebra operation module (PRAM) 166.

Engine Interface Processor (EI
P) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
M) 164 of the three processors are interconnected by an internal bus 167, and a large capacity memory (EBDM) 1
A tightly coupled multiprocessor having 63 as a shared memory is configured. The large capacity memory (EBDM) 163 is arranged in a common address space of each of the three processors.

The functions of these three processors, that is, the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164 are distributed. In this case, in order to efficiently perform their specific roles, each of these processors
Although tightly coupled, the operation is controlled by an independent monitor (operating system for microprocessor) suitable for each.

Engine Interface Processor (EI
P) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
The functional distribution of M) 164 is as follows.

First, the engine interface processor (EIP) 161 carries out communication between the host computer 10 and the database arithmetic processing unit 16 and is also connected to the disk controller of the magnetic disk unit 17 via a path 18. It controls data input / output with the disk device 17. Further, the engine interface processor (EIP) 161 also performs reconfiguration processing of an output file when outputting data to the magnetic disk device 17.

In communication with the host computer 10, an engine interface processor (EIP) is used.
161 indicates the CPU 11 via the first channel device 14.
It receives the command sent from the and sends it to the engine control processor (ECP) 162. Further, the engine interface processor (EIP) 161 receives the status as a command result sent from the engine control processor (ECP) 162, and sends it back to the CPU 11 via the first channel device 14.

Next, in inputting / outputting data from / to the magnetic disk device 17, the engine interface processor (EIP) 161 is operated by the engine control processor (EC).
P) receives an input / output request from the memory 162 and transfers data between the large capacity memory (EBDM) 163 and the magnetic disk device 17. At this time, if the selection projection input command is given from the CPU 11, the engine interface processor (EIP) 161 follows the request from the engine control processor (ECP) 162, and at the time of input, according to the selection condition in parallel with the input processing. Selection processing and projection processing by projection specification are performed.

Engine Interface Processor (EI
P) 161 has a local memory 168. When executing the selective projection input command, the memory 16
Two input buffers IB1 and IB2 are secured on the eight.

Engine control processor (ECP) 162
Is an engine interface processor (EIP) 16
1, a large capacity memory (EBDM) 163, and a hardware sorter control processor (ECAM) 164 are controlled via an internal bus 167. When the command from the CPU 11 is a calculation processing command such as sort or relational algebraic calculation, the engine control processor (ECP) 162 manages generation and execution of various command processing processes corresponding to the command. The engine control processor (EC
P) 162, in the case of the selected projection input command, transmits the selection condition and the projection designation included in the command to the engine interface processor (EIP) 161.
It controls the execution of the file data input process and the selective projection process for the same data in parallel.

The large-capacity memory (EBDM) 163 stores file data to be operated read from the magnetic disk device 17, the result of selective projection by the engine interface processor (EIP) 161 for the data, and the CPU 1
Various arithmetic processing commands, selective projection input commands, hardware sorter control processor (EC
AM) 164, Parallel Sorting Module (PSO
M) 165, and parallel relational algebra calculation module (PR
It is a shared memory that stores the calculation result by the AM) 166, and further the integrated result of the calculation result by the engine control processor (ECP) 162. The file data to be calculated is stored in the input buffer unit in the large capacity memory (EBDM) 163, and the calculation processing result is stored in the large capacity memory (EBD).
M) Stored in the output buffer unit in 163.

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
Based on the command from 62, the operations by the parallel sorting module (PSOM) 165 and the parallel relational algebraic operation module (PRAM) 166 are controlled.

In this case, the hardware sorter control processor (ECAM) 164 is a large capacity memory (EBDM).
Parallel sorting module (PS
The calculation result output from the parallel relational algebraic calculation module (PRAM) 166 is stored in the large capacity memory (EBDM) 163. When the data is input to the parallel sorting module (PSOM) 165, First, a key cutout process is executed. In this key cutout processing, the hardware sorter control processor (ECAM) 164 cuts out only the calculation target key field required for the calculation from each calculation target record, and adds the start address of the record in the large capacity memory (EBDM) 163 to it. A record identification number (record identifier) RID which is (a pointer indicating) is added and sent to the parallel sorting module (PSOM) 165.

Parallel sorting module (PSOM)
165 is a hardware sorter control processor (ECA
M) is a dedicated hardware circuit that is driven by 164 and executes sorting in parallel, and is connected to a parallel relational algebraic operation module (PRAM) 166. The parallel sorting module (PSOM) 165 is called a pipeline merge sorter, and is formed by cascade-connecting a plurality of sort cells that perform 2-way merge.

Parallel Relational Algebra Operation Module (PRAM)
166 is JOIN (join) in the relational database
Is a dedicated hardware circuit that executes relational algebraic operations such as and RESTRICT (constraints, semi-joins) in parallel,
The sorted data is input from the parallel sorting module (PSOM) 165, and the calculation result is output to the hardware sorter control processor (ECAM) 164. When executing only the sorting process, the parallel relational algebraic operation module (PRAM) 166 functions as the final sort cell.

As described above, the engine interface processor (EIP) 161 and the engine control processor (E
The CP) 162 and the hardware sorter control processor (ECAM) 164 are distributed with functions for executing various arithmetic processes such as sort process and select process. In this case, these processors operate asynchronously except for the transfer of data in the buffer on the large capacity memory (EBDM) 163, and execute the respective functions in parallel. That is, processing such as sorting and selecting is usually composed of selective projection input processing, arithmetic processing, and output processing, but the hardware sorter control processor (ECAM) 1
The calculation processing under the control of 64 is executed in parallel with the selection projection input processing of the calculation target data by the engine interface processor (EIP) 161. When the engine control processor (ECP) 162 needs to perform an integrated processing of the calculation result from the hardware sorter control processor (ECAM) 164, the integrated processing and the output processing by the engine interface processor (EIP) 161 are also performed in parallel. Is executed. Next, a series of processes directly related to the present invention performed by the data processing device shown in FIG. 1 will be described with reference to the flowcharts of FIGS.

First, (the CPU of the host computer 10
It is assumed that the selective projection input command is sent from 11) to the database arithmetic processing unit (DBE) 16 via the system bus 13 and the first channel unit 14. This selective projection input command is transmitted to the engine control processor (ECP) 162 via the engine interface processor (EIP) 161 and the processor (EC
P) 162 is received (step S1 in FIG. 2).

Then, the engine control processor (EC
P) 162 extracts only the selection condition part and the projection designating part from the selection projection input command, and outputs the large capacity memory (EB).
DM) 163 and the address of an input buffer (not shown) for storing the selected projection result are transmitted to the engine interface processor (EIP) 161 as an input start instruction via the internal bus 167 (step S2 in FIG. 2). ).

Engine Interface Processor (EI
P) 161 is an engine control processor (ECP) 16
When receiving the input start instruction from 2, the input start flag (not shown) is first set to "1" as the processing of the input start instruction to indicate that the input start state is set (step S11 in FIG. 3). ).

Next, the engine interface processor (EIP) 161 stores the address of the input buffer for storing the selected projection result, the selection condition and the projection designation in its own internal table (not shown) (step S1 in FIG. 3).
2). And engine interface processor (EI
P) 161 secures, for example, two input buffers IB1 and IB2 of the same size in the local memory 168 (step S13 in FIG. 3), and ends the input start instruction processing.

On the other hand, engine control processor (ECP)
162 is an engine interface processor (EI
P) 161 sends an input start instruction to the processor (E)
The (IP) 161 input processing (the input processing routine therefor) is called (step S3 in FIG. 2).

Then, the engine interface processor (EIP) 161 starts executing the input processing routine shown in FIGS. First, the engine interface processor (EIP) 161 determines whether the input start flag is "1" (step S2 in FIG. 4).
1). In the first process, the input start flag is "1". In this case, the engine interface processor (E
The IP) 161 sets the input start flag to “2” to indicate that it is not the first time thereafter (step S in FIG. 4).
22) Further, a buffer switching flag (not shown) is set to "1" to indicate that there is valid data in the input buffer IB1 (step S23 in FIG. 4).

Next, the engine interface processor (EIP) 161 is connected to the engine control processor (EC).
P) The file data designated by 162 is read from the magnetic disk device 17 via the path 18 and input to the input buffer IB1 (step S24 in FIG. 4). Data input to this input buffer IB1 is the same as that of the buffer IB1.
Is full (or until the target file data ends).

Engine Interface Processor (EI
P) 161 determines whether or not the file data to be input is the end when the data input to the input buffer IB1 is executed (step S25 in FIG. 5). If not, the buffer switching flag is "1". It is determined whether or not (step S25 in FIG. 5). In the first process, the buffer switching flag is "1". In this case, the engine interface processor (EIP) 161 sets the buffer switching flag to "2" in order to validate the input buffer IB2 (step S27 in FIG. 5).

Next, the engine interface processor (EIP) 161 selects selective projection end flag (not shown).
Is determined to be "2" (step S2 in FIG. 5).
8). The selective projection end flag indicates that the selective projection process for the data in the input buffer IB1 is completed when it is "1", and the selective projection process for the data in the input buffer IB2 is completed when it is "2". Indicates that The initial value of the selective projection end flag is "2", so the determination in the first step S28 is YES.

When the determination in step S28 is YES, that is, when the selection projection flag is "2", the engine interface processor (EIP) 161 determines that the input buffer IB
It is determined that the selective projection process for the data in 1 is possible, and the selective projection routine is called with the buffer type information indicating the input buffer IB1 and the pointer (buffer address) of the buffer IB1 as arguments (step S29 in FIG. 5). .

Then, the engine interface processor (EIP) 161 reads the subsequent file data to be selected and projected from the magnetic disk device 17 and inputs it to the input buffer IB2 (step S30 in FIG. 5). Thus, the (first) input processing routine called by the engine control processor (ECP) 162 ends.

Then, the engine control processor (EC
P) 162 is an engine interface processor (E
It is checked whether or not the input completion is notified from the (IP) 161 (steps S4 and S5 in FIG. 2). As in this example, when the input completion is not notified, the engine control processor (ECP) 162 returns to step S3 and performs the input processing (the input processing routine therefor) by the engine interface processor (EIP) 161. call. As a result, the second input processing routine is executed.

In the present embodiment, the selective projection routine is called in step S29 (see FIG. 5) of the first input processing routine described above, whereby the selective projection processing according to the routine is executed by the engine interface processor. The (EIP) 161 executes the following in parallel with the input processing routine.

First, the engine interface processor (EIP) 161 selects the data of the input buffer (here, the input buffer IB1) of the address passed as an argument when it is called from the input processing routine according to the selection condition on the internal table. Then, the selection result is projected according to the projection specification on the internal table, and the projection result (and thus the selected projection result) is the address of the input buffer for storing the selected projection result stored in the internal table, that is, the engine. Control processor (ECP) 162
The data is output to the input buffer on the large capacity memory (EBDM) 16 designated by (step S41 in FIG. 7).

Next, the engine interface processor (EIP) 161 determines that the type of the input buffer subjected to the selective projection processing in step S41 is IB1 or IB.
2 is determined (step S42 in FIG. 7),
In the case of IB1 as in this example, the selection projection end flag is set to "1" to indicate the end of the selection projection for the data in the input buffer IB1, and the selection projection routine is exited. If the selective projection processing has been performed on the data in the input buffer IB2, the selective projection end flag is set to "2" and the selective projection routine is exited.

Since the input start flag is "2" in the second input processing routine, the determination at the first step (step S21 in FIG. 4) of the routine is NO. In this case, skip steps S22 to S24 in FIG.
It progresses to step S25 of FIG. Here, if the file data to be input is not the end, it is judged whether or not the buffer switching flag is "1" (step S26 in FIG. 5). The buffer switching flag has been set to "2" in the process of the previous step S27, and therefore the determination in step S26 is NO.

Then, the engine interface processor (EIP) 161 sets the buffer switching flag to "1" in order to validate the input buffer IB1 (step S31 in FIG. 6).

Next, the engine interface processor (EIP) 161 selects selective projection end flag (not shown).
Is determined to be "1" (step S3 in FIG. 6).
2). Here, if the first selection projection routine has been completed, that is, if the selection projection process for the data in the input buffer IB1 has been completed (FIG. 7, step S4).
The selection projection end flag is "1" (due to 3),
The determination in step S32 is YES. If the selective projection processing for the data in the input buffer IB1 has not yet been completed and the selective projection end flag is not “1”,
Engine interface processor (EIP) 161
Waits for the selective projection end flag to become "1".

When the determination in step S32 is YES, that is, when the selective projection process for the data in the input buffer IB1 is completed, the engine interface processor (EIP) 161 performs the selective projection process for the data in the input buffer IB2 this time. Determined to be possible,
The selection projection routine is called with the buffer type information indicating the input buffer IB2 and the pointer (buffer address) of the buffer IB2 as arguments (step S3 in FIG. 6).
3).

Then, the engine interface processor (EIP) 161 reads the subsequent file data to be selected and projected from the magnetic disk device 17 and inputs it to the input buffer IB1 (step S34 in FIG. 6). Thus, the (second) input processing routine called by the engine control processor (ECP) 162 ends.

As described above, in this embodiment, when the selective projection input command is given from the (host CPU 11) of the host computer 10 to the database arithmetic processing unit (DBE) 16, the engine interface processor (EI)
P) The two input buffers IB1 and IB2 are secured in the local memory 168 in the P. 161, and the file data to be selected and projected is transferred to the engine interface processor (E).
While the IP) 161 is inputting to one of the input buffers, the processor (EIP) 161 itself selects the selection condition for the data already input to the other input buffer in parallel with the input processing. According to the input buffer IB1 and the input buffer IB, the selection processing according to the above and the projection processing according to the projection designation are performed, and the result (selection projection result) is output to the input buffer on the large capacity memory (EBDM) 163.
It is designed to be performed while alternately switching 2 and.

Therefore, the target file data can be processed at a higher speed than the conventional method in which all the target file data is input to the input buffer on the large capacity memory (EBDM) 163 and then the selective projection process is performed on the data in the buffer. The required size of the input buffer on the large capacity memory (EBDM) 163 can be significantly reduced.

It should be noted that two input buffers on the large-capacity memory (EBDM) 163 are secured and used alternately, so that the data after the selective projection processing outputted to this input buffer is continued thereafter. Other arithmetic processing, for example, a hardware sorter control processor (ECAM) 164
The sort processing and the like under the control of can be performed in parallel with the selective projection processing.

The above processing is performed while alternately switching between the input buffer IB1 and the input buffer IB2, and when the file data which is the target of the selective projection ends, the engine interface processor (EIP) 16
1 determines YES in step S25 of FIG. In this case, the engine interface processor (EIP) 16
1 is an engine control processor (ECP) 16 indicating completion of input
2 is notified (step S35 in FIG. 5), and the input processing routine ends.

Engine Control Processor (ECP) 162
When the input processing routine is finished, the engine interface processor (EIP) 161 checks whether or not the input completion is notified (steps S4 and S5 in FIG. 2). When the input completion is notified as in this example, the engine control processor (ECP) 162 ends the selective projection input process.

[0058]

As described above, according to the present invention, in the arithmetic processing unit (database arithmetic processing unit) in response to the selective projection input command from the host unit, the input means (secondary storage unit of the processing unit) The first processor for inputting / outputting data between the two) has a selection projection processing function in addition to the input processing function for the file data, so that the selection processing and projection for the same data are performed in parallel with the input processing for the file data. By executing the processing, the load on the host device and the load on the database processing device can be reduced, and only the result of the selection / projection process is stored in the internal memory instead of the input file data. As a result, the internal memory area can be used effectively, and the use of work files is not required, and efficient data processing can be achieved for the entire system. Kill.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall system configuration of a data processing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a selective projection input process with an engine interface processor (EIP) 161 by an engine control processor (ECP) 162 in the embodiment.

FIG. 3 is a flowchart for explaining an input process by an engine interface processor (EIP) 161 and a start process required for a selective projection process in parallel with the same in the embodiment.

FIG. 4 is a diagram showing a part of a flow chart for explaining an input process by an engine interface processor (EIP) 161 and a selective projection process in parallel therewith in the embodiment.

FIG. 5 is a view showing another part of the flowchart for explaining the input processing by the engine interface processor (EIP) 161 and the selective projection processing in parallel therewith in the embodiment.

FIG. 6 is a view showing the rest of the flowchart for explaining the input processing by the engine interface processor (EIP) 161 and the selective projection processing in parallel therewith in the embodiment.

FIG. 7 is a flowchart for explaining in detail the selective projection processing by the engine interface processor (EIP) 161 in the embodiment.

[Explanation of symbols]

10 ... Host computer, 11 ... CPU, 13 ... System bus, 16 ... Database processing unit (DB)
E), 17 ... Magnetic disk device (secondary storage device), 18
... Path, 161 ... Engine interface processor (EIP, first processor), 162 ... Engine control processor (ECP, third processor), 163 ... Large-capacity memory (EBDM, internal memory), 164 ... Hardware (HW) Sorter control processor (ECAM, second
Processor), 168 ... Local memory, IB1, I
B2 ... Input buffer.

Claims (2)

[Claims] 1. A host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device, wherein the operation is performed in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic process on target file data, the arithmetic processing device passes the file data of the arithmetic target through the path in accordance with a calculation request from the host device. And an input means for inputting from the secondary storage device, and when a selection projection input command including a selection condition and projection designation is given from the host device, input operation target file data from the secondary storage device. While inputting by the input means, the input means for performing the selection / projection processing according to the selection condition and the projection designation on the same file data. Arithmetic processing means for performing sorting or relational algebraic arithmetic on the calculation target file data or the result of the selection / projection processing by the input means, the calculation target file data or the selection / projection processing result, and the arithmetic processing means And an output means for outputting the calculation result to the secondary storage device, wherein the calculation processing device receives the input according to the selection projection input command from the host device. A data processing device, characterized in that the input of the calculation target file data and the selection / projection processing for the same data are executed in parallel by using the means. 2. A host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device, wherein the operation is performed in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic process on target file data, the arithmetic processing device is configured to communicate with the host device and to communicate with the secondary storage device. Is a first processor for executing data input / output, and when a selection projection input command including a selection condition and projection designation is given from the host device, operation target file data is input from the secondary storage device. A first processor that performs selection / projection processing on the same file data according to the selection condition and projection specification, and an arithmetic circuit that performs sorting or relational algebraic operation A second processor for controlling execution of the operation by the operation circuit, operation target file data input by the first processor or a result of the selection / projection processing by the first processor, and operation by the operation circuit And a third processor for controlling the operation of the first and second processors based on an instruction from the host device supplied via the first processor. When the host computer gives the selective projection input command to the arithmetic processing unit, the third processor performs the same process as the input process of the arithmetic target file data to the first processor. Selection for data
The first processor is instructed to execute the projection processing in parallel, and in response to this instruction, the first processor selects and performs the input processing.
A data processing apparatus, wherein projection processing is executed in parallel, and the selection / projection processing result is stored in the internal memory.