JPH06102290A - Signal waveform display - Google Patents

Abstract

PURPOSE:To obtain a signal waveform display in which contrast of natural brightness can be provided at the superposed part of waveform. CONSTITUTION:An A/D converter 3 outputs digital data of observing signal where sampling frequency is subjected to frequency division of at least two- phase, and the digital data is fed through a data buffer 4 to a memory 5. Data is eventually read out from the memory 5 and a comparator 7 compares previous data with current one. A degree of superposition managing circuit 8 counts the degree of superposition and the resultant data of counting is then stored while being distributed to parts other than the waveform data areas of continuous memory rows, not larger in number than the number of phases subjected to frequency division of the A/D converter 3, with reference to a predetermined address of the memory 5. Waveform data and degree of superposition data are fed from the memory 5 to D/A converters 10, 12 for vertical axis and luminance control thus producing a luminance control signal 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal waveform display device used for observing a physical phenomenon.

[0002]

2. Description of the Related Art Generally, a signal waveform observing device such as an oscilloscope repeatedly displays a waveform on a CRT, but by repeating this at high speed, the portion where the waveforms overlap is brighter than other portions to the human eye. It is visible and allows the observer to naturally identify multiplicity and signal waveforms.

By the way, in recent years, digitization has progressed, and observed waveforms have once been digitized and stored in a memory.

[0004]

However, in the conventional signal waveform observing device using digital data, only one overlapping point in the memory is recognized and the same number of times as other points on the waveform are recognized. Will be displayed. Therefore, the observer cannot obtain the information based on the difference in brightness, resulting in the loss of the amount of observed information that can be identified by the difference in brightness. This state is shown in FIG.

In FIG. 10 (a), the waveforms A, B, and C have points X.
1, X2, X3, and X4 overlap each other. FIG. 10B is an enlarged view of the portion of the point X1. FIG. 11 is a diagram for explaining the increase in the brightness of the superimposed portions X1, X2, X3, and X4 where the same waveform display should be expected. In the overlapping portion X1 of the waveform display lines in FIG. 11B, the brightness should originally be high. With such a small number of waveforms as in this example, it is difficult to understand the adverse effect when there is no brightness difference, but when the waveform density is high, the waveforms cannot be distinguished at all. FIG. 12 shows an example thereof. 12A and 12B show examples of different waveforms contained in one television waveform. Since these two waveforms are usually on the same synchronization signal, the observed waveforms appear to overlap. If there is no difference in the brightness of the overlapped portion, the result is as shown in FIG. 12C, and the chrominance portion cannot be identified at all. In FIG. 12D, a luminance difference is added to this portion, and the existence of two types of signals can be confirmed.

In order to solve the above problem, there is a method of generating brightness information using program software.
However, there is a problem that the processing speed cannot catch up with the observation of high-speed signals.

Further, generally, the average or maximum luminance of a digitized signal waveform display device is fixed, which may hinder observation depending on the type of waveform. To deal with this problem, the conventional measures have relied solely on the method in which the measurer manually adjusts the brightness. However, when the waveform changes frequently, it is difficult to handle it manually.

The present invention solves the above-mentioned conventional problems and displays from a digitized observed signal waveform without increasing the circuit scale and requiring almost no program software. Signal waveform display device capable of providing natural brightness to overlapping portions of waveforms to be observed and separating and recognizing observed waveforms, thus improving reliability, workability by high-speed processing, economical efficiency, etc. In addition to the above purpose,
It is an object of the present invention to provide a signal waveform display device capable of automatically controlling the average level or the maximum value of the brightness of an observed waveform displayed.

[0009]

The technical means of the present invention for achieving the above object is an A / D conversion means for dividing a sampling frequency by at least two phases and outputting digital data of an observation signal. A data buffer that receives data from the A / D conversion means in the number of phases described above, a memory that receives data from the data buffer, a means that reads the data of the corresponding address stored in this memory, and the previous data of this same address. And the current data are compared, and the output of this comparison means is used to count the superposition frequency when the previous data and the current data are the same, and the count result data is divided into the above-mentioned frequency divisions based on a predetermined address in the memory. A means for outputting the data to be distributed and stored in a portion other than the waveform data area of the continuous memory row having the maximum number of phases; It reads over data, in which a means for generating a signal for waveform display commensurate with the superimposition frequency.

Another technical means of the present invention for achieving the above object is an A / D conversion means for dividing a sampling frequency by at least two phases and outputting digital data of an observation signal, and this A / D conversion means. A data buffer that receives data in the above-mentioned number of phases from the conversion means, a memory that receives data from this data buffer, a means that reads the data of the corresponding address stored in this memory, and the previous data and the current data of this same address. The means for comparing and the output of this comparing means are used to count the superposition frequency when the previous data and the present data are the same, and the data of this counting result is used to maximize the frequency division phase number based on the predetermined address of the memory. Means for outputting the data to be distributed and stored in a portion other than the waveform data area of a continuous memory row, the superposition frequency data and the control signal. Means for controlling the output level by, in which a means for generating a signal for the waveform displayed corresponding to the controlled output level.

Yet another technical means of the present invention for achieving the above object is to divide the sampling frequency into at least two phases and output digital data of an observation signal.
D conversion means, a data buffer that receives data from the A / D conversion means in the number of phases described above, a memory that receives data from the data buffer, a means that reads data at the corresponding address stored in the memory, A means for comparing the previous data and the current data at the same address, and the output of this comparison means is used to count the superposition frequency when the previous data and the current data are the same, and the data of this counting result is used as a reference for the predetermined address of the memory. Means for outputting to store in a portion other than the waveform data area of the continuous memory row having the maximum number of frequency division phases, the means for detecting the maximum value of the superimposition frequency, and the superimposing means. A means for controlling the output level by a control signal using the frequency data and the output data of the maximum value detecting means, and corresponding to the controlled output level It is obtained by a means for generating a signal for display type.

[0012]

Therefore, according to the present invention, since the superposition frequency of the waveform is measured and the electric signal corresponding to the superposition frequency is generated, it is possible to add the luminance difference of the waveform overlapping portion to the digitized signal waveform image. It will be possible. Further, the A / D conversion means outputs the digital data of the observation signal obtained by dividing the sampling frequency by at least two phases, inputs the digital data to the memory via the data buffer, reads the corresponding address data stored in the memory, and outputs the same. The previous data of the address and the present data are compared by the comparison means, and the superposition frequency counting means counts the superposition frequency when the previous data and the present data are the same with the output of the comparison means, and the data of this counting result is stored in the memory. Since the memory is distributed and stored in a portion other than the waveform data area of the continuous memory row having the maximum number of frequency division phases based on the predetermined address, it can be operated at high speed without increasing the memory scale. be able to.

Further, by generating a signal for waveform display corresponding to the output level controlled by the superposition frequency data and the control signal, it is possible to control the average level or maximum value of the luminance of the displayed waveform. it can.

[0014]

【Example】

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing a signal waveform display device in a first embodiment of the present invention.

As shown in FIG. 1, the observed signal is supplied from the input terminal 1 to the observed signal amplifier circuit 2. The observation signal amplification circuit 2 supplies its output to the A / D conversion circuit 3. A / D
The digital output obtained by the conversion circuit 3 is sent to the data buffer 4. The data buffer 4 supplies its output to the memory 5 and the superimposition detection comparator 7. The read output of the memory 5 is the waveform read buffer 6 and the display data buffer 9
Is supplied to. The superimposition detecting comparator 7 obtains the comparison data from the waveform read buffer 6 and determines whether this data matches the information in the data buffer 4, and sends the determination output to the superposition degree management circuit 8. The superposition degree management circuit 8 obtains previous superposition degree data from the waveform reading buffer 6 and generates a superposition degree data update value. This superimposition degree update value data is supplied to the data buffer 4 and stored in the memory 5 when these processes are completed. Display data buffer 9
Is the waveform data supplied from the memory 5 for vertical axis D /
The weight data supplied from the memory 5 is supplied to the A converter 10 and the D / A converter 12 for brightness control. The vertical axis D / A converter 10 converts the waveform data into a CRT.
And the like are converted into a vertical axis signal waveform display signal 11 for display. The brightness control D / A converter 12 converts the superimposition degree data into a brightness control signal 13 for displaying on a CRT or the like and supplies the signal to the brightness control circuit 14. The order of these is CP
The memory address counter 16 controlled by the control circuit 15 including U, supplies its output to the memory 5, the horizontal axis display data buffer 17 and the like. The horizontal axis D / A converter 18 generates a horizontal axis signal 19 from the output of the horizontal axis display data buffer 17. The observation signal amplifying circuit 2 supplies a part of the output to the synchronizing circuit 20, the synchronizing circuit 20 transmits the synchronizing signal output to the memory address counter 16, and manages the position of the signal waveform data stored in the memory 5.

FIG. 2 shows a concrete example of the superposition degree management circuit 8 and the like in FIG. 1, and FIG. 3 shows a display data buffer 9 and a brightness control D / A when the superposition degree management circuit 8 shown in FIG. 2 is used.
A specific example of the converter 12 will be shown.

In FIG. 2, the observation signal that has entered the A / D conversion circuit 3 through the observation signal amplification circuit 2 is converted into a two-phase digital output, and two data buffers 41 and 42 are provided.
Is supplied to. Now, 41 is an odd address output ADC data buffer, and 42 is an even address output ADC
For data buffer. The output terminals of the data buffers 41 and 42 are connected to the waveform memories 51 and 52 and the superposition detection comparators 71 and 72, respectively. 51 is an odd address side waveform memory, and 52 is an even address side waveform memory. Reference numeral 71 is an odd address side superimposition detection comparator, and 72 is an even address side superposition detection comparator. The read outputs of the waveform memories 51 and 52 are connected to the waveform read buffers 61 and 62, and are also connected to the display data buffer 9 by the bus line 55.
61 is the odd address side waveform read buffer, and 62
Is the even-address-side waveform read buffer. The outputs of the waveform read buffers 61 and 62 are connected to the superimposition detection comparators 71 and 72, and the superposition degree management circuit 8
Connected to the superimposition degree progressive adder 81. The outputs of the superposition detection comparators 71 and 72 become superposition detection outputs through the AND circuit 73, and are connected to the progressive input terminal of the superposition degree progressive adder 81. The output of the superposition degree progressive adder 81 is connected to the superposition degree data input section of the data buffers 41 and 42 via the data latch circuit 82. Reference numeral 85 is a circuit for detecting the maximum value of the superposition frequency, which is used when automatically controlling the maximum brightness level. 56 is the data output line.

In FIG. 3, the display data buffer 9 for obtaining the waveform data from the waveform memories 51 and 52 by the bus line 55 comprises a display data register main body 90 and output buffers 91 and 92 thereof. The vertical axis data part is transmitted from the buffers 91 and 92 to the vertical axis D / A converter 10 through the data bus 98, and the superimposition degree data is supplied to the brightness control D / A converter 12. Reference numeral 91 is an odd address side data output buffer, and 92 is an even address side data output buffer.

1 waveform (1 screen) acquisition time is 1 acquisition
Assuming that the number of waveform extraction points per time is 1,000, it becomes 10 ns x 1 k = 10 µs at a sample rate of 100 MS / s.
The maximum number of overlapping waveforms is 10ms ÷ (10n
s × 1000) = 1000, which requires a frequency memory of about 10 bits. However, a memory that operates in real time and at high speed is not only costly, but also consumes a large amount of power. In addition, the frequency of overlapping of waveforms may be close to zero depending on the signal, and it can be said that it is meaningless to provide a 10-bit frequency memory over all display points. On the other hand, in order to manage the waveform superimposition frequency, it is not impossible to convert 10-bit data into 3 bits, considering that there is generally no case where the luminance difference between the waveforms is required to be so strict. Since the purpose of the present invention is to realize high-speed performance by real-time operation, the frequency must be established on the basis of the update number of one. Therefore, it cannot be solved by the method of rounding up the precision.
That is, the update unit of the count is 1, and a method capable of handling the largest possible number is required.

Now, let's consider using the remaining portions of the waveform memories 51 and 52. Consider a case where the memory width is 16 bits as a standard memory structure. If the waveform data is stored in 10 bits using this memory, the remaining portion is 6 bits. If 3 bits are allotted for the additional information of the waveform, the memory width that can be used for the waveform superposition frequency management is 3 bits. With 3 bits, the maximum superposition degree is 1,000, but the capacity is almost unmanageable. Therefore, restrictions are imposed on both sides as follows.

FIG. 4 shows the human sense intensity and the magnitude of the physical stimulus that gives it. In FIG.
A1, A2, A3, A4, and A5 indicate that the distance has an exponentially increased state. The human senses corresponding to the respective physical intensities A1 to A5 increase almost linearly. That is, the human sense responds logarithmically to the stimulus intensity. For example, the intensity with respect to the volume of hearing can be expressed in logarithm. Similarly, the visual sense also logarithmically responds to the amount of light received. From this,
Even if the information having the physical strength A4 or higher in FIG. 4 is cut off to be in the state of the thick broken line in the figure, the human identification area is narrowed by only 20%. That is, since the region width of 1 to 10 and the region width of 10,000 to 100,000 are treated as the same difference for human beings, if the region having the larger physical significance is the region of 1 to 10, 1,000 ~
It may be worthwhile to sacrifice 100,000 areas. In the present invention, this interpretation is exactly applied.

Next, the visual resolution of luminance will be described with reference to FIG. FIG. 5A shows a superposed portion X2 of the two waveforms A and B in FIG. 11, and FIG. 5B shows a state in which this is displayed by the bright spot of the CRT. The diameter of the bright spot Y in FIG. 5B is usually about 0.2 mm. In contrast,
The interval between the bright spots Y is at least 0 in the case of displaying 1,000 points as described above.
It is 1 millimeter. That is, the bright spot Y almost overlaps with the adjacent bright spot Y by almost half. Further, when the brightness is increased, the bright point Y causes halation Z and the diameter further increases. Therefore, the bright point Y adjacent to the intersection of the waveform A and the waveform B in FIG. 5B is covered by the bright point of the intersection. Will end up. Therefore, the brightness of the bright points Y adjacent to the intersections is increased as a result, so that the resolution in the brightness information is not maintained up to the level of each bright point.

For the above reasons, in the embodiment of the present invention,
A memory for the luminance, that is, the waveform superposition frequency was constructed by the method shown in FIG. 2 of the embodiment of the present invention with reference to FIG.
The method of using the waveform memories 51 and 52 in FIG. FIG. 6 shows times t-6, t-5, t- in the memory.
4, t-3, t-2, t-1, t0, t + 1, t + 2,
It is waveform data corresponding to t + 3 and t + 4, and is shown to be composed of a waveform amplitude data area of 10 bits, a luminance data area of 3 bits, and an attached data area of 3 bits, for a total of 16 bits. Here, regarding the waveform data, time t-6, t-5, t-4, t-.
3, t-2, t-1, t0, t + 1, t + 2, t + 3,
Enter an independent value corresponding to t + 4. On the other hand, for the waveform superimposition frequency data, adjacent memories are used, and one memory stores the waveform superimposition frequency data. With this method, the data width for the waveform superposition frequency is 3
Bit plus 3 bits, 6 if used in cascade
Bit data, that is, up to 64 decimal can be counted. This is the originally required maximum frequency of 1.0
It is 15.6 times smaller than the data width that covers 00, but it can be narrowed down to a range that can be called approximately one digit in decimal. Of course, if the waveform superposition frequency data area per waveform data can be set to a 4-bit width, it becomes 8 bits, that is, 256, which is 4 for the maximum frequency of 1,000.
You can approach up to one-third.

FIG. 6 will be described in more detail. Since the waveform superposition frequency data constitutes one data item with two points, a combination without deviation is required. In FIG. 6, the times t0 and t + 1 are combined as one set, but the times t0 and t + 1 are actually combined, but the time t0 must actually be a specific signal.

Returning to FIG. 2, a specific circuit will be described. The observation signal output from the amplifier circuit 2 is converted into digital information by the A / D conversion circuit 3, but the output of a high-speed A / D conversion circuit is generally in two phases. This is because consideration is given to the fact that the subsequent circuit that receives the output does not have to operate at high speed. In FIG. 2 as well, the A / D conversion circuit 3 adopts a two-phase output method, and the output appears alternately in the ADC data buffers 41 and 42. According to the above example, if the sampling frequency is 100 MS / s, the output frequency will be 50 MHz. This 50MHz is the buffer 41
And 42 are 180 degrees out of phase. Therefore, if one output (here, the buffer 41 side) is set as a reference, it is possible to specify the odd number side in the addresses of the waveform memories 51 and 52. Here, since the lower 3 bits of the buffers 41 and 42 are allotted to the superposition frequency data, the lower 3 bits of the buffer 41 are the upper 3 bits of the superposition frequency data, and the lower 3 bits of the buffer 42 are the lower 3 bits of the superposition frequency data. It can be a bit. FIG. 2 is set in this state. Therefore, times t0 and t + 1 in FIG. 6 correspond to odd addresses and even addresses, respectively. Even in the waveform memories 51 and 52, the upper 3 bits of the superposition frequency data are stored in the odd address side waveform memory 51, and the lower 3 bits of the superposition frequency data are stored in the even address waveform memory 52. Further, in the waveform read buffers 61 and 62 as well, the upper 3 bits of the superposition frequency data are output to the odd address side waveform read buffer 61 and the even address side waveform read buffer 62.
The lower 3 bits of the superposition frequency data are output to.

Next, the operation of the circuit shown in FIG. 2 will be described. The A / D conversion circuit 3 receiving the supply of the observation signal from the observation signal amplification circuit 2 samples the observation signal at the time t0 by the sampling clock CLK, and then digitally outputs to the ADC data buffer 41 of odd address output. Output the data. The next cycle of the sampling clock CLK is generated at time t + 1 and A
The / D conversion circuit 3 is caused to sample the observation signal, but since the sampling clock is divided into a frequency of ½ inside the A / D conversion circuit 3, the time t +
The digital data generated at 1 is A for even address output.
It is supplied to the DC data buffer 42. These two digital data are output to the superposition detection comparators 71 and 72. At the same time, the previous sampling data corresponding to the respective addresses from the odd-numbered address side waveform memory 51 and the even-numbered address side waveform memory 52 is the odd-numbered address side. It is output to the superimposition detection comparators 71 and 72 through the waveform read buffer 61 and the even address side waveform read buffer 62. The superposition detection comparators 71 and 72 are logic comparison circuits having an exclusive OR circuit as a core, and the superposition detection output AND circuit 73 is used only when the previous value and the current value of the waveform data match. Generates high potential level output.
Now, assuming that the previous value and the current value match, the high potential level output of the AND circuit 73 for superimposition detection output is added to the progressive input of the superposition degree progressive adder 81, and the waveform read buffer 6
The lower 3 bits of 1 and 62 are obtained, and the previous superposition frequency data, which is 6-bit data, is updated by one. The superposition degree progressive adder 81 is a full adder (Ful) having 6-bit input and 1-bit input.
l Adder) circuit. The superposition frequency data updated in this way is passed through the data latch circuit 82 to A
It is supplied to the lower 3 bits of the DC data buffers 41 and 42, and the waveform memories 51 and 52 together with the current waveform data value.
Rewrite the contents of. In the waveform data read cycle, both the waveform data and the superposition frequency data are simultaneously sent through the bus line 55 to the display data buffer 9 (see FIG. 1,
(See FIG. 3). The superimposition frequency maximum value detection circuit 85 constantly monitors the superimposition frequency and detects the maximum value.

Although operation timing control signals other than the sampling clock signal are not shown in FIG. 2, the timing control signals according to the above-described sequence are generated by the control circuit 15 including the CPU of FIG. 1 and the memory address counter 16. Has occurred and is being supplied.

Next, the operation of the entire apparatus according to the embodiment of the present invention, which has a circuit as the core, will be described with reference to FIG. 1 in which the intended function is realized in this way.

The memory address counter 16 of FIG. 1 is supplied with a synchronization pulse indicating a synchronization time by the synchronization circuit 20 which has obtained the synchronization signal from the observation signal amplification circuit 2. The memory address counter 16 which receives the synchronizing pulse generates waveform data and a timing signal for determining an address position inside the memory, and controls the address of the memory 5. The display data buffer 9 supplies the waveform data portion to the vertical axis D / A converter 10 and converts it into a vertical axis signal waveform display signal 11 which is one of the signals for displaying the waveform on the CRT or the like.
Further, the display data buffer 9 supplies the superimposition frequency data portion to the brightness control D / A converter 12 and converts it into a brightness control signal 13 corresponding to the superimposition frequency. The address control signal from the memory address counter 16 is also supplied to the horizontal axis display data buffer 17, and is converted into a horizontal axis signal 19 by the horizontal axis D / A converter 18 as horizontal position information.

A vertical axis signal waveform display signal 11 will be described with reference to FIG.
A specific example of the output unit of the brightness control signal 13 will be described. The brightness control D / A converter 12 converts the waveform data obtained from the memory 5 into a brightness control signal 13 corresponding to the waveform superposition frequency through the display data buffer 9. That is, inside the display data buffer 9, the output extracted from the display data register body 90 is divided into odd and even addresses, and the odd address side superposition frequency data output buffer 91 and the even address side superposition frequency data output buffer are output. To 92. The lower 3 bits of the odd number address side superposition frequency data output buffer 91 output the upper 3 bits of the superposition frequency data, and the lower 3 bits of the even address side superposition frequency data output buffer 92 output the lower 3 bits of the superposition frequency data. Therefore, the superposition frequency data configured as 6 bits in total is restored here. This 6-bit data is a brightness control D / A
It is converted into an analog signal by the converter 12. 3D
The / A converter 12 is shown by a simple equivalent circuit.
The 6-bit superposition frequency data is connected to six exponentially weighted resistors R1, R2, R3, R4, R5, R6, respectively. Generally, the resistance is R1 = R2 × 2 = R3 × 4
= R4 × 8 = R5 × 16 = R6 × 32 Therefore, the higher the bit, the larger the current flowing through the resistor and the greater the influence on the output. In this way, an electric signal corresponding to the superimposition degree is generated and used as the brightness control signal 13.

The waveform data portions of the odd number address side superimposition frequency data output buffer 91 and the even address side superimposition frequency data output buffer 92 shown in FIG. 3 are data indicating the amplitude and voltage of the waveform and are supplied to the vertical axis D through the data bus 98. /
It is transmitted to the A converter 10.

As described above, according to the present embodiment, the excess portions of the wavemeter memories 51 and 52 can be used to count and store the overlap of the waveforms, and based on the data, the overlap of the waveforms can be displayed. The brightness can be controlled according to the degree.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

7 to 9 show a signal waveform display device according to a second embodiment of the present invention, and FIG. 7 is a block diagram showing a concrete example of a display data buffer and a brightness control D / A converter. 8 is a configuration diagram showing a specific example of the luminance stabilizing circuit, and FIG.
FIG. 3 is a configuration diagram showing a specific example of a maximum value detection circuit.

In this embodiment, a structure different from that of the first embodiment will be described. In FIG. 7, a display data buffer 9 for obtaining waveform data from the waveform memories 51 and 52 (see FIG. 2) by a bus line 55 includes a display data register main body 90 and an output buffer 91 thereof.
92, a data offset circuit 93 for controlling the maximum brightness depending on the superposition degree of the waveform or the observer's intention, and the output subjected to the offset processing to the brightness control D / A converter 12
And a buffer register 94 for supplying to the. The vertical axis data portion from the output buffers 91 and 92 is transmitted to the vertical axis D / A converter 10 through the data bus 98. Reference numeral 91 is an odd address side superposition frequency data output buffer, and 92 is an even address side superposition frequency data output buffer. Reference numerals 95 and 96 are offset inputs for controlling the offset amount. In the example of FIG.
The control lines are 2 bits to allow a 3 bit offset. Reference numeral 95 is a lower bit control input, and 96 is an upper bit control input. 97 is a buffer register 94
It is a control line for updating the contents of.

The D / A converter 12 has an 8-bit input structure, and FIG. 7 shows this by a simple equivalent circuit. Now, the 6-bit superposition frequency data is six exponentially weighted resistors R1, R2, R3, R4, R5, R.
6 connected to 6 and resistors R3, R4, R5,
Consider a case where six R6, R7, and R8 are connected.

Generally, the resistance is R1 = R2 × 2 = R3 × 4
= R4 × 8 = R5 × 16 = R6 × 32 = R7 × 64 = R
It is set as 8 × 128. Therefore, the higher the bit, the larger the current flowing through the resistor and the greater the influence on the output. That is, the resistors R1, R2, R3, R4, R
When connected to 6 of 5, R6 and resistors R3, R4,
6 when connected to 6 of R5, R6, R7, R8
The influence of bits is R6: R8, that is, a difference of 1: 4. Moreover, because it leads to the difference in the level itself,
The result is an offset condition. Figure 7
In this example, the offset can be selected in three ways. Therefore, if this offset is controlled by another signal, the maximum brightness or the minimum brightness can always be automatically kept constant.

In FIG. 7, the amount of offset is represented by control lines 95 and 9
It can be adjusted with 2 bits of 6. According to the 2-bit value, 6 bits from the odd address side data output buffer 91 and the even address side data output buffer 92 are connected to six resistors R1, R2, R3, R4, R5 and R6. , Resistors R2, R3, R4, R5, R
When connected to 6 of R6, R7, and R3, R4, R
5, R6, R7, and R8 can be connected. A case in which the output 56 of the superimposition frequency maximum value detection circuit 85 is connected to the offset amount control lines 95 and 96 of FIG. 7 via the brightness stabilization circuit 86 shown in FIG. 8 will be described. Now, the outputs 101 and 102 of FIG. 8 are changed in state by dividing the 6-bit output of the superposition frequency maximum value detection circuit 85 into the following four stages. First, the outputs Q1, Q2, Q3, Q4, Q5 and Q6 of the superposition frequency maximum value detection circuit 85 are all L.
In the case of the level, both the output lines 101 and 102 become the L level. That is, "00" is indicated. When either one of the outputs Q1 and Q2 of the superposition frequency maximum value detection circuit 85 reaches the H level, the output line 101 becomes the H level.
That is, "01" is indicated. Next, when one of the outputs Q3 and Q4 of the superposition frequency maximum value detection circuit 85 reaches the H level, the output line 102 becomes the H level. That is, "10" is indicated. Finally, the superposition frequency maximum value detection circuit 8
When either of the outputs Q5 and Q6 of No. 5 reaches the H level, the output lines 101 and 102 become the H level. That is, "11" is indicated. Therefore, the output lines 101, 102
Connect to control inputs 95 and 96 respectively,
The larger the maximum value of the superposition frequency, the higher the average brightness.
Conversely, connecting output line 101 to control input 96 and output line 102 to control input 95 stabilizes maximum brightness.

FIG. 9 shows a specific example of the superimposition degree maximum value detection circuit 85. The current value data 121 obtained from the data latch circuit 82 is converted into the exclusive OR circuit 122 as shown in FIG.
To enter. On the other hand, the output of the flip-flop circuit 123 holding the maximum value of the superimposition degree is used as another input of the exclusive OR circuit 122 via the buffer register 124.
If the two inputs are different, the maximum value at that time must be H, so the exclusive OR circuit 12
The CLEAR terminal of the flip-flop circuit 123 is set to the H level and the output is set to the H level by using the output of H level 2. If the two inputs are the same, the maximum value at that time must be the same as the input. Therefore, the input level is supplied to the D terminal so that the output becomes the same as the input level when the clock arrives. . At this time, the output of the flip-flop circuit 123 should be at the same level as that of the two inputs even if it is not controlled by the clock, but the reason for constantly rewriting the data is to facilitate the initial setting when the power is turned on. This is because the data error due to the mixing of noise is corrected in a short time. In this way, an electric signal corresponding to the superimposition degree is generated and used as the brightness control signal 13.

The waveform data portions of the odd address side superimposition frequency data output buffer 91 and the even address side superimposition frequency data output buffer 92 shown in FIG. 7 are data indicating the amplitude and voltage of the waveform and are used for vertical axis D through the data bus 98. /
It is transmitted to the A converter 10.

As described above, according to the present embodiment, it is possible to count and store the overlap of the waveforms by utilizing the surplus portion of the waveform memory, and based on the data, the degree of the overlap of the waveforms can be displayed. It is clear that the brightness can be controlled by It is also clear that a natural brightness difference can be given to the overlapping portion of the waveforms displayed on the display device, and the average level or maximum value of the brightness can be automatically controlled. It has also been shown that these circuits execute during this processing operation without software intervention and are therefore capable of high-speed signal observation.

In the above embodiment, the A / D converter 3 is replaced by 2
It was explained that the output is performed with a frequency division of 1/3, but it is 1/3.
It is obvious that it is also possible to divide the frequency by 1/4, without needing to show it in the drawings, and therefore the description thereof is omitted. In addition, the superposition frequency data can be distributed to the four memory columns by the frequency division of 1/4, but since the luminance resolution is reduced by that much, the A of 1/4
Even in the / D converter, the superposition frequency data may be distributed only to two memory columns. This is also apparent without needing to be shown in the figure, and will be omitted. The present invention is
Various design changes can be made without departing from the basic technical idea.

[0044]

As described above, according to the present invention, the superposition frequency of waveforms is measured and an electric signal corresponding to the superposition frequency is generated, so that the luminance difference of the waveform overlapping portion is digitized in the digitized signal waveform image. Can be added. As a result, the lack of the luminance information in the overlapping portions of the waveform, which is a major drawback of the conventional waveform display device, can be solved, and the overlapping waveforms can be separately recognized. Also, the A / D conversion means outputs the digital data of the observation signal obtained by dividing the sampling frequency by at least two phases, inputs the digital data to the memory via the data buffer, and reads the previous data and the present data of the same address read from the memory. The comparison means compares, and the superposition degree counting means counts the superposition degree in the case where the previous data and the present data are the same with the output of the comparison means. Since the memory is distributed and stored in a portion other than the waveform data area of the continuous memory row having the maximum number of cycles, it is suitable for high-speed operation without increasing the scale of the memory circuit. Excellent economy, requiring almost no control program software,
It is a reliable product.

Further, by generating a signal for waveform display corresponding to the output level controlled by the superposition frequency data and the control signal, the average level or maximum value of the brightness of the displayed waveform is automatically controlled. can do.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a signal waveform display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a superposition degree management circuit of the signal waveform display device.

FIG. 3 is a configuration diagram showing a specific example of a display data buffer and a brightness control D / A converter of the signal waveform display device.

FIG. 4 is an explanatory diagram showing a relationship between human sense intensity and physical intensity.

FIG. 5A is an explanatory diagram of a superimposed portion of a signal waveform, and FIG. 5B is an explanatory diagram of halation of a bright spot and a superimposed portion of the signal waveform.

FIG. 6 is an explanatory diagram of a waveform memory used in an embodiment of the present invention.

FIG. 7 is a configuration diagram showing a specific example of a display data buffer and a brightness control D / A converter of a signal waveform display device according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram showing a specific example of a brightness stabilizing circuit of the signal waveform display device.

FIG. 9 is a configuration diagram showing a specific example of a maximum value detection circuit of the signal waveform display device.

10A is an explanatory diagram of a signal waveform, and FIG. 10B is an explanatory diagram of a superimposed portion of the signal waveform.

FIG. 11A is an explanatory diagram of a brightness increase of a superposed portion where waveform display is expected, and FIG. 11B is an explanatory view showing an overlapping portion of waveform display lines where the brightness should be high.

12A and 12B show examples of different waveforms contained in one television waveform, respectively. FIG. 12C shows chrominance portion identification when there is no difference in luminance of the superposed portion. Explanatory diagram showing that it can not be done at all (d) is an explanatory diagram in which the brightness difference is added to the overlapping part

[Explanation of symbols]

 3 A / D conversion circuit 4 Data buffer 5 Memory 6 Read buffer 7 Superimposition detection comparator 8 Superposition degree management circuit 9 Display data buffer 10 Vertical axis D / A converter 11 Vertical axis signal waveform display signal 12 Brightness control D / A converter 13 Luminance control signal 17 Horizontal axis display data buffer 18 Horizontal axis D / A converter 19 Horizontal axis signal 41 Odd address output ADC data buffer 42 Even address output ADC data buffer 51 Odd Address side waveform memory 52 Even address side waveform memory 61 Odd address side waveform read buffer 62 Even address side waveform read buffer 71 Odd address side superimposition detection comparator 72 72 Even address side superposition detection comparator 73 Superposition detection output AND circuit 81 Superposition degree progressive adder 82 Data latch Circuit 85 Superimposition frequency maximum value detection circuit 90 Display data register main body 91 Odd address side superposition frequency data output buffer 92 Even address side superposition frequency data output buffer 93 Offset circuit 95 Control input 96 Control input

Claims (3)

[Claims] 1. An A / D that divides a sampling frequency into at least two phases and outputs digital data of an observation signal.
The conversion means, the data buffer that receives data from the A / D conversion means in the number of phases described above, the memory that receives the data from the data buffer, and the means that reads the data of the corresponding address stored in the memory A means for comparing the previous data of the address and the present data, and the output of this comparing means, the superposition frequency when the previous data and the present data are the same is counted, and the data of this counting result is used as a reference for the predetermined address of the memory. Means for outputting the data for distribution and storage in a portion other than the waveform data area of the continuous memory row having the maximum number of frequency division phases and the waveform display corresponding to the superposition frequency Waveform display device having means for generating a signal for. 2. An A / D that divides a sampling frequency into at least two phases and outputs digital data of an observation signal.
The conversion means, the data buffer that receives data from the A / D conversion means in the number of phases described above, the memory that receives the data from the data buffer, and the means that reads the data of the corresponding address stored in the memory A means for comparing the previous data of the address and the present data, and the output of this comparing means, the superposition frequency when the previous data and the present data are the same is counted, and the data of this counting result is used as a reference for the predetermined address of the memory. Means for distributing and storing the data in a portion other than the waveform data area of the continuous memory column having the maximum number of frequency division phases, and means for controlling the output level by the superposition frequency data and the control signal , A signal waveform display device having means for generating a signal for waveform display corresponding to the controlled output level. 3. An A / D that divides a sampling frequency into at least two phases and outputs digital data of an observation signal.
The conversion means, the data buffer that receives data from the A / D conversion means in the number of phases described above, the memory that receives the data from the data buffer, and the means that reads the data of the corresponding address stored in the memory A means for comparing the previous data of the address and the present data, and the output of this comparing means, the superposition frequency when the previous data and the present data are the same is counted, and the data of this counting result is used as a reference for the predetermined address of the memory. Means for distributing and storing in a portion other than the waveform data area of the continuous memory row having the maximum number of frequency division phases, means for detecting the maximum value of the superposition frequency, and the superposition frequency A means for controlling the output level by a control signal using the data and the output data of the maximum value detecting means, and a wave corresponding to the controlled output level. Signal waveform display device and means for generating a signal for display.