JP2628590B2 - Scan line position detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting the position of a scanning line when displaying a screen of a raster display device such as a CRT.

2. Description of the Related Art When displaying an image created by a computer as an animation in real time on a screen such as a CRT,
Usually, a video memory for storing image data is prepared for two screens, and while the image data in one video memory is read and displayed on the screen, the image data of the next screen is written to the other video memory. Is displayed in the following procedure.
Thereby, a real-time animation without flicker can be displayed.

Problems to be Solved by the Invention In the above conventional method, a video memory having a capacity twice as large as the amount of image data displayed on the screen is required. This leads to an increase in cost, or conversely, if the memory capacity is limited, there is a problem that the resolution of the image must be reduced to half.

On the other hand, if image data can be written to the video memory and screen output can be performed from the same, the video memory only needs to be for one screen. However, in this case, if the contents of the video memory are rewritten irrespective of the screen output, for example, the nth raster (scanning line) is output as the image data before rewriting, and the (n + 1) th raster is the image data after rewriting. And a discontinuous line may occur. This is visually perceived as flickering by the human eye, making the animation difficult to see.

An object of the present invention is to solve such a problem and to provide a device capable of knowing a display position on a raster display device in order to control operations related to screen output in synchronization with screen output.

Means for Solving the Problems In order to achieve the above object, according to the present invention, in a scanning line position detecting device of a display device performing raster-type scanning, a counting device for counting the number of horizontal synchronization signals after initialization; Total number holding means for holding data representing the number of horizontal synchronization signals in a period; first comparing means for comparing the output of the counting means with the output of the total number holding means; and the output of the counting means being the total number holding means. Reset means for initializing the counting means when the output exceeds the number of outputs, display width number holding means for holding data representing the number of horizontal synchronization signals in the display period, output of the counting means and output of the display width number holding means. A second comparing means for comparing the output of the counting means, a subtracting means for subtracting an output of the total number holding means from an output of the counting means, and an output of the counting means being smaller than an output of the display width number holding means. Selecting means for selecting the output of the counting means at the time, and selecting and outputting the output of the subtracting means otherwise.

Operation The counting means starts counting from the time when one vertical period of raster scanning starts, and continuously outputs the number of horizontal scanning lines at each time during the one vertical period. Therefore, the current scanning position can be known by using the output of the counting means. Further, the selection means sets the counter value (which is always a positive value) when the raster scanning is performed during the display period, and sets the counter value during the retrace period (when the raster scanning is not performed) to [-( (Total number-counter value)]. The value output during the latter retrace period is always negative, and (total number-counter value)
Represents the number of horizontal periods until the start of the next vertical period.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a system configuration diagram of a computer system that performs image output. The CPU 30 writes image data to be output on the screen to the video memory 34 via the system bus.
Thereafter, the CRT controller (CRTC) 32 controls the image output, outputs the data in the video memory 34 to the output unit 36 at an appropriate timing, and sends the horizontal and vertical synchronization signals to the CRT display device 38. Output unit 36 is video memory
The image data sent from 34 is converted into an analog image signal that can be input to the CRT display 38.

The CRTC 32 includes a circuit for generating horizontal and vertical synchronization signals. FIG. 3 shows a configuration of a circuit for generating a vertical synchronization signal and a display signal. The counter 40 inputs a horizontal synchronizing signal generated by a horizontal synchronizing signal generation circuit (not shown) as a clock pulse SCLK, and counts up the result of increasing the number of the pulses to the four comparators 43, 45, 47,. Four
Output to 9. The other inputs of the comparators 43, 45, 47, and 49 are data provided from a total register 42, a display width register 44, a synchronization start register 46, and a synchronization end register 48, respectively.

The outputs of the comparators 43 and 45 connected to the total register 42 and the display width register 44 are input to the first RS flip-flop 50, and the synchronization start register 46 and the synchronization end register
The outputs of the comparators 47 and 49 connected to 48 become the input of the second RS flip-flop 52.

Note that the output of the comparator 43 connected to the total register 42 is input to the reset terminal CL of the counter 40. Therefore, the counter 40 stores the value c of the counter in the total register 42.
Is reset when the data becomes equal to the data M stored in the memory, and the counting is started again from 0.

The total register 42 stores count data M corresponding to the length of one vertical period. Display width register 44
Stores count data N corresponding to a period of screen display (one field) within one vertical period (of course, N <M). The synchronization start register 46 stores count data S corresponding to the length from the display start time to the rise of the vertical synchronization signal (here, N <S <M). The synchronization end register 48 stores count data E corresponding to the length from the display start point to the end point of the vertical synchronization signal (N <S <E).
<M).

The vertical synchronizing signal generation circuit of FIG. 3 having the above configuration generates a display signal and a vertical synchronizing signal by the following operation. After the counter 40 is reset as described above, when the counter value c reaches the value N stored in the display width register, the output of the second comparator 45 becomes high level and the first RS flip-flop 50 The output is inverted.
The output of the first RS flip-flop 50 is the counter value c
Is inverted when it becomes equal to the value M stored in the total register, and returns to the original state. Therefore, as shown in the upper part of FIG. 4, the output of the first RS flip-flop 50 goes high only during the screen display period, and thereafter repeats the cycle of going low until it reaches one vertical period. That is, the output of the first RS flip-flop 50 is a display signal related to vertical scanning. The period after the display period is a retrace period.

When the counter value c reaches the value S stored in the synchronization start register, the output of the third comparator 47 goes high, and the output of the second RS flip-flop 52 is inverted. No. 2
The output of the RS flip-flop 52 is inverted when the value c of the counter next becomes equal to the value E stored in the synchronization end register, and returns to the original state. Therefore, the output of the second RS flip-flop 52 is a pulse signal that is at a high level only for a predetermined period (between S and E) within the retrace period, as shown in the lower part of FIG. That is, the output of the second RS flip-flop 52 is a vertical synchronization signal.

The horizontal synchronization signal generation circuit has substantially the same configuration as the above-described vertical synchronization signal generation circuit except that the clock pulse SCLK input to the counter is a video clock, and performs the same operation.

In the image display system according to the present embodiment, as described below, it is possible to obtain data on the position of the scanning line currently being scanned. This is performed by the scanning position detection circuit shown in FIG. In this embodiment, the scanning position detection circuit of FIG. 1 is included in the CRTC 32 of FIG. 2 together with the vertical synchronization signal generation circuit shown in FIG. 3, and the counter 40, display width register 44, Total register 42
Use In addition to these, the scanning position detecting circuit compares the value c of the counter 40 with the data N stored in the display width register 44, the value c of the counter 40 and the value stored in the total register 42. A subtracter 22 for calculating a difference (c−M) from M and a subtractor based on the comparison result of the comparator 20
A selector 24 for selecting one of the output of the counter 22 and the output of the counter 40, and a data register 26 for holding the output of the selector 24 are provided.

The main scanning position detection circuit operates as follows. Comparator 20
Supplies a low level signal to the terminal S of the selector 24 when the value c of the counter 40 is equal to or less than the value N stored in the display width register (c ≦ N). Terminal c if c> N
To a high level signal. The selector 24 outputs the value c of the counter 40 input to the terminal B from the terminal Y while the terminal S is at the low level. While the terminal S is at the high level, the value (c−M) from the subtractor 22 input to the terminal A is output from the terminal Y. Accordingly, the value c of the counter is written into the data register 26 receiving the signal from the selector 24 during the vertical display period, and the value (c−M) is entered during the retrace period.
Is written. FIG. 5 shows the relationship among the display signal, the counter value c, the output of the comparator 20, and the value of the data register 26 at this time.

Here, since the counter 40 is reset when the value c reaches the total value M and returns to 0, (c−M)
Is always a negative value. Accordingly, by reading the value of the data register 26, the CPU 30 can know the current position of the scanning line on the CRT display 38. That is, if the value of the data register 26 is positive, the value indicates the current scanning position (the number from the top) on the screen, and if the value is negative, the display is currently displayed during the flyback period. Indicates that there is a time of [− (c−M)] in the horizontal period before the display of the next screen starts.

By using the scanning position detection circuit of this embodiment, 1
Just preparing a video memory for the screen enables real-time animation output without flicker. That is, the CPU 30 of FIG. 2 outputs the image data to the video memory 34 while reading the value of the data register 26, so that when the CRT 32 outputs the image data to the output unit 36, 3) The disadvantage of rewriting data can be prevented.

Although a CRT display is used as a display device in the above embodiment, this is an example of a raster display device, and the present invention is also applicable to a case where a liquid crystal display device, a plasma display device, or the like is used. Of course you can.

Further, in the above embodiment, as shown in FIG. 1, individual circuits such as a comparator, a subtractor, and a selector are used. However, instead of using these, the same operation can be performed by the CPU 30 by software. For example, the same function as described above can be realized by causing the CPU 30 to repeatedly execute a subroutine as shown in the flowchart of FIG. Briefly explaining the flowchart of FIG. 6, first, the value of the counter 40 is read (step # 10), and it is checked whether the value c is equal to or less than the data N indicating the display width (step # 12). c ≦
In the case of N, the counter value c is directly stored in the data register 26
(D in FIG. 6) (step # 14),
If not (c> N), write (c-M) into the data register 26 (step # 16). Next, the counter value c
Is larger than a value (total value) M corresponding to one vertical cycle (step # 18). If c> M, the counter 40 is reset to 0 and the routine is terminated. When c ≦ M, this routine is terminated without any operation.

As described above, the current scanning position of a raster scanning type display device such as a CRT can be sequentially known by using the output of the counting means of the scanning line position detecting device of the present invention. Also, from the positive / negative value of the output of the selection means,
It is easy to know whether the raster scan is within the display period or during the retrace period, and the current position in each period (the current scan line position during the display period, Is the number of horizontal periods up to the start of the next vertical period). As one application example of the present invention, for example, even when the video memory has only one screen when outputting an image from a computer, it is possible to appropriately write the image data into the video memory based on the value obtained in this way. It is possible to generate a flicker-free real-time animation while saving memory.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a scanning line position detecting device for a computer system having an image output according to an embodiment of the present invention, and FIG. FIG. 3 is a block diagram of a vertical synchronizing signal generation circuit in a CRT controller, FIG. 4 is a waveform diagram of a vertical display signal and a vertical synchronizing signal, and FIG. 5 is a scanning line position detection of the embodiment. FIG. 6 is an explanatory diagram showing a change in the value of the counter and the value of the data register of the apparatus. FIG.

Claims (1)

(57) [Claims] 1. A scanning line position detecting device for a display device which performs raster-type scanning, a counting means for counting the number of horizontal synchronization signals after initialization, and holding data representing the number of horizontal synchronization signals in one vertical period. Total number holding means, first comparing means for comparing the output of the counting means with the output of the total number holding means, and reset for initializing the counting means when the output of the counting means exceeds the output of the total number holding means. Means, a display width number holding means for holding data representing the number of horizontal synchronization signals in the display period, a second comparing means for comparing the output of the counting means and the output of the display width number holding means, Subtracting means for subtracting the output of the total number holding means from the output; and selecting the output of the counting means when the output of the counting means is smaller than the output of the display width number holding means. Scan line position detecting device characterized by comprising a selection means for selectively outputting the output of the subtraction means when not.