JPH0593758A - Generation of in-circuit test pattern - Google Patents

Abstract

PURPOSE:To enable the generation of an in-circuit test pattern which requires neither the correction of control information nor the correction of a test pattern of an IC by preparing the control information to stop the operation of the IC on the input side of the IC to be tested considering a wiring state on a test board. CONSTITUTION:An arbitrary IC mounted on a board is extracted 1. In other words, the IC to be tested is selected from circuit models of the board. Circuit restraint conditions are generated. 2 in the generation of a test pattern from a wining state of an input signal line of the IC extracted and a pin attribute of an input circuit of the IC. The circuit restraint conditions are determined for all input pins of the IC extracted 1 while an error judgment 3 is made on whether the total of the number of drive pins of a tester used for the testing of the IC to be tested and the number of drive pins of a tester used to satisfy the restraint conditions is within the limited number of the tester. (When the judgment results are GOOD, a test pattern based on the circuit restraint conditions generated 2 previously is prepared 4.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electrical board assembly testing and, more particularly, to a test pattern generation method for in-board testing of boards.

[0002]

2. Description of the Related Art Conventionally, this type of in-circuit test pattern generation method has been held in a general-purpose library format for each IC, that is, a test object I which is made into a library.
The test pattern of C and the control information for stopping the operation of the IC are combined to create the test pattern of the target IC.

[0003]

In the above-mentioned conventional in-circuit test pattern generation method, control information for stopping the operation of the input side IC of the IC under test is held in a general-purpose library format for each IC. Therefore, depending on the wiring condition on the test board, the IC under test is not general-purpose and the control information in the library may not be used as it is, and the control information needs to be corrected.
Further, for the same reason, when the IC test pattern cannot be used for general purposes, the test pattern has to be modified and used.

An object of the present invention is to provide an in-circuit test pattern generation method which does not require modification of control information and modification of IC test patterns.

[0005]

The in-circuit test pattern generation method of the present invention is a test pattern generation method for an in-circuit test, which is performed as an assembly test of an electric board on which a plurality of ICs are mounted. A first step of extracting an arbitrary IC mounted in
By referring to the IC extracted in the extraction step, the pin attribute of the circuit on the input side of the IC, and the connection state of the signal line connected to the pin, the circuit constraint condition on the in-circuit test is determined. It is characterized by including a second step of obtaining and a third step of generating a test pattern based on the circuit constraint condition obtained by the circuit constraint condition creating step.

[0006]

[Operation] Considering the wiring condition on the test board, I
Since the control information for stopping the operation of the input IC of C is created, it is not necessary to hold it in the library format for each IC, and it is not necessary to modify the control information. Further, for the same reason, it is not necessary to correct the IC test pattern.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart of an in-circuit test pattern generation method which is an embodiment of the present invention.

In this embodiment, first, an arbitrary IC mounted on a board (not shown) is extracted. That is, an IC to be tested is selected from the circuit model of the board (step 1). Next, a circuit constraint condition for generating a test pattern is obtained from the wiring state of the input signal line of the IC extracted in step 1 and the pin attribute of the input circuit of the IC (step 2). Detailed contents of step 2 will be described later with reference to FIG.

Next, circuit constraint conditions are obtained for all input pins of the IC extracted in step 1, and are used to satisfy the number of drive pins and the constraint condition of the tester used for testing the IC under test. It is determined whether or not the total number of drive pins of the tester to be tested is within the limit of the tester (step 3). When the circuit constraint conditions are obtained for all input pins of the extracted IC and the total number of drive pins is within the limit number of the tester (GOOD), the test pattern based on the constraint conditions obtained in step 2 Generation is performed (step 4).

FIG. 2 is a detailed flowchart of step 2 of FIG.

First, the following step 2 is performed until the processing for obtaining the circuit constraint conditions for all the input pins of the IC under test is completed.
The end condition of this flow that repeats steps 2 to 27 is determined (step 21). Next, the unprocessed input pin of the IC under test is extracted, and the circuit trace (fan-in trace) is performed in the signal input direction to search for the pin of the input side IC of the IC under test (step 22). If the input IC is not registered in the library, the constraint condition cannot be created, and the process is terminated (step 23). Next, it is performed when the signal value (attribute) of the unprocessed input pin extracted in step 22 is fixed (step 24). For pins such as clamp pins and unused pins to which a fixed value is input, the fixed value of the pin is obtained from the circuit model and used as a constraint condition when generating a test pattern.

When the signal line of the unprocessed input pin extracted in step 22 is connected to the output pin of the IC under test (which is a feedback circuit), this signal line is used only for observation and control. Do not drive a value for the test pattern as a constraint condition when the test pattern is generated (step 25).

When the pin of the input side IC of the unprocessed input pin extracted in step 22 is a tristate pin, backtrace is performed on the circuit model so that the value of this pin is in the tristate state. If all the signal lines necessary for tri-state control can be controlled from the pins of the in-circuit tester, the obtained signal line and its value are used as the constraint conditions when generating the test pattern. If all the signal lines cannot be controlled, or if the number of signal lines required for control exceeds the number of tester drive pins, the constraint condition cannot be created and the process ends (step 26).

When the pin of the input side IC of the unprocessed input pin extracted in step 22 is a logic signal pin, the value of this pin becomes a signal value having a potential (not ground) on the circuit model. Backtrace. If all the signal lines required to have a potential on this pin can be controlled from the pins of the in-circuit tester, the obtained signal line and its value are used as constraint conditions when generating the test pattern. If the signal lines cannot be controlled or if the number of signal lines required for control exceeds the number of tester drive pins, the constraint condition cannot be created and the process ends (step 27).

FIG. 3 is a detailed flowchart of step 4 of FIG.

First, an IC to be tested according to the purpose of detecting a defective assembly of the board and the case of detecting a deterioration failure.
The failure is defined (step 31). Stored data 32
Is created in step 2 of FIG. 1, and control signal lines and control values are described as circuit constraints. Next, pre-assign processing is performed on the circuit model based on the stored data 32 (step 33). Finally, a test pattern is generated by a random pattern or an algorithm based on the constraint condition of the circuit (step 34).

[0018]

As described above, according to the present invention, the control information for stopping the operation of the input side IC of the IC under test is created in consideration of the wiring state on the test board, and the IC is formed in the library format. It is not necessary to hold each time and there is no need to modify the control information. Further, for the same reason, there is an effect that it is not necessary to correct the IC test pattern.

[Brief description of drawings]

FIG. 1 is a flowchart of an in-circuit test pattern generation method that is an embodiment of the present invention.

FIG. 2 is a detailed flowchart of step 2 in FIG.

FIG. 3 is a detailed flowchart of step 4 of FIG.

[Explanation of symbols]

1, 2, 3, 4, 21, 22, 23, 24, 25, 2
6, 27, 31, 33, 34 Step 32 Stored data

Claims (1)

[Claims] 1. A test pattern generation method for an in-circuit test, which is performed as an assembly test of an electrical board on which a plurality of ICs are mounted, wherein a first IC for extracting an arbitrary IC mounted on the board is used.
Of the IC extracted in the extraction step, the pin attribute of the circuit on the input side of the IC, and the connection state of the signal line connected to the pin, in the in-circuit test. An in-circuit test pattern generation method comprising: a second step of obtaining a circuit constraint condition; and a third step of generating a test pattern based on the circuit constraint condition obtained by the circuit constraint condition creating step.