JP3131047B2 - Wiring test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring test method,
The present invention relates to a wiring test method for testing a wiring pattern on a printed circuit board using a collective probe type tester.

[0002] The wiring pattern of a printed circuit board is becoming finer, and it is technically difficult to test all test points with a collective probe type tester. Therefore, a higher performance wiring test method is demanded.

[0003]

2. Description of the Related Art In a conventional test method for testing a wiring pattern on a printed circuit board, a test is performed on all test points using a collective probe type tester.

[0004]

At present, wiring patterns on printed circuit boards are becoming finer. If the above-mentioned conventional test methods are used to test the finer wiring patterns, it is difficult to position the jig. Yes, and also very expensive.

It is an object of the present invention to provide a wiring test method capable of performing a complete test on a wiring pattern of a miniaturized printed circuit board without any omission in the test.

[0006]

According to a first aspect of the present invention, there is provided a collective probe type tester (48, 8).
In a wiring test method for testing a wiring pattern of a printed circuit board using 2), a position of the collective probe type tester (48, 82) with respect to the wiring pattern is determined from CAD drawing data (12, 58) of the wiring pattern of the printed circuit board. The method comprises the steps of extracting test points that exceed the limit of alignment accuracy, and testing the test points (36 to 36) with a two-pin probe type tester (80).

According to a second aspect of the present invention, there is provided a wiring test method for testing a wiring pattern of a printed circuit board using a collective probe type tester (48, 82), wherein the CAD drawing data (12, 58) of the wiring pattern of the printed circuit board is provided. ),
Extracting a test point exceeding a limit of the alignment accuracy of the package probe type tester (48, 82) with respect to the wiring pattern;
And a step of adding test pads (50 to 50) for testing by the collective probe type tester (48).

[0008]

According to the first aspect of the present invention, the test points exceeding the limit of the alignment accuracy with respect to the wiring pattern of the collective probe type tester (48, 82) are determined from the CAD drawing data (12, 58) of the wiring pattern of the printed circuit board. The test points (36 to 36) are extracted and tested using a 2-pin probe tester (80).

Therefore, a test point which cannot be tested by the collective probe type tester can be tested, and a complete test without leakage can be performed. Note that, in this case, the other test points are tested with the collective probe type tester as in the related art.

[0010]

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 shows a configuration for carrying out a wiring test method according to a first embodiment of the present invention.

In FIG. 1, a net data extracting device 10
Is a data storage unit 14 for storing CAD drawing data 12
A display unit 18 for displaying the data in the data storage unit 14 on the display device 16, a correction unit 20 for correcting the data in the data storage unit 14, an instruction unit 22 for specifying an extraction condition, A test point extraction unit 24 for extracting test points from data in the data storage unit 14 based on the extraction conditions from the instruction unit 22;
Test point and data in the data storage unit 14 and substrate data (position data of contact holes and the like) 2
And a net data extraction unit 30 for extracting the net data 28 based on the sixth data. The correction unit 20 and the instruction unit 22 are set by the input device 32.

Here, referring to FIG. 2 showing a wiring pattern to be tested (for example, an LSI wiring pattern), FIG.
2A shows an initial wiring pattern, and FIG.
Then, the test points 34 to 34, 36 of the wiring pattern
To 36 are provided. This test point 34-3
Test points 36 to 36 among 4, 36 to 36 are arranged close to each other, and the positions of the test points 36 to 36 where the test pins hit are indicated by reference numerals 38 to 38. Here, the test points 36 to 36 are arranged close to each other, and the distance d is smaller than the minimum allowable distance do to the test pin, and therefore, the test points 36 to 36
It is difficult to apply a test pin to 36.

The net data extracting device 1 shown in FIG.
The net data extracting unit 30 in the test pattern 0 performs the processing described below with respect to the test points 34 to 34 and 36 to 36, so that the test points which cannot be tested by the collective probe type tester 48, Exceeds the limit of the alignment accuracy of the collective probe type tester 48 and extracts test points that cannot be tested. In parallel with this, the net data extracting unit 30 extracts the net data of the test point to be subjected to the normal test.

In FIG. 1, a test data creation unit 42 in a test data creation device 40 processes the net data 28 from the net data extraction device 10 to generate test data 44.
Create Based on the test data 44, the tester control device 46 controls the collective probe type tester 48 to test the wiring pattern.

Next, the operation will be described. In the net data extraction device 10, the CAD drawing data 12 is stored in the data storage unit 14 as wiring pattern data. The data stored in the data storage unit 14 is output to the display device 16 by the operation of the display unit 18 and displayed. The operator can correct the data in the data storage unit 14 by operating the input device 32 and operating the correction unit 20 while looking at the wiring pattern displayed on the display device 16. Here, a test pin cannot be applied to the miniaturized hattern by the conventional technique. However, if the data of the wiring pattern is corrected as described above and an additional process such as adding a test pad is performed, a test is performed on the additional test pad. You can hit the pin. Hereinafter, this point will be described with reference to FIG.

FIG. 2B shows a wiring pattern in which a test pad is added to the original wiring pattern of FIG. 2A, and in FIG.
The additional test pads 50 to 50 are formed corresponding to the test pads 36 to 36 and the additional test pads 50 to 50, respectively.
50 is connected by wires 52-52. And
Test pins can be applied to the additional test pads 50 to 50, and reference numerals 54 to 54 indicate positions where the test pins hit the additional test pads 50 to 50. Reference numerals 38 to 38 are the same as reference numerals 38 to 38 in FIG. 2A, and indicate positions where test pins hit test points 36 to 36 before test pads 50 to 50 are added.
By forming the additional test pads 50 to 50 in this manner, it is easy to apply test pins, and as a result,
All test points, including other test points that do not have additional test pads, can be tested only with the collective probe tester.

As described above, the data in the data storage unit 14 is modified. When the instruction unit 22 receives an instruction to extract a test point from the input device 32, the instruction unit 22
Supplies the extraction conditions to the test point extraction unit 24, whereby the test point extraction unit 24 extracts the specified test point data from the data storage unit 14, and supplies the extracted test point data to the net data extraction unit 30. The net data extracting unit 30 extracts the net data 28 based on the data specified by the test point extracting unit 24, the data from the data storage unit 14 and the conditions changed from the board data 26, and the specified conditions.

Using the extracted net data 28, the test data creation unit 42 in the test data creation device 40
Test data 44 is created, and based on the test data 44, the tester controller 46
8 to test the wiring pattern. Here, it should be noted that the test pads 50 to 50 are added to the test points 36 to 36 to which the test pins cannot be applied to make new test points, and the net data is extracted (FIG. 2 ( B)), all test points including other test points having no additional test pad can be tested only by the collective probe type tester. Second Embodiment Next, FIG. 3 shows a configuration for carrying out a wiring test method according to a second embodiment of the present invention. FIG. 2 shows a configuration of a combined test method of the collective probe type tester and the 2-pin probe type tester.

In FIG. 3, the net data extracting device 56
Although not shown, includes a data storage unit, a display unit, a correction unit, an instruction unit, a test point extraction unit, and a net data extraction unit as in the first embodiment of FIG. The net data extracting device 56 receives the CAD drawing data 58 and the board data 60, and a graphic display 62, a keyboard 64 and a mouse 66 are connected to the net data extracting device 56.

Using the net data 68 and 69 from the net data extracting device 56, a test data creating device 70
The test data creation unit 72 creates test data 74 for the 2-pin probe tester and test data 76 for the batch probe tester, and supplies both test data 74 and 76 to the tester controller 78. The tester controller 78 controls the 2-pin probe tester 8 based on the 2-pin test data 74.
0, and similarly, controls the collective probe type tester 82 based on the collective test data 76, thereby testing the wiring pattern.

Next, the operation will be described. When the CAD drawing data 58 is input to the net data extracting device 56, the operation is performed as follows. The wiring pattern obtained from the CAD drawing data 58 is displayed on the graphic display 62. Of the wiring patterns displayed on the graphic display 62, a test point at which it is difficult to apply a test pin, that is, a test point having an interval d between adjacent test points smaller than the minimum allowable interval do (see FIG. 2A)
) Is directly designated with the mouse 66 or the like. The net data 68 of the test point specified above is extracted by the net data extracting device 56. The test data creating device 70 creates 2-pin test data 74 for the test points extracted as described above. Net data 69 for other test points
Is extracted by the net data extraction device 56. The test data creation device 70 creates batch test data 76 for the test points extracted as described above. On the basis of the two-pin test data 74 created above, the tester controller 78 controls the two-pin probe tester 8
A test of the wiring pattern is performed using 0. Based on the batch test data 76 created above,
The tester control device 78 tests the wiring pattern using the collective probe type tester 82.

As described above, in the second embodiment of the present invention,
For test points where it is difficult to apply test pins, separate from the test data for batch probe testing,
Since the test data for the two-pin probe tester is created, such a difficult test point can be tested using the two-pin probe tester.

[0025]

As described above, according to the present invention,
Extract test points that exceed the limit of alignment accuracy for wiring patterns of the batch probe type tester Extract test points that exceed the limit of alignment accuracy for wiring patterns and test these extracted test points with a two-probe type tester Or a test is performed by a collective probe type tester with additional pads provided, so that a leak-free test can be performed on a wiring pattern of a miniaturized printed circuit board, and a complete test can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration for implementing a wiring test method according to a first embodiment of the present invention.

FIG. 2 shows a wiring pattern to be tested, and FIG.
FIG. 2B is a diagram of an initial wiring pattern, and FIG.

FIG. 3 is a diagram showing a configuration for implementing a wiring test method according to a second embodiment of the present invention.

[Description of Signs] 10 ... Net data extraction device 12 ... CAD drawing data 36-36 ... Test points that are difficult to test 48 ... Batch probe type tester 50 ... Additional test pad 56 ... Net data extraction device 58 ... CAD drawing data 80 ... 2 Pin probe type tester 82… Batch probe type tester

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeo Ogawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-4-19575 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/02

Claims (1)

(57) [Claims] 1. A wiring test method for testing a wiring pattern of a printed circuit board using a collective probe type tester (48, 82). Tester (48, 8
2) a step of extracting a test point exceeding the limit of the alignment accuracy with respect to the wiring pattern; and a step of testing the test points (36 to 36) with a two-pin probe tester (80). Characteristic wiring test method.