JPH0575417A - Semiconductor relay circuit - Google Patents

Abstract

PURPOSE:To realize a high speed semiconductor relay circuit by shortening the time required for boosting the gate-source voltage of an output FET and to provide the circuit configuration in which the values of circuit components is easily set. CONSTITUTION:A transistor(TR) 6 reaching a low impedance when a charge current flows to the gate of an output FET 4 to form a charging path for a gate-source storage charge of the output FET 4 is connected between the drain and the gate of the output FET 4 via a reverse current blocking rectifier element 7, and the circuit is formed separately from a control circuit forming the discharge path of a stored charge between the gate and the source of the output FET 4. In this case, the circuit constants are set more easily than in a conventional circuit and the switching characteristic is equivalent to or more than that of the conventional circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor relay circuit using an optical coupling system for isolation between input and output.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional semiconductor relay circuit (Japanese Patent Application No. 1-166325). The circuit configuration will be described below. A light emitting diode 1 is connected between the relay input terminals I1 and I2. A photovoltaic diode array 2 is optically coupled to the light emitting diode 1. The positive electrode of the photovoltaic diode array 2 is connected to the gate of an NMOS-type enhancement mode output FET 4 via a resistor 3. The negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. The source and drain of the depletion mode control FET 5 are connected to the gate and source of the output FET 4, respectively. The gate of the control FET 5 is connected to the positive electrode of the photovoltaic diode array 2. The drain and source of the output FET 4 are connected to the relay output terminals O1 and O2, respectively. Further, the base of the NPN transistor 6 is connected to the positive electrode of the photovoltaic diode array 2, the emitter is connected to the gate of the output FET 4, and the collector is connected to the drain of the output FET 4 via the rectifying element 7 for preventing backflow. is doing.

A signal source S as an external circuit is connected between the relay input terminals I1 and I2 via a resistor R. Between the relay output terminals O1 and O2, a load Z is provided as an external circuit.
And a series circuit of the DC power source E are connected with the polarities shown. Now, when an input current flows from the signal source S to the light emitting diode 1 via the resistor R, the light emitting diode 1 generates an optical signal. Upon receiving this optical signal, the photovoltaic diode array 2 generates a current. This current always flows through the resistor 3 through the source and drain of the control FET 5 which is in a low impedance state. When the voltage generated by the resistor 3 exceeds the threshold voltage of the control FET 5, the control FET 5
5 is in a high impedance state. As a result, the current from the photovoltaic diode array 2 is transferred to the output FET 4
Charge between the gate and source of. Further, the voltage generated by the resistor 3 forward-biases between the base and the emitter of the transistor 6, so that the collector and the emitter of the transistor 6 become conductive. As a result, from the DC power source E to the load Z, the relay output terminal O1, the backflow preventing rectifying element 7,
A charging current flows between the gate and the source of the output FET 4 through the collector and the emitter of the transistor 6. Therefore, the gate-source voltage of the output FET 4 rapidly rises. When this voltage exceeds the threshold voltage of the output FET 4, the output FET 4 is turned on and the relay output terminals O1 and O2 are electrically connected. As a result, a load current flows from the DC power source E to the load Z. After that, a slight current flows through the resistor 3 through the source / drain of the control FET 5, and the bias voltage generated in the resistor 3 keeps the control FET 5 in a high impedance state. Since the drain-source voltage becomes almost zero after the output FET 4 is completely turned on, the photovoltaic diode array 2
Current flows from the drain to the source of the output FET 4 via the PN junction between the base and collector of the transistor 6, but the rectifying element 7 for blocking the reverse current is provided in this path. , No current flows.

When the input current between the relay input terminals I1 and I2 is cut off and the light signal from the light emitting diode 1 disappears, the output current from the photovoltaic diode array 2 disappears. At this time, since the transistor 6 is reverse-biased between the base and the emitter by the gate-source voltage of the output FET 4, the collector and the emitter thereof are non-conductive. In addition, since the gate-source voltage of the control FET 5 decreases due to the disappearance of the photoelectromotive force, the control FET 5 enters a low impedance state, and the output FE
The electric charge accumulated in the gate-source capacitance of T4 is rapidly discharged through the control FET5. As a result, the output FET 4 is turned off and the relay output terminals O1 and O2 are cut off.

[0005]

In the prior art, the resistor 3 for biasing the control FET 5 to the high impedance state is used to obtain the forward bias for making the transistor 6 conductive. Therefore, the control FET5
Is a threshold voltage Vth of the base-emitter voltage (about 0.5) when the transistor 6 becomes conductive.
It cannot be set higher than V). Otherwise, control FE
T5 cannot be in a high impedance state indefinitely. Also, the threshold voltage Vt of the control FET 5
h is a current Id that can flow between the drain and the source of the FET 5 when the gate and the source thereof are not biased.
There is a positive correlation with s. This current Ids is output FET
When 4 becomes non-conducting, it becomes the discharge current of the accumulated charge between its gate and source. Therefore, this current Ids
Is larger, the turn-off time of the output FET 4 can be shortened. However, as described above, in the conventional circuit, F
Since the threshold voltage of ET5 cannot be set higher than about 0.5 V, the current Ids could not be increased above a certain value.

The present invention has been made in view of the above circumstances, and an object of the present invention is to shorten the time required for increasing the gate-source voltage of an output FET to increase the speed of a semiconductor relay circuit. And to provide a circuit configuration in which constants of circuit elements can be easily set.

[0007]

According to the present invention, in order to solve the above problems, as shown in FIG. 1, a light emitting diode 1 for generating an optical signal in response to an input signal, and a light emitting diode. 1. The photovoltaic diode array 2 arranged to receive the optical signal of No. 1, the resistor 3 connected in series with the photovoltaic diode array 2, and the photovoltaic power of the photovoltaic diode array 2 to the resistor 3 An output FET 4 which is applied between the gate and the source via the gate and switches between a conductive state and a non-conductive state between the drain and the source; and a control circuit which forms a discharge path for accumulated charge between the gate and the source of the FET 4. In the provided semiconductor relay circuit, an output FET
When a charging current flows to the gate of the output FET 4, a semiconductor element such as a transistor 6 which is in a low impedance state and forms a charging path of the accumulated charge between the gate and the source of the output FET 4 is connected to the drain gate of the output FET 4. It is characterized in that a rectifying element 7 for blocking backflow is connected between them.

[0008]

In the present invention, when the charging current flows through the gate of the output FET 4, the impedance becomes low.
A semiconductor element such as a transistor 6 which forms a charge path for the accumulated charge between the gate and the source of the output FET 4 is
The output FET 4 is connected between the drain and the gate through a rectifying element 7 for preventing backflow, and this circuit is connected to the output FET.
Since it is configured separately from the control circuit that forms the discharge path of the accumulated charge between the gate and the source of 4, it is easier to set the circuit constant than before, and it is possible to obtain the same or higher switching characteristics. It was

[0009]

FIG. 1 is a circuit diagram of an embodiment of the present invention. The circuit configuration will be described below. Relay input terminal I
The light emitting diode 1 is connected between 1 and I2.
A photovoltaic diode array 2 is optically coupled to the light emitting diode 1. The positive electrode of the photovoltaic diode array 2 is connected to the gate of the NMOS type enhancement mode output FET 4 via the resistors 3 and 8. The negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. The depletion mode control FET 5 is connected to the gate of the output FET 4 via the anode and cathode of the diode 9.
Source is connected. The source of the output FET 4 is connected to the drain of the depletion mode control FET 5. The gate of the control FET 5 is connected to the positive electrode of the photovoltaic diode array 2. The drain and source of the output FET 4 are connected to the relay output terminals O1 and O2, respectively. Also, NPN
The base of the transistor 6 is connected to the connection point of the resistor 3 and the resistor 8, the emitter is connected to the gate of the output FET 4, and the collector is connected to the output FET through the backflow blocking rectifier 7.
It is connected to the drain of 4.

A signal source S as an external circuit is connected between the relay input terminals I1 and I2 via a resistor R. Between the relay output terminals O1 and O2, a load Z is provided as an external circuit.
And a series circuit of the DC power source E are connected with the polarities shown. Now, when an input current flows from the signal source S to the light emitting diode 1 via the resistor R, the light emitting diode 1 generates an optical signal. Upon receiving this optical signal, the photovoltaic diode array 2 generates a current. This current always flows through the resistor 3 through the source and drain of the control FET 5 which is in a low impedance state. When the voltage generated by the resistor 3 exceeds the threshold voltage of the control FET 5, the control FET 5
5 is in a high impedance state. As a result, the current from the photovoltaic diode array 2 is transferred to the output FET 4
Charge between the gate and source of. Further, a charging current flows between the gate and the source of the output FET 4 via the resistor 8, and a voltage is generated across the resistor 8. The voltage generated by the resistor 8 forward-biases between the base and emitter of the transistor 6, so that the collector and emitter of the transistor 6 become conductive. As a result, from the DC power source E through the load Z, the relay output terminal O1, the backflow blocking rectifying element 7, and the collector-emitter of the transistor 6,
A charging current flows between the gate and source of the output FET4. Therefore, the gate-source voltage of the output FET 4 rapidly rises. When this voltage exceeds the threshold voltage of the output FET 4, the output FET 4 is turned on and the relay output terminals O1 and O2 are electrically connected. As a result, a load current flows from the DC power source E to the load Z. After that, a slight current flows through the resistor 3 between the source and drain of the control FET 5, and the bias voltage generated in the resistor 3 keeps the control FET 5 in a high impedance state. Output FET
After 4 is completely turned on, the drain-source voltage becomes almost zero, so that the current from the photovoltaic diode array 2 is output via the PN junction between the base and collector of the transistor 6. An attempt is made to flow between the drain and source of the FET 4 for use, but no current flows because a rectifying element 7 for preventing backflow is provided in this path.

When the input current between the relay input terminals I1 and I2 is cut off and the optical signal from the light emitting diode 1 disappears, the output current from the photovoltaic diode array 2 disappears. At this time, since the transistor 6 is reverse-biased between the base and the emitter by the gate-source voltage of the output FET 4, the collector and the emitter thereof are non-conductive. In addition, since the gate-source voltage of the control FET 5 decreases due to the disappearance of the photoelectromotive force, the control FET 5 enters a low impedance state, and the output FE
The charge accumulated in the gate-source capacitance of T4 is rapidly discharged through the diode 9 and the control FET 5. As a result, the output FET 4 is turned off,
The relay output terminals O1 and O2 are cut off.

FIG. 2 is a circuit diagram of another embodiment of the present invention. In this embodiment, an enhancement type MOSFET 16 is connected instead of the bipolar type transistor 6. That is, the gate of the MOSFET 16 is connected to the resistor 3
Connected to the positive electrode of the photovoltaic diode array 2 via
The source is connected to the gate of the output FET 4, and the drain is connected to the drain of the output FET 4 via the rectifying element 7 for blocking backflow. The operation is similar to that of the embodiment shown in FIG.

[0013]

According to the present invention, a circuit for accelerating the turn-on of a semiconductor relay and a circuit for accelerating the turn-off of the semiconductor relay can be separately formed, and the constants of circuit elements can be easily set and the semiconductor can be operated at high speed. There is an effect that a relay can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 1 Light Emitting Diode 2 Photovoltaic Diode Array 3 Resistor 4 Output FET 5 Control FET 6 Transistor 7 Rectifier 8 Resistor 9 Diode

Claims (1)

[Claims] 1. A light emitting diode that generates an optical signal in response to an input signal, a photovoltaic diode array arranged to receive the optical signal of the light emitting diode, and a series connection to the photovoltaic diode array. A resistor, an output FET in which the photovoltaic power of the photovoltaic diode array is applied between the gate and the source through the resistor to switch between a conductive state and a non-conductive state between the drain and the source, and the FE.
In a semiconductor relay circuit including a control circuit that forms a discharge path for accumulated charge between the gate and source of T, when a charging current flows through the gate of the output FET, a low impedance state occurs, and the gate of the output FET A semiconductor relay circuit characterized in that a semiconductor element such as a transistor forming a charge path for accumulated charge between sources is connected between a drain and a gate of the output FET via a rectifying element for preventing backflow.