JPH0546365Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data receiving circuit that receives serial digital data.

[Prior Art] Such a serial data receiving circuit has conventionally been constructed as shown in FIG. In the figure, serial data Data and a driving clock RCK having a frequency that is an integral multiple (for example, 16 times) of the data are input to a data sample circuit 19, and its output is input to the serial input SI of the shift register 6, the start bit confirmation circuit 17, and The signal is input to the parity check circuit 13. Further, the clock generation circuit 12, stop bit confirmation circuit 18, and latch pulse generation circuit 14 are driven by the drive clock RCK. The clock from the clock generating circuit 12 is input to the counter 16, and the shift clock SCK generated by the counter 16 is input to the clock input CK of the shift register 6. The clock PCK generated by the counter 16 is also input to the parity check circuit 13 and the stop bit confirmation circuit 18. The clock is also input to the start bit confirmation circuit 17. Furthermore, the initialization pulse Fend from the latch pulse generation circuit 14 is sent to the counter 16,
The latch pulse is input to the parity check circuit 13 and the start bit confirmation circuit 17, and the latch pulse generation circuit 14 outputs a latch pulse Latch based on the outputs of the parity check circuit 13 and the stop bit confirmation circuit 18, and inputs the latch pulse to the enable input EN of the latch circuit 7. is input.

The operation of this configuration will be explained with reference to timing charts shown in FIGS. 5a to 5e. As shown in figure a, the serial data Data is at H level when reset is applied, and one frame of data starts from the start bit at L level, and consists of data bits 1 to 8 and parity bit P.
and an H level stop bit. First, after each part is reset by the reset signal Reset, when the serial data Data shown in FIG. Detected and synchronized. When the confirmation circuit 17 confirms the start bit, it generates an output, and the clock generation circuit 12 is driven to generate the shift clock SCK shown in FIG. When the first clock of the shift clock SCK is input to the start bit confirmation circuit 17 and it is detected that it is in the L level state, the clock generation circuit 12
The second and subsequent clocks are output via the counter 16. On the other hand, since the serial data Data is input to the shift register (8 bits) 6, this data is sequentially shifted from MSB to LSB using the shift clock SCK. At the same time, serial data is also taken into the parity check circuit by the clock PCK generated by the counter 16. Since the data bits of the serial data are 8 bits,
The shift clock SCK is set from the MSB to the LSB of the shift register 6 at the ninth clock.
Confirm the stop bit and perform a parity check including the stop bit at the 11th pulse of PCK. As a result of the parity check and stop bit confirmation, if the data is normal, the latch pulse generation circuit 14 outputs the latch pulse Latch at the 11th pulse of PCK as shown in FIG. do. Also, at the same timing, the initialization pulse Fend is output to initialize the parity check circuit 13, counter 16, and start bit confirmation circuit 17.

[The problem that the idea aims to solve]

In such a conventional configuration, for example, in FIG. 4, the counter 16 counts the shift clock SCK by "9" in order to input the data bit into the shift register 6, and further counts the shift clock SCK by "11" to confirm the parity check and stop bit. , and a 4-bit counter 16 is required. Furthermore, various control circuits are required to perform parity checks and stop bit checks when the count value of the shift clock SCK is from "9" to "11", making the circuits complicated.

Therefore, an object of the present invention is to provide a data receiving circuit with a simple circuit configuration that does not require a counter or a control circuit.

[Means to solve the problem]

The configuration of the present invention to solve the above problems includes a clock generation circuit that is driven by a reset signal, initialized and re-driven by a start bit, and has at least a start bit and the number of bits of serial digital data, and is in an initialized state. A shift register in which data having a polarity opposite to that of the start bit is set and the duty setting data is sequentially inputted from MSB to LSB by a clock from the clock generating circuit, and a latch circuit that latches the output of the shift register. ,
It is detected that a start bit is set in the MSB of the shift register and that the start bit is shifted to the LSB by the clock, and this MSB is set.
The data input to the shift register during the period from 1 to LSB is detected as received data.

Further, for the same purpose, a data receiving circuit that receives serial digital data starting from a start bit is driven by a reset signal, and a clock generating circuit that is initialized and re-driven by the start bit, and at least a clock generating circuit that receives serial digital data starting from the start bit. It has the number of bits of serial digital data, and in the initialization state, data with a polarity opposite to that of the start bit is set, and the start bit and serial digital data are sequentially input from MSB to LSB by the clock from the clock generation circuit. It comprises a shift register and a latch circuit that latches the output of the shift register, a start bit is set in the MSB of the shift register, and the start bit is set by the clock.
The shift to LSB is detected, and the data input to the shift register during the period from MSB to LSB is detected as the serial digital data.

[Effect]

In the above configuration, serial data is sequentially input to the shift register by the shift clock SCK from the clock generation circuit, but the data before the start bit is equal to the data set in the shift register in the initialized state. Therefore, the state of the shift register does not change. On the other hand, when the start bit is input to the MSB of the shift register, it is sequentially shifted by the shift register SCK,
When set to LSB, serial digital data is set in the shift register. Therefore
It detects that the contents of the LSB have changed from the initialized state to the start bit data, and outputs the serial digital data of the shift register to the latch circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 4 are denoted by the same reference numerals. Serial data Data and driving clock RCK
is input to the data edge detection circuit 15, of which data Data is input to the shift register 6, and the inverted data is input to the parity check circuit 13.
is input. The shift register 6 is assumed to have one frame worth of duty determination data (11 bits).
In addition, the data edge detection signal is output from the clock generation circuit 1.
The shift clock SCK is input to the clock input CK of the shift register 6 and the parity check circuit 13. The MSB and LSB data from the shift register 6 and the output of the parity check circuit 13 are input to the latch pulse generation circuit 14, which outputs the latch pulse Latch to the latch circuit 7, and performs the parity check with the shift register 6 by the initialization pulse Fend. Output to circuit 13.

The operation of this configuration will be explained with reference to the timing charts in FIGS. 2a to 2d and the state diagram of the shift register 6 in FIG. 3. The clock generating circuit 12 is driven by the reset signal Reset as shown in FIG. 2B, and outputs a shift clock SCK. The shift clock SCK is data edge detection circuit 1
5, when the serial data Data changes from H level to L level, it is initialized and re-driven. The shift register 6 is initialized by a reset signal Reset and an initialization pulse Fend, and in this initialization state, data (H level) having a polarity opposite to that of the start bit is set in MSB to LSB. Therefore, even during the period T before the start bit is detected, the shift clock SCK
Since the serial data Data is being outputted, the serial data Data is input to the shift register and taken in. However, during this period T, the data Data is at H level like the data set in the shift register 6, so the serial data Data is input to the shift register 6. The state does not change. Next, when an edge is detected in the data, the clock generating circuit 12 is initialized, and the L level data of the start bit is set in the MSB of the shift register 6 by the first pulse after initialization, as shown in FIG. Data bits are captured from the 2nd pulse to the 9th pulse, and the start bits are sequentially captured.
Shift from MSB to LSB. and the 11th
The start bit is set to LSB by the pulse, and shift register 6 contains one frame's worth of data from the start bit to the stop bit.
Data is imported. Further, the parity check circuit 13 receives inverted data of the serial data Data. At this time, during the period T after initialization until the start bit, data is input by the shift clock SCK, but since this data is at the L level, it is equal to the initial value of the parity check circuit 13, so the state does not change. Next, when the inverted start bit data (H level) is input, the next 9 bits of data (up to the parity bit) are treated as data to be parity checked, and a parity check is performed.

From the above, when the LSB of the shift register 6 changes from the H level to the L level, the result of the parity check at that time and the data of the MSB, that is, the H level data of the stop bits, are checked, and as shown in Figure 2 c and d. , a latch pulse Latch and an initialization pulse Fend are output, and the data of the 8 data bits set in the second to ninth bits of the shift register 6 are latched. Further, the shift register 6 is initialized, all digits are set to H level data, and the parity check circuit 13 is initialized.

According to the above configuration, the shift register is set to the number of bits of one frame of serial data, detects that the LSB becomes a start bit, and ends the data acquisition of the shift register. That is, the shift register performs the functions of the counter 16 and start bit and stop bit confirmation circuits 17 and 18 in FIG. 4 by counting the shift clock SCK. Further, the drive clock for the parity check circuit 13 and shift register 6 can be shared. Furthermore, since the clock generating circuit 12 is initialized by detecting the data edge of the serial data Data, synchronization can be achieved in the middle of the data.

〔effect〕

As described above, according to the present invention, the data receiving circuit can be configured in a simplified manner, and synchronization can be achieved in the middle of data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data receiving circuit of the present invention, FIG. 2 is a timing chart showing waveforms of each part in FIG. 1, FIG. 3 is a diagram showing the state of the shift register in FIG. Fig. 4 is a block diagram showing a conventional data receiving circuit, Fig. 5 is a timing chart showing waveforms of each part in Fig. 4, 6...Shift register, 7...Latch circuit, 1
2... Clock generation circuit, 13... Parity check circuit, 14... Latch pulse generation circuit.

Claims (1)

[Claims for Utility Model Registration] A data receiving circuit that receives serial digital data starting from a start bit, comprising: a clock generating circuit driven by a reset signal and initialized and re-driven by the start bit; It has a start bit and the number of bits of serial digital data, and in the initialization state, data with the opposite polarity to the data polarity of the start bit is set, and the start bit and serial digital data are sequentially generated from MSB to LSB by the clock from the clock generation circuit. and a latch circuit that latches the output of the shift register, and detects that a start bit is set in the MSB of the shift register and that the start bit is shifted to the LSB by the clock;
A data receiving circuit characterized in that data input to a shift register during a period from MSB to LSB is detected as the serial digital data.