JPH0541452A - Standard cell system integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the width of a circuit and enhance its degree of integration by laying out and interconnecting automatically standard cell groups designed to share a diffusion layer of the same potential with adjacent cells. CONSTITUTION:A cell basic frame 1 is positioned on the outside of diffusion layers 2a and 2b. However, in the case where cell connection frames 1b, 1c and 1d are on the inner side than the cell basic frame 1 and adjacent cells are located in the same connection frame (e.g. 1b), they are laid out so that they may be connected with each other. The connection frames include three types of potentials, say, a power source potential and a grounding potential 1b, a power source potential and a power source potential 1c and a ground potential and a grounding potential 1d. They are registered in one library together with input/output information. As for a sharing method for the connection frames, it is selected that the cells be arrayed so that their horizontal direction may be minimized. This construction makes it possible to reduce the cells by about 20%.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type integrated circuit for automatic placement and wiring, and more particularly to a method for connecting adjacent standard cells.

[0002]

2. Description of the Related Art As an example of a standard cell type integrated circuit for automatic placement and wiring according to the prior art, a two-layer aluminum CM
The OS circuit will be described with reference to FIG.

A power line 4a and a ground line 4b made of a first aluminum wiring are arranged in a basic frame 1 of the cell. The input to the cell is connected to the polysilicon gate electrode 3a from the first aluminum 4 in the wiring channel 9 through the polysilicon wiring 3. The output is designed to connect from the diffusion layer contact 2c to the second aluminum 5 through the first aluminum 4.
This is a 5-layer wiring cell. The diffusion layers 2a and 2b in the cell are formed inside the cell frame 1 so as not to short-circuit with the diffusion layers 2a and 2b of the adjacent outer cells. The cells are arranged so that the vertical sides of the cell frame 1 are in contact with each other.

FIG. 4 shows an inverter having two stages and two inputs of N.
A circuit in which one OR and one NAND are arranged side by side is simplified and partially symbolized.

[0005]

In the standard cell according to the prior art, since the diffusion layer is formed inside the cell, the diffusion layers having the same potential such as the power supply or the ground potential cannot be shared with each other.

Therefore, there is a drawback that the lateral dimension becomes large.

[0007]

In the standard cell type semiconductor integrated circuit with automatic placement / wiring of the present invention, cells are configured so that adjacent diffusion cells can share a diffusion layer region of the same potential, and The cell information for enabling is registered in the cell library together with the input / output terminal information.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the structure of a standard cell. Figure 1 (a)
Is an inverter, FIG. 1 (b) is a 2-input NOR, FIG. 1 (c)
Indicates a 2-input NAND. The basic frame 1 of the cell is outside the diffusion layers 2a and 2b, as in FIG. 4 in the prior art. However, if the cell connection frames 1b, 1c, and 1d are inside the cell basic frame 1, and adjacent cells have the same connection frame (for example, 1b and 1b), they are arranged so as to be in contact with each other. . There are three types of frames for connection: power supply potential and ground potential 1b, power supply potential and power supply potential 1c, and ground potential and ground potential 1d, which are registered together with input / output terminal information in one library.

FIG. 1 (d) shows a circuit in which two stages of the same inverter as in FIG. 4 of the prior art and two inputs of NOR and NAND are connected one stage each. In FIG. 1 (d), the circuit has an additional two-input NAND.

Here, FIG. 1 will be supplementarily described with reference to FIG.
2 of FIG. 2A, FIG. 2B, FIG. 2C, and FIG.
When two cells are connected in series in series, they are shown in FIG.
Since it has a common connection frame 1b with (b), FIG.
FIG. 2 (e) shows the cell of (a) arranged upside down. The upper and lower sides are shown by writing an uppercase F in each cell. Figure 2
Since (b) and FIG. 2 (c) have a common connection frame 1c, they can be connected as they are. Both FIG. 2C and FIG. 2D have the connection frame 1d, but the arrangement of FIG. 2C has already been decided, and the connection frame 1d cannot be shared with FIG. 2D.

2 (b) and 2 (c) show the connection frame 1
If d is not shared, as shown in FIG.
2C is turned over and FIG. 2C and FIG.
d can be shared.

There are a plurality of methods for sharing the connection frame, and it is possible to arrange the cells and select the combination that minimizes the horizontal direction. Actually, even if cells are sequentially arranged so that the connection frame can be shared, there is no great difference in the horizontal dimension. In this embodiment, FIG.
As shown in the width 10 of (d), the width 10 of the prior art FIG.
It was possible to reduce the area by about 20% as compared with.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 3 shows a circuit in which two inverters shown in FIG. 3A are connected in parallel and the diffusion layer region of the same potential is shared to reduce the diffusion capacitance of the output section to realize high performance.
It shows in (b). Also in this embodiment, the same effect can be obtained by changing the combination of the common connection frames for the power supply / ground potential.

[0016]

EFFECTS OF THE INVENTION A standard cell group designed to share a diffusion layer region of the same potential between adjacent cells is automatically arranged and wired so as to share the diffusion layer.

As a result, as compared with the width 10 of the prior art shown in FIG. 4, as shown by the width 10 of FIG. 1 (d) according to the present invention, the degree of integration can be improved by about 20%.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a first embodiment of the present invention.

FIG. 2 is a schematic plan view illustrating the arrangement and orientation of the cells of FIG.

FIG. 3 is a schematic plan view showing a second embodiment of the present invention.

FIG. 4 is a schematic plan view showing a standard cell and its layout and wiring according to a conventional technique.

[Explanation of symbols]

1 Cell Basic Frame 1a, 1b, 1c, 1d Connection Frame 2a N ⁺ Type Diffusion Layer 2b P ⁺ Type Diffusion Layer 2c Diffusion Layer Contact 3 Polysilicon Wiring 3a Polysilicon Gate Electrode 4 First Aluminum 4a Power Supply First Aluminum 4b Grounding first aluminum 5 Second aluminum 6 Diffusion layer contact 7 Polysilicon-first aluminum contact 8 First aluminum-second aluminum contact 9 Wiring channel 10 Width

Claims (1)

[Claims] 1. A semiconductor integrated circuit using a standard cell method, characterized in that a standard cell group designed so that adjacent cells can share a diffusion layer region of the same potential is automatically arranged and wired. Cellular integrated circuit.