JPH10173055A - Cell-based semiconductor device and standard cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cell area with ensuring a certain degree of freedom of the signal line interconnection between cells. SOLUTION: The cell composed of combined desired circuit function blocks, including basic elements 1, 2, inner wiring 10 for internally connecting the basic elements 1, 2, and power lines 11, 12 for feeding power voltages to the elements 1, 2; the lines 11, 12 being interconnected between cells adjacent to both sides of one element. The signal line 10 is composed of a lower wiring layer than the power lines 11, 12. A not shown signal line wiring laminated above the lines 11, 12 form external signal lines wiring input/output terminals of different cells. This allows the second layer and following wiring layers to be used as power lines, the line width thereof to be reduced more than that in prior art, and the cell area to be reduced because of effective use of the lower layers of the power lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell-based semiconductor device capable of reducing the cell area while securing a certain degree of freedom in connecting signal lines between cells, and a standard cell.

[0002]

2. Description of the Related Art Conventionally, a so-called cell-based (or building block system) semi-custom design method has been developed by using an ASIC (Application Specific Integrated Circuit).
ircuit) Widely used in design. In this design method, common design assets registered in a library are combined, and an I / O tool is used by using an automatic placement and routing tool.
The efficiency of the C design is improved. Cell-based ASICs
Unit logic circuit registered in the cell (or element only)
And a general cell system in which already designed circuit function blocks are arranged and wired in a hierarchical structure.

FIGS. 3 and 4 are pattern diagrams illustrating a conventional unit cell used for designing a cell-based ASIC and registered in a library in advance. FIG. 3 shows a two-input NAND cell, and FIG. 4 shows a three-input NOR cell. 3 and 4, reference numeral 1 denotes a P-channel MOS transistor (hereinafter referred to as PMOS), and reference numeral 2 denotes an N-channel M transistor.
OS transistor (hereinafter referred to as NMOS), 3 is a p-type active region, 4 is an n-type active region, 5 is a gate electrode, 6 is a P-type active region.
The drain region (p ⁺ impurity diffusion region) of MOS 1, 7 is the source region (p ⁺ impurity diffusion region) of PMOS ¹ , 8 is the drain region (n ⁺ impurity diffusion region) of NMOS ² , 9
Is the source region (n ⁺ impurity diffusion region) of NMOS2, 1
0 is an internal signal line, 11 is a power supply voltage supply line, and 12 is GND
These are patterns of lines (in the present invention, 11 and 12 are collectively referred to as power supply lines).

The gate electrode 5 is made of, for example, a first layer of polysilicon (1PS), polycide, or the like. An input terminal T _IN is provided in the middle of each gate electrode 5.

The internal signal line 10 is formed of a second-layer film of polysilicon (2PS), polycide, tungsten, or the like, which is stacked on the gate electrode 5 with an interlayer insulating layer interposed therebetween. A first contact (1CNT) is provided on the interlayer insulating layer under the internal signal line 10. This 1CN
The internal signal line 10 is connected to the drain region 6 of the PMOS 1 and one drain region 8 of the NMOS 2 via T. In the middle of the internal signal line 10, the output terminal T _OUT
Is provided.

On the other hand, the power supply lines 11 and 12 are wired in parallel in one direction in the upper and lower portions of the cells, and the wiring width is different between different types of cells (in this example, the NAND cell of FIG. 3 and the NOR cell of FIG. 4). (Between cells). This is because the internal power supply lines 11 and the GND lines 12 are connected in series only by arranging cells of different types in one direction. The power supply voltage supply line 11 is connected to the source region of the PMOS via 1 CNT. The GND line 12 is connected to the other source region 9 of the NMOS 2 via 1 CNT.

In the design of a conventional cell-based ASIC using the unit cell configured as described above, if the necessary functions, performances, and constraints based on customer specifications are given to an automatic placement and routing tool, the automatic placement and routing is performed. The tool calls an appropriate logic circuit cell (unit cell) from the library and performs an optimal pattern design. That is, after unit cells of different types are automatically combined and arranged so as to satisfy customer specifications (functions and performances), the arranged cells are automatically connected by multilayer wiring.

For example, in the examples shown in FIGS. 3 and 4, power supply voltage supply lines 11 in a cell column are
The GND lines 12 are interconnected with each other. In the automatic wiring, wiring of an external signal line for interconnecting the input / output terminals T _IN and T _OUT between cells and the power supply voltage supply line 1 of each cell row are used.
1 and the wiring of the external power supply line for sharing the cell line GND line 12 with each other.

[0009]

A unit cell in which a circuit or an element having a predetermined function is pre-installed is provided for configuring various circuit function blocks in accordance with customer requirements as described above. In the design stage, it is required that the degree of freedom of the interconnection between the cells be large so as to be applicable to any circuit. Specifically, that the degree of freedom of wiring for cell-to-cell connection means that the pattern or connection point of the unit cell itself does not hinder the connection of the external signal line later. Therefore, in FIGS. 3 and 4, for example, the internal signal line 10, the power supply voltage supply line 11, and the GND line 12 are all connected to the first wiring layer (for example,
Tungsten layer) is used. In this wiring, the problem of signal delay must be considered. In other words, the signal lines that connect near each other use lower-layer wiring, and wiring that carries signals far away, such as clock lines and bus lines, has less wiring and a high degree of freedom in wiring.
In addition, the use of different wiring layers according to the type of signal is made, such as using the upper wiring having lower resistance.

On the other hand, from the standpoint of a semiconductor process, as the wiring structure becomes more multilayered, planarization becomes more important in consideration of the easiness of later processes, and it is better to make the film thinner on the lower side and thicker on the upper side. preferable. In addition, in terms of workability, L & S (Line and Space)
It is preferable to increase the interval, and the lowermost layer often has to use a relatively high-resistance material such as a tungsten film. In view of the above, the first wiring layer is made of a material having a relatively high resistivity, such as 1PS or a tungsten film, and is relatively thin, so that the internal wiring connecting adjacent elements is formed. Suitable as a layer.

However, in recent cell-based ASICs, which may have a large-scale circuit configuration, the disadvantage of using the first wiring layer as a power supply line inside the cell is that the freedom of wiring between cells is secured. Has become relatively large in relation to. That is, in recent IC manufacturing processes, 4
By increasing the number of wiring structures such as layers and five layers, wiring resources are increased, and the degree of freedom of wiring is also increased. In addition, as logic circuits have become larger and faster, demands for smaller areas and shorter wiring lengths have gradually increased. Wiring is to be performed. However, in the conventional cell structure, since the power supply line inside the cell is constituted by the first wiring layer having a high sheet resistance, the internal power supply line width is inevitably widened. In fact, it was difficult to reduce the area.

The present invention has been made in view of such circumstances, and provides a cell-based semiconductor device and a standard cell capable of reducing the cell area while securing a certain degree of freedom in connecting signal lines between cells. The purpose is to do.

[0013]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a cell-based semiconductor device of the present invention comprises a plurality of types of cells in which at least a basic element is formed in advance. Is a cell-based semiconductor device in which a desired circuit function block is configured by arbitrarily combining, the cell includes a plurality of basic elements, and an internal signal line connecting the plurality of basic elements inside the cell. A power supply line connected to cells adjacent to each other on both sides in one direction and supplying a power supply voltage to the basic element, wherein the internal signal line is formed of a wiring layer lower than the power supply line. The signal line wiring layer stacked above the power supply line constitutes an external signal line for connecting input / output terminals of different cells.

As described above, in the present cell-based semiconductor device, the power supply line in the cell is constituted by the wiring layer above the internal signal line, so that the second and subsequent wiring layers generally formed of aluminum or the like are provided. Can be used as a power supply line, and the line width of the power supply line can be made narrower than before.
Further, the first wiring layer pattern and the contact can be formed below the power supply line, so that the cell area can be easily reduced. As a result, the power supply line is formed in a higher layer than in the prior art, and in this sense, the degree of freedom of the inter-cell wiring is slightly reduced. However, as described above, in consideration of the fact that the degree of freedom in connection between cells has been greatly increased with the recent increase in the number of wiring layers, the internal signal lines must not be drawn outside the power supply lines. By doing so, the reduction in the degree of freedom in the connection between cells does not cause much problem, and the present invention can provide a great effect that the cell area is reduced by increasing the power supply lines.

From the viewpoint of securing the degree of freedom of connection between cells, it is desirable to use the lower wiring layer as much as possible for the power supply line. However, for example, when cells having the same function are connected continuously. In that case, an external signal line can be wired on the same layer as the power supply line or on the lower layer side. In this case, if the positions of the input / output terminals are determined so that the external signal lines are wired substantially parallel to the power supply lines, the external signal lines can be wired without any problem in the degree of freedom.

In the standard cell according to the present invention, a plurality of basic elements, an internal signal line for connecting the plurality of basic elements inside the cell, and the cells adjacent to each other on one side in one direction are connected to each other. And a power supply line for supplying a power supply voltage to the standard cell, wherein the internal signal line is formed of a wiring layer below the power supply line.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a cell-based semiconductor device and a standard cell according to the present invention will be described in detail with reference to the drawings. 1 and 2 show the cell base A
A unit cell (standard cell) according to the present embodiment, which is used for SIC design and registered in a library in advance
FIG. The standard cell of the present invention is characterized by this pattern diagram, and the cell-based semiconductor device of the present invention has a desired circuit function block by arbitrarily combining cells of different types as exemplified in this pattern diagram. It is configured. Therefore,
In the following description, an embodiment of the present invention will be described by describing the cell patterns of FIGS. 1 and 2 showing the main parts of the present invention.

FIG. 1 shows a two-input NAND cell in a cell-based ASIC of the present invention, and corresponds to FIG. 3 showing a conventional example. FIG. 2 shows a cell-based ASIC of the present invention.
FIG. 4 shows a three-input NOR cell in FIG.
And corresponding. Here, the same components as those of the conventional cells shown in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. 1 and 2, reference numeral 1 denotes a PMOS,
2 is an NMOS, 3 is a p-type active region, 4 is an n-type active region, 5 is a gate electrode, 6 is a drain region (p ⁺ impurity diffusion region) of PMOS 1, and 7 is a source region (p ⁺ impurity diffusion region) of PMOS 1. ), 8 is the drain region (n ⁺ impurity diffusion region) of NMOS 2, 9 is the source region (n ⁺ impurity diffusion region) of NMOS ² , 10 is the internal signal line, 11 is the power supply voltage supply line, and 12 is the GND line (the present invention). Here, patterns 11 and 12 are collectively referred to as power supply lines). Also,
Reference symbol T _IN indicates an input terminal, T _OUT indicates an output terminal, and 1 CNT indicates a first contact (a connection hole between the first wiring layer and the source region 7 or the drain region 8).

The difference between the cell of the present embodiment and the conventional cell shown in FIGS. 3 and 4 is that, first, the power supply voltage supply line 11 and the GND line 12 are connected to a second wiring layer (hereinafter referred to as a second wiring layer). (Referred to as a wiring layer). In a specific example, for example, the first Al wiring layer (1AL) is selected as the second wiring layer. By forming the power supply lines 11, 12 from the second wiring layer, the power supply lines 11, 1
Each of the widths 2 is as thin as 40% of the conventional one in this case. Note that the wiring width of the power supply lines 11 and 12 is
As in the related art, the types of cells are unified between different types of cells (in this example, between the NAND cell of FIG. 1 and the NOR cell of FIG. 2).

Second, the power supply lines 11 and 12 are formed by using a wiring layer on the upper layer side than the conventional one, so that the transistor 1
Alternatively, the contact structure for supplying the power supply voltage to the power supply 2 is different from the conventional structure. That is, a contact pad layer 13 made of, for example, a second polysilicon film is arranged on an insulating layer (not shown) on the source region 7 of the PMOS 1, and this is
The source region 7 is connected via the CNT. The contact pad layer 13 is connected to the power supply line 11 on the upper layer side via a second contact (2CNT) formed on an insulating layer (not shown) formed thereon. Similarly, on the NMOS 2 side, the source region 9 and the GND line 1
2, a contact pad layer 13 is interposed via an insulating layer, and the contact pad layer 13
1 is connected to the lower source region 9 via CNT,
It is connected to the upper GND line 12 via the CNT. In FIG. 2, the symbol SCNT is 1CNT and 2CN.
An example of a stack contact where T is stacked with the contact pad layer 13 interposed therebetween is shown.

Third, since the power supply line is conventionally formed of the lowermost wiring layer, the area under the power supply line cannot be effectively used. However, in the present invention, the power supply line is divided into two layers. By using the wiring layers subsequent to the first layer, the lower layer side region can be effectively used. That is, in the conventional FIGS. 3 and 4, in order to secure a distance from the internal signal line 10 of the same level,
(2CN) that could only be placed inside
T, SCNT) are located immediately below the power supply lines 11 and 12 in the present embodiment. The internal signal line 10 is connected to the power line 1
Wiring can also be performed immediately below 1, 12.

Although not particularly shown, the standard cells thus configured form a circuit functional block by combining a large number and types based on customer specifications at the time of arrangement and wiring, as in the conventional case. Input terminal T
_{The IN} / output terminal T _OUT is optimally connected using a second-layer Al wiring (2AL), a third-layer Al wiring (3AL),. The power supply lines 11 and 12 connected in series in the cell row at the time of arranging the cells are lifted up to the upper layer side by a contact plug or a contact pad layer, shared by the upper wiring layer, and led out. .

In the cell-based ASIC and the standard cell of this embodiment, the power supply lines 11 and 12 are connected to the internal signal line 1.
0, the line width can be reduced without changing the volume resistivity of the power supply lines 11 and 12 (or while lowering the volume resistivity).
Internal signal lines 10 can be wired below 1, 12;
As a result, the entire cell area can be reduced as compared with the related art. For example, in the examples of FIG. 1 and FIG. 2, the line width of the power supply lines 11 and 12 is 60% of the conventional one, and the distance from the internal signal line 10 is 40 to 50% of the conventional one. The cell area is reduced by about 20%. In this cell structure, the power supply lines 11, 12 and the internal signal line 10 can be overlapped, and the width of the power supply lines 11, 12 can be further reduced depending on the thickness of 1AL. In this case, 30 to 50% Further area reduction is also possible.

In the above description, the power supply lines 11 and 12 are
The present invention is not limited to the case where the first wiring layer is used, but the present invention is not limited to this. The power supply line uses a wiring layer above the internal signal line, and the signal line wiring above the power supply line. The layer is required to be an external signal line, that is, a signal line that can be automatically wired. Therefore, an external signal line may be provided on the same layer as the power supply line or on the lower layer side. In this case, from the viewpoint of securing the degree of freedom of wiring, it is preferable that the external signal line be wired substantially in parallel with the power supply line.
The external signal line is connected to the power supply line 1 when, for example, cells having the same function are continuously connected.
Similarly to 1 and 12, the signal line lead-out position and the line width may be determined in advance, and the input terminal T _IN may be automatically connected to the output terminal T _OUT of the adjacent cell only by arranging the cell. . Of course, the external signal line on the same layer or lower layer as the power supply line is not formed in advance in the cell, but may be wired at the time of automatic wiring.

[0025]

As described above, according to the cell-based semiconductor device and the standard cell according to the present invention, it is possible to reduce the cell area while securing a certain degree of freedom in connecting signal lines between cells. it can. Further, the resistance of the power supply line can be reduced, and the voltage drop can be reduced.
Further, the region on the lower layer side of the wiring layer can be effectively used. That is, in addition to being used for area reduction, for example, as shown in the present embodiment, it is also possible to reduce the resistance of the lead wiring of the gate electrode or to provide a contact directly below the power supply line.

[Brief description of the drawings]

FIG. 1 is a pattern diagram showing a NAND cell according to an embodiment of the present invention.

FIG. 2 is a pattern diagram showing a NOR cell according to an embodiment of the present invention.

FIG. 3 is a pattern diagram showing a conventional NAND cell.

FIG. 4 is a pattern diagram showing a conventional NOR cell.

[Explanation of symbols]

1 ... PMOS, 2 ... NMOS, 3 ... p-type impurity region, 4
... n-type impurity region, 5 ... gate electrode, 6, 8 ... drain region, 7, 9 ... source region, 10 ... internal signal line, 11 ...
Power supply voltage supply line (power supply line), 12 GND line (power supply line), 13 contact pad layer, T _IN ... input terminal, T
_OUT ... output terminal, 1CNT, 2CNT, SCNT ... contact.

Claims (5)

[Claims] 1. A cell-based semiconductor device in which a desired circuit function block is formed by arbitrarily combining a plurality of types of cells in which at least a predetermined basic element is formed in advance. A basic element, an internal signal line connecting the plurality of basic elements inside the cell, and a power supply line interconnected between cells adjacent on both sides in one direction and supplying a power supply voltage to the basic element. The internal signal line is formed of a wiring layer below the power supply line, and the signal wiring layer stacked on the upper side of the power supply line is an external signal for connecting input / output terminals of different cells. A cell-based semiconductor device constituting a line. 2. The semiconductor device according to claim 1, further comprising the external signal line formed of a wiring layer of the same hierarchy as the power supply line, wherein the external signal line is wired substantially in parallel with the power supply line.
3. The cell-based semiconductor device according to 1. 3. The external signal line further comprising a wiring layer below the power supply line, wherein the external signal line is wired substantially parallel to the power supply line.
3. The cell-based semiconductor device according to 1. 4. The cell-based semiconductor device according to claim 1, wherein said power supply line is formed of a film having a lower resistance than said internal signal line. 5. At least a plurality of basic elements, an internal signal line connecting the plurality of basic elements in a cell, and a cell connected to cells adjacent on both sides in one direction, wherein a power supply voltage is applied to the basic element. A standard cell having a power supply line to be supplied, wherein the internal signal line is formed of a wiring layer lower than the power supply line.