JPH0537338A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent a rush current generated in an output and a through- current flowing through a buffer circuit. CONSTITUTION:The output circuit is constituted of a buffer circuit 60, a P channel side pre-buffer circuit 40 connected to a, P channel input of the buffer circuit 60, and an N channel side pre-buffer circuit 50 connected to an N channel input of the buffer circuit 60. The P channel side pre-buffer circuit 40 is provided with a MOS transistor 43 for repeating turn-on and turn-off by a clock signal phi so that a fall of the potential of an output signal Sp becomes stepwise. The N channel side pre-buffer circuit 50 is provided with a MOS transistor 51 for repeating turn-on and turn-off by the clock signal so that a rise of the potential of an output signal Sn becomes stepwise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an output circuit for outputting an internal signal to the outside of the integrated circuit.

[0002]

2. Description of the Related Art A large current drive capability is required because a large number of logic gates are connected to the output of an integrated circuit. Since the logic gate inside the integrated circuit has a small current drive capability,
The output signal of the logic gate is output to the output terminal of the integrated circuit through a buffer circuit that increases the current drive capability.

When the channel width of a MOS transistor forming a logic gate is W and the channel length is L, the value of W / L is small, and therefore the ON resistance of the logic gate is large. Further, the MOS transistor forming the buffer circuit has a large W / L value and thus has a large gate capacitance. Therefore, it takes time to charge and discharge the gate input capacitance of the buffer circuit.

In order to shorten the charge / discharge time, a pre-buffer circuit using a MOS transistor having a larger W / L value than the logic gate and a smaller W / L value than the buffer circuit is a logic gate and a buffer circuit. It is provided between.

In this case, since the gate capacitance of the MOS transistor of the pre-buffer circuit is smaller than that of the buffer circuit, the gate capacitor of the buffer circuit is charged and discharged in the time required for the gate capacitance to be charged and discharged. It will be shorter than the time it takes. Further, the MOS transistor of the pre-buffer circuit that drives the buffer circuit is M which is used for the logic gate.
Since the on resistance is smaller than that of the OS transistor, the charge and discharge time for the gate capacitance of the buffer circuit is shortened. Therefore, by providing the pre-buffer circuit between the logic gate and the buffer circuit, the AC characteristics from the logic gate output to the integrated circuit output are improved.

Conventionally, the rise time and fall time of the output of the pre-buffer circuit are the rise time and fall time of the input of the pre-buffer circuit and the ON resistance of the MOS transistor forming the pre-buffer circuit and the MOS transistor forming the buffer circuit. It is set by the gate capacitance of.

FIG. 5 shows a conventional output circuit provided in an integrated circuit, and FIG. 6 is a timing chart showing its operation. The pre-buffer circuit 10 includes a P channel MOS transistor 11 and an N channel MOS transistor.
Composed of 12. The source of the transistor 11 is the power supply VD
Connected to D, the source of transistor 12 is grounded. The drains of the transistors 11 and 12 are connected to the node b1. Further, the gates of the transistors 11 and 12 are connected to the node a1, and the node a1
The output signal Sa of the logic gate 13 is input to.

The buffer circuit 14 comprises a P channel MOS transistor 15 and an N channel MOS transistor 16. The source of the transistor 15 is connected to the power supply VDD, and the source of the transistor 16 is grounded. The drains of transistors 15 and 16 are connected to node Z1 and
The external terminal 17 is pulled out from. Then, one end of the external load capacitance CL is connected to the terminal 17, and the other end of the capacitance CL is grounded. The gates of the transistors 15 and 16 are connected to the node b2, and the node b2 is connected to the node b1 of the prebuffer circuit 10.

As shown in FIG. 6, the output signal Sa of the logic gate 13 rises from the GND level, and the prebuffer circuit 10
When the threshold voltage Vth1 is exceeded, the transistor 11 turns off and the transistor 12 turns on. Therefore, the charges previously charged in the gate capacitance Cb of the buffer circuit 14 are discharged through the transistor 12, and the potential of the output signal Sb of the prebuffer circuit 10 starts to drop from the power supply voltage VDD level toward the GND level.

When the potential of the signal Sb falls below the threshold voltage Vth2 of the buffer circuit 14, the transistor 15 in the buffer circuit 14 turns on and the transistor 16 turns off. Therefore, the external load capacitance CL is charged through the transistor 15 and the output signal of the buffer circuit 14 is
The potential of SZ starts to rise from the GND level to the power supply voltage VDD level.

The rise time and fall time of the signal Sb are the rise time and fall time of the signal Sa and the buffer circuit.
When the gate capacitances Cb and Sa of 14 rise, the transistor
It is determined by the source-drain resistance of 12 and the source-drain resistance of the transistor 11 when Sa falls.

If the rising time and the falling time of the signal Sb are short, the time for the signal Sb which is the input of the buffer circuit 14 to reach the threshold voltage Vth2 of the buffer circuit 14 becomes short, and the signal Sb even after reaching the threshold voltage Vth2. Since the voltage change of Sb is rapid, the drain current of the transistor 16 flows sharply when the signal Sb rises, and the drain current of the transistor 15 flows sharply when the signal Sb falls.

Therefore, a large current flows in the buffer circuit 14 in a short time, and the charging / discharging current I of the external load capacitance CL causes an overshoot phenomenon and an undershoot phenomenon due to the rush current as shown in the waveform of FIG. As a result, there is a problem that the power supply voltage VDD fluctuates, and a malfunction or a latch-up phenomenon is induced in the logic gate connected to the power supply voltage VDD and the ground.

Therefore, conventionally, as shown in FIG. 7, W / of MOS transistors 21 and 22 used in the pre-buffer circuit 20 is used.
The value of L is made small so that the rising time and the falling time of the signal Sb become long. The other circuit configuration is the same as that of FIG.

As a result, the change time of the transistors 15 and 16 of the buffer circuit 14 from the off state to the on state becomes long, and the voltage change of the signal SZ also becomes gentle as shown in FIG. Therefore, the charge / discharge current I of the external load capacitance CL has no rush current.

[0016]

Conventionally, the W / L value of a MOS transistor forming a pre-buffer circuit is made small, and the change time of the MOS transistor forming a buffer circuit from an off state to an on state is lengthened. Due to
It was preventing rush current.

However, when the power supply voltage increases, the rise time and fall time of the pre-buffer circuit output are shortened, and the rush current increases in the buffer circuit output, which is ineffective.

On the other hand, the change time from the OFF state to the ON state of the transistor in the buffer circuit is lengthened, but the change time from the ON state to the OFF state is also lengthened, and the P-channel MOS transistor of the buffer circuit is also increased. , N-channel MOS transistors are simultaneously turned on for a long time, and the through current increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to prevent the rush current of the buffer circuit output even when the power supply voltage is high, and to reduce the through current flowing through the buffer circuit. It is to provide an output circuit capable of

[0020]

The output circuit of the present invention comprises:
A first channel type first, in which a source and a drain are inserted in series between a first potential supply terminal and a first node, and a clock signal and an input signal are respectively supplied to a gate,
A second channel in which the second MOS transistor and the source / drain are inserted in series between the second potential supply terminal and the first node, and the gate is supplied with the clock signal and the input signal, respectively. Type 3rd and 4th MO
A pre-buffer circuit including an S-transistor and a source / drain are inserted between the first potential supply terminal and the second node, and a gate is supplied with the signal of the first node. A channel-type fifth MOS transistor and a second channel in which a source-drain gap is inserted between the second potential supply end and the second node, and a gate is supplied with the signal of the first node. Type sixth MOS
A buffer circuit including a transistor is provided.

Further, in the output circuit of the present invention, the source-drain is inserted between the first potential supply terminal and the first node, and the input signal is supplied to the gate of the first channel type first circuit. A second channel-type second transistor in which a MOS transistor and a source / drain are inserted in series between the first node and a second potential supply terminal, and a clock signal and the input signal are respectively supplied to a gate. , The third MOS
A first pre-buffer circuit including a transistor and a source / drain are serially inserted between the first potential supply terminal and a second node, and the gate receives the clock signal and the input signal, respectively. The supplied first channel type fourth and fifth MOS transistors and the source-drain are inserted between the second node and the second potential supply terminal, and the gate is supplied with the input signal. A second pre-buffer circuit composed of a second channel type sixth MOS transistor, and a source / drain between the first potential supply terminal and the third node, and a gate above the The seventh MOS transistor of the first channel type to which the signal of the first node is supplied and the source-drain are inserted between the second potential supply terminal and the third node, and the gate is inserted. Characterized by comprising a buffer circuit comprising a eighth MOS transistor of the second channel type having a signal of the second node is supplied.

[0022]

According to the present invention, since the input signal to the buffer circuit is applied stepwise by the action of the clock-controlled transistor, the amount of change per unit time of the current appearing in the output signal of the buffer circuit is small and the power supply fluctuation. Can be suppressed.

According to the present invention, the pre-buffer circuit has two
By providing one, the timing when the P-channel MOS transistor and the N-channel MOS transistor of the buffer circuit are turned on from the time when they are turned off from the time when they are turned on,
The P-channel and N-channel are not turned on at the same time, which prevents the generation of a through current from the power supply of the buffer circuit to the ground.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings with reference to the drawings. FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention.
MOS transistors controlled by a clock signal for controlling the fall time are provided on the P-channel side and the N-channel side, respectively.

The prebuffer circuit 30 includes two P-channel M
It is composed of OS transistors 31, 32 and two N-channel MOS transistors 33, 34, and is a P-channel MOS transistor.
The source of the transistor 31 is connected to the power supply voltage VDD,
The drain is connected to the source of the P-channel MOS transistor 32. Also, the drain of the transistor 32 is a node
Connected to b3.

The drain of N channel MOS transistor 33 is connected to node b3, and the source is connected to the drain of N channel MOS transistor 34. The source of the transistor 34 is grounded.

The clock signal Φ is input to the gates of the transistors 31 and 34. The gates of the transistors 32 and 33 are both connected to the node a2, and the output signal Sa of the logic gate 13 is input to the node a2.

The buffer circuit 14 comprises a P channel MOS transistor 15 and an N channel MOS transistor 16. The source of the transistor 15 is connected to the power supply VDD, and the drain is connected to the node Z1. The drain of the transistor 16 is connected to the node Z1 and the source is grounded. One end of the external load capacitance CL is connected to the external terminal 17 drawn out from the node Z1, and the other end of the capacitance CL is grounded. The gates of the transistors 15 and 16 are both connected to the node b1, and the node b1 is connected to the node b3.

Next, the operation of the circuit of the above embodiment will be described with reference to the timing chart of FIG. First, when the potential of the signal Sa rises from the GND level and reaches the threshold voltage Vth5 of the pre-buffer circuit 30, the P-channel MO
The S transistor 32 turns off and the N channel MOS transistor 33 turns on.

The N-channel MOS transistor 34 is turned on when the clock signal Φ applied to the gate is at the VDD level and turned off when it is at the GND level, and is repeatedly turned on and off in accordance with the clock signal Φ.

Only when the N-channel MOS transistor 34 is on, the charge charged in the gate capacitance Cb of the buffer circuit 14 is discharged through the N-channel MOS transistors 33 and 34, so that the signal appearing at the node b3.
The potential of Sb drops stepwise from the VDD level.

The potential of the signal Sb falls and the buffer circuit 14
When the threshold voltage Vth6 is reached, the P-channel MOS transistor 15 turns on and the N-channel MOS transistor 16 turns off. Therefore, P is added to the external load capacitance CL.
Power supply voltage VDD through channel MOS transistor 15
Is added and the capacitance CL is charged.

The voltage of the signal SZ appearing at the node Z1 rises from the GND level as the external load capacitance CL is charged by the charge current I generated by the power supply voltage VDD. At this time, the potential of the signal Sb applied to the gate of the P-channel MOS transistor 15 decreases stepwise, so P
The on resistance of the channel MOS transistor 15 gradually decreases. Therefore, the charge current I flowing through the P-channel MOS transistor 15 does not suddenly flow and no rush current occurs.

Further, even when the power supply voltage VDD becomes high, the clock signal Φ remains at the G level even when the transistor 33 is in the on-state even when the signal Sb applied to the input of the buffer circuit 14 falls.
Since the potential of the signal Sb does not change during the ND level, it does not become extremely short. Therefore, the charge current I output from the buffer circuit 14 does not suddenly flow, and the power supply voltage VDD does not greatly change.
It is possible to prevent the malfunction of other elements sharing the power supply.

Next, the potential of the signal Sa falls from the VDD level and the threshold voltage of the pre-buffer circuit 30.
When Vth5 is reached, the transistor 32 turns on and the transistor
33 turns off. The transistor 31 is turned off when the clock signal Φ applied to the gate is at the VDD level, GND
When it is at the level, it is turned on and repeatedly turned on and off by the clock signal Φ.

Since the gate capacitance Cb of the buffer circuit 14 is charged by the power supply voltage VDD through the transistors 31 and 32 only when the transistor 31 is on, the node b3
The potential of the signal Sb appearing at the stepwise rises from the GND level.

When the potential of the signal Sb rises from the GND level and reaches the threshold voltage Vth6 of the buffer circuit 14, the N channel MOS transistor 16 turns on and the P channel MOS transistor 15 turns off. Therefore,
The charges previously charged in the external load capacitance CL are discharged through the transistor 16, and the potential of the signal SZ appearing at the node Z1 falls from the VDD level.

At this time, since the potential of the signal Sb applied to the gate of the transistor 16 rises stepwise, the transistor 16
ON resistance of is gradually decreased. Therefore, the transistor 16
The discharge current I flowing through does not flow rapidly, and no rush current occurs.

Even if the power supply voltage VDD rises, the rise time of the signal Sb applied to the input of the buffer circuit 14 is such that the clock signal Φ is VD even when the transistor 32 is in the ON state.
Since the potential of the signal Sb does not change during the D level, it does not become extremely short. Therefore, the discharge current I that the buffer circuit 14 sinks does not suddenly flow, and the power supply voltage VDD does not greatly change.
It is possible to prevent the malfunction of other elements sharing the power supply.

Next, a second embodiment will be described with reference to FIG. In this second embodiment, two prebuffer circuits, that is, a P channel side prebuffer circuit 40 and an N channel side prebuffer circuit 50 are provided.

The P-channel side pre-buffer circuit 40 includes one P-channel MOS transistor 41 and two N-channel M transistors.
It is composed of OS transistors 42 and 43. The drain of the transistor 41 is connected to the node p1 and the source is connected to the power supply VDD. The drain of the transistor 42 is connected to the node p1 and the source is connected to the drain of the transistor 43. The source of the transistor 43 is grounded.

The gates of the transistors 41 and 42 are both connected to the node a3, and the node a3 has a logic gate.
The 13 output signals Sa are input. The clock signal Φ is input to the gate of the transistor 43.

The N-channel side pre-buffer circuit 50 is composed of two P-channel MOS transistors 51 and 52 and one N-channel MOS transistor 53. The drain of the transistor 51 is connected to the source of the transistor 52, and the source is connected to the power supply VDD. Transistor 52
Is connected to the node n1, and the drain of the transistor 53 is connected to the node n1. Also transistors
The 53 source is grounded.

The gates of the transistors 52 and 53 are both connected to the node a4, and the output signal Sa of the logic gate 13 is input to the node a4. Further, the clock signal Φ is input to the gate of the transistor 51.

The buffer circuit 60 comprises a P channel MOS transistor 61 and an N channel MOS transistor 62. The source of the transistor 61 is connected to the power supply VDD and the drain is connected to the node Z2. Transistor 62
Has its drain connected to node Z2 and its source grounded. The node Z2 is connected to the external terminal 17, one end of the external load capacitance CL is connected to the terminal 17, and the other end of the capacitance CL is grounded.

The gate of the P-channel MOS transistor 61 is connected to the node p1 of the pre-buffer circuit 40 on the P-channel side. The gate of the N-channel MOS transistor 62 is N
It is connected to the node n1 of the pre-buffer circuit 50 on the channel side.

Next, the operation of the circuit of the second embodiment will be described with reference to the timing chart shown in FIG. First, when the signal Sa falls from the power supply voltage VDD level and reaches the threshold voltage Vth7 of the pre-buffer circuit 40, the transistor 41 is turned on and the transistor 42 is turned off.

Through this transistor 41, the power supply VDD
As the gate of the transistor 61 of the buffer circuit 60 is charged by, the signal Sp appearing at the node p1 becomes G
Stand up from the ND level. When the potential of the signal Sp exceeds the threshold voltage Vth8 of the transistor 61, the transistor 61 that was on turns off.

On the other hand, the signal Sa falls from the power supply potential VDD, and the threshold voltage Vt of the prebuffer circuit 50 is increased.
When h7 is reached, transistor 52 turns on and transistor 52
53 turns off. Further, the transistor 51 is turned on when the clock signal Φ applied to the gate is at the GND level.

When the clock signal Φ is at the GND level and the transistors 51 and 52 are both on, the power supply VDD charges the gate of the transistor 62 of the buffer circuit 60,
The potential of the signal Sn appearing at the node n1 rises. Transistor 51 is turned on by clock signal Φ,
Because it turns off repeatedly, it becomes a step.

The potential of the signal Sn rises, and the transistor 62
When the threshold value vth9 is exceeded, the transistor 62 is turned on. Since the electric charge previously charged in the external load capacitance CL is discharged through the channel of the transistor 62, the potential of the signal SZ appearing at the node Z2 decreases.

Since the signal Sn raises the potential stepwise,
The on resistance of the transistor 62 controlled by the signal Sn gradually decreases. For this reason, the discharge current I passing through the transistor 62 does not suddenly flow, so that no rush current occurs.

Since the potential of the signal Sn rises stepwise, the time when it reaches the threshold voltage is later than that of the signal Sp. Therefore, when the signal Sp first exceeds the threshold voltage Vth8 and the P-channel MOS transistor 61 is turned off, the signal Sn does not reach the threshold voltage Vth9 and the transistor 62 is still off.

Therefore, the buffer circuit 60 receives the input signal S
From the start of p and Sn to the end,
The transistors 61 and 62 are never turned on at the same time. Therefore, the power supply VDD of the buffer circuit 60
No through current flows from the ground to the ground.

Next, when the potential of the signal Sa rises from the GND level and reaches the threshold voltage Vth7 of the pre-buffer circuit 40, the transistor 41 in the P-channel side pre-buffer circuit 40 turns off and the transistor 42 turns on.
Further, the transistor 43 is turned on when the clock signal Φ applied to the gate is at VDD level.

When the clock signal Φ is at the VDD level and the transistors 42 and 43 are both in the ON state, the charges previously charged in the gate of the transistor 61 are the transistors 42 and 43.
Will be discharged through. Therefore, the potential of the signal Sp appearing at the node p1 falls stepwise in accordance with the clock signal Φ, and when the threshold voltage Vth8 of the transistor 61 is reached, the transistor 61 is turned on.

On the other hand, the potential of the signal Sa rises from the GND level and the threshold voltage of the prebuffer circuit 50.
When reaching Vth7, in the N-channel side pre-buffer circuit 50, the transistor 52 is turned off and the transistor 53 is turned on.
Therefore, the charge previously charged in the gate of the transistor 62 is discharged through the transistor 53. Therefore, the potential of the signal Sn appearing at the node n1 is V
When the signal Sn reaches the threshold voltage Vth9 of the transistor 62 after falling from the DD level, the transistor 62
Turns off.

When the transistor 62 is off and the transistor 61 is on, the charge current I from the power supply VDD charges the external load capacitance CL, and the potential of the signal SZ appearing at the node Z2 rises from the GND level.

Since the signal Sp is stepwise lowered by the clock signal Φ, the on-resistance of the transistor 61 controlled by the signal Sp gradually decreases. Therefore, the charge current I passing through the transistor 61 does not suddenly flow, and the rush current does not occur.

Further, since the potential of the signal Sp falls in a stepwise manner, the time to reach the threshold voltage is later than that of the signal Sn. Therefore, when the potential of the signal Sn first exceeds the threshold voltage Vth9 and the transistor 62 is turned off, the potential of the signal Sp does not reach the threshold voltage Vth8, and the transistor 61 is still off.

Therefore, the buffer circuit 60 has the transistor 61 between the start and the end of the falling of the input.
And the transistor 62 are not turned on at the same time,
No through current flows from the power supply VDD of the buffer circuit 60 to the ground.

[0062]

As described above, according to the present invention, since the potential of the input signal to the buffer circuit by the prebuffer circuit is changed stepwise by using the clock signal,
The ON resistance of the buffer circuit also decreases stepwise, and even if the power supply voltage rises, the increase in rush current appearing in the output of the buffer circuit is suppressed, and the power supply fluctuation is suppressed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment circuit shown in FIG.

FIG. 3 is a circuit diagram of an output circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the embodiment circuit shown in FIG.

FIG. 5 is a circuit diagram of a conventional output circuit.

6 is a timing chart showing the operation of the conventional circuit of FIG.

FIG. 7 is a circuit diagram of a conventional output circuit.

8 is a timing chart showing the operation of the conventional circuit of FIG.

[Explanation of symbols]

10, 20, 30, 40, 50 ... Pre-buffer circuit, 13 ... Logic gate, 14, 60 ... Buffer circuit, 17 ... External terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/096 B 6959-5J

Claims (2)

[Claims] 1. A first channel-type first device in which a source / drain is inserted in series between a first potential supply terminal and a first node, and a gate is supplied with a clock signal and an input signal, respectively. , The second MOS transistor and the source
A second channel type third and fourth drains are inserted in series between the second potential supply terminal and the first node, and the gate is supplied with the clock signal and the input signal, respectively. A pre-buffer circuit including a MOS transistor and a source-drain are inserted between the first potential supply terminal and the second node, and a gate is supplied with the signal of the first node. A channel-type fifth MOS transistor and a second channel in which a source-drain gap is inserted between the second potential supply end and the second node, and a gate is supplied with the signal of the first node. A sixth type MOS transistor and a buffer circuit including the sixth type MOS transistor. 2. A first channel-type first MOS transistor and a source / drain in which a source / drain is inserted between a first potential supply end and a first node, and an input signal is supplied to a gate. Second channel type second and third MOS transistors in which a space is inserted in series between the first node and the second potential supply terminal and a gate is supplied with the clock signal and the input signal, respectively. The first consisting of
Channel of the pre-buffer circuit and the source / drain thereof are inserted in series between the first potential supply terminal and the second node, and the gate is supplied with the clock signal and the input signal, respectively. Type fourth and fifth MOS transistors and sources
A second pre-buffer including a second channel type sixth MOS transistor having a drain inserted between the second node and the second potential supply terminal and having the gate supplied with the input signal. A seventh MOS of a first channel type in which a circuit and a source / drain are inserted between the first potential supply terminal and the third node, and the signal of the first node is supplied to the gate. A second channel type eighth MOS transistor in which a transistor and a source / drain are inserted between the second potential supply terminal and the third node, and a signal of the second node is supplied to a gate. And a buffer circuit comprising: