JP2647587B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit,
In particular, logic gate circuits (NOT, AND, OR, NAN)
(D, NOR, etc.) without reducing the switching speed, etc., thereby suppressing fluctuations in the power supply voltage caused when multiple bits are switched at the same time.

[0002]

2. Description of the Related Art For example, NAN constituting a semiconductor integrated circuit
It is desirable that a logic gate circuit such as a D circuit or a NOR circuit operate as small and as fast as possible.
2. Description of the Related Art With the improvement of microfabrication technology and the like, the trend toward multi-bit and high-speed semiconductor integrated circuits in recent years has been increasing.

[0003]

However, as the number of bits and the speed of the semiconductor integrated circuit increase, the problem arises that the power supply voltage fluctuates when a large number of bits are simultaneously switched. In order to solve such a problem, conventionally, since the amplitude of the fluctuation of the power supply voltage is inversely proportional to the rise time and the fall time of the signal, the rise time and the fall time of the transistor in the final output stage are delayed. However, this has the disadvantage that the speed is reduced and the characteristics are deteriorated.

The present invention has been made in view of such an unsolved problem in the prior art, and provides a semiconductor circuit capable of suppressing a fluctuation in power supply voltage without causing a reduction in speed or the like. It is intended to be.

[0005]

In order to achieve the above object, a semiconductor circuit according to the present invention comprises a first circuit in which a self- drain voltage is supplied to a gate between a charging side of a logic gate circuit and a power supply. P-channel MOS transistor and a second P-channel MOS transistor whose gate has the output of the logic gate circuit supplied through an inverter in parallel between the discharge side of the logic gate circuit and ground. , The first N which has its own drain voltage supplied to the gate
A channel MOS transistor, and a second N-channel gate having an output of the logic gate circuit supplied through an inverter.
A channel MOS transistor is interposed in parallel, and the driving power of the first P-channel MOS transistor and the first N-channel MOS transistor is large, and the second P-channel MOS transistor and the second N-channel MOS transistor The driving force of the transistor was reduced.

[0006]

[0007]

When the output of the logic gate circuit rises from "L" to "H", the output side of the logic gate circuit and the power supply are connected and charging is performed. Is still low, the gate voltage of a second P-channel MOS transistor (hereinafter referred to as a PMOS transistor) whose output is supplied via an inverter is at the “H” level, and the second PMOS transistor Since it is in the off state, charging is performed only through the first PMOS transistor.

However, the first PMOS transistor is:
Since the gate is supplied with its own drain voltage, the output of the logic gate circuit is lower than the power supply voltage V _CC by the threshold value V _THP of the first PMOS transistor (V _CC -V _THP ). It can only be charged up to Then, when the output of the logic gate circuit becomes high, the second PM
Since the OS transistor is turned on, the charging side of the logic gate circuit is connected to the power supply via the second PMOS transistor, and when the second PMOS transistor is turned on, the gate voltage of the first PMOS transistor increases. Since the first PMOS transistor is turned off, the output side of the logic gate circuit is charged by the second PMOS transistor.
This is performed only through the MOS transistor.

At this time, the second PMOS transistor is
Since the output of the logic gate circuit is supplied via the inverter, it constitutes a positive feedback circuit, so that it is used in a saturation region, and the output side of the logic gate circuit is charged to the power supply voltage V _CC . On the other hand, when the output of the logic gate circuit falls from "H" to "L", the output side of the logic gate circuit is connected to the ground and discharge occurs, contrary to the rise. When the output of the logic gate circuit is still high, the output is supplied to a second N-channel MOS transistor (hereinafter referred to as N
MOS transistors. Since the gate voltage in ()) is “L” and the second NMOS transistor is in the off state, the discharge is performed only through the first NMOS transistor.

However, the first NMOS transistor has:
The output of the logic gate circuit is discharged only up to the threshold value V _THN of the first NMOS transistor because its own drain voltage is supplied to its gate. And
When the output of the logic gate circuit goes low, the second N
Since the MOS transistor is turned on, the discharge side of the logic gate circuit is connected to the ground via the second NMOS transistor, and when the second NMOS transistor is turned on, the gate voltage of the first NMOS transistor decreases. Since the first NMOS transistor is turned off, the discharge on the output side of the logic gate circuit is performed only through the second NMOS transistor.

At this time, the second NMOS transistor is
Since the output of the logic gate circuit is supplied via the inverter, it constitutes a positive feedback circuit, so that it is used in the saturation region, and the output side of the logic gate circuit drops to the ground level. That is, according to the present invention, when the output of the logic gate circuit rises, first, the first PMOS
_Charged to (V _CC -V _THP ) through the transistor,
Next, while being charged to the power supply voltage V _CC through the second PMOS transistor, when the output of the logic gate circuit falls, first, it is discharged to V _THN through the first NMOS transistor, and then, It is discharged to the ground level via the second NMOS transistor.

The driving power of the first PMOS transistor and the second NMOS transistor is increased (for example, the first PMOS transistor and the first NMOS transistor).
The ratio of the channel width W and the channel length L of the transistor W /
L is increased), and the second PMOS transistor and the second
Of the NMOS transistor (for example, the ratio W / L of the channel width W and the channel length L of the second PMOS transistor and the second NMOS transistor is reduced). Charge and discharge are performed at high speed until the second PMOS transistor or the second NMOS transistor is turned on, and at low speed after the second PMOS transistor or the second NMOS transistor is turned on. Charging and discharging will be performed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention, in which a semiconductor circuit according to the present invention is applied to a signal output device 1 of a semiconductor integrated circuit. First, the configuration will be described. This signal output device 1 has a CMOS inverter 2 as a logic gate circuit, and the input side of the CMOS inverter 2 is connected to a signal output line 3 of a semiconductor integrated circuit. The side is connected to the output pad 4.

And a source of a PMOS transistor P ₀ as a charging side constituting the CMOS inverter 2;
A first PMOS transistor P ₁ and a second PMOS transistor P ₂ intervene in parallel between the power supply V _CC and C
NMOS as discharge side constituting MOS inverter 2
A first NMOS transistor N ₁ and a second NMOS transistor N ₂ are provided in parallel between the source of the transistor N ₀ and the ground GND.

The gate of the first PMOS transistor P ₁ is supplied with the drain voltage of the first PMOS transistor P _{1, and} the gate of the second PMOS transistor P _{2 is connected to} the gate of the CMOS inverter 2. The output is supplied via an inverter 5 having a small driving force. The gate of the first NMOS transistor N ₁ has the first N
MOS drain voltage of the transistor N ₁ is supplied to the second gate of the NMOS transistor N _2, CMOS
The output of the inverter 2 is supplied via an inverter 6 having a small driving force.

Then, the first PMOS transistor P ₁
Further, the first NMOS transistor N ₁ is a transistor having a large ratio (large driving force) W / L of the channel width W and the channel length L, and the second PMOS transistor P _{2 and} the second PMOS transistor P ₂ Is a transistor having a small ratio (low driving force) W / L of the channel width W and the channel length L.

Next, the operation of this embodiment will be described. FIG.
(A) to (f) are waveform diagrams respectively showing waveforms at points a to f in FIG. 1, where point a is the input side of the CMOS inverter 2, point b is the output side of the CMOS inverter 2, and point c is output side, d point of the inverter 5 is the output side, e point of the inverter 6 is the drain side, f point of the first PMOS transistor P ₁ represents the first drain of the NMOS transistor N _1.

That is, when the input to the CMOS inverter 2 starts rising at time t ₁ (see FIG. 2A), the PMOS transistor P ₀ shifts from the on state to the off state, and the NMOS transistor N ₀ turns off. To ON state. At this time, the first NMOS transistor N ₁ is in the ON state because the potential on its own drain side is supplied to the gate, and the output of the CMOS inverter 2 is connected to the gate of the _second NMOS transistor N _2. Since it is supplied via the inverter 6, it is in the off state.

Therefore, the electric charge accumulated on the output side of the CMOS inverter 2 is supplied to the ground GND through the NMOS transistor N ₀ and the first NMOS transistor N _1.
Although is discharged to the side, a first NMOS transistor N ₁ is for a large transistor driving force, the output side potential of the CMOS inverter 2 drops relatively steeply (Fig. 2
(B)).

[0020] However, the drain side of the potential of the first NMOS transistor N ₁ at this time, since the first voltage drop at the NMOS transistor N ₁ is generated, by the amount of the threshold V _THN of the NMOS transistor N ₁ , And a potential higher than the ground GND level (see FIG. 2F).
Therefore, the potential on the output side of the CMOS inverter 2 drops sharply until the threshold value V _THN is reached (until the time t ₂ is reached) (see FIG. 2B). .

On the other hand, when the potential on the output side of the CMOS inverter 2 drops, the output of the inverter 6 rises, so that the gate voltage of the _second NMOS transistor N2 increases (see FIG. 2 (d)). NMOS transistor N ₂ is shifted from the oFF state to the oN state of the first N
MOS drain voltage of the transistor N ₁ falls (FIG. 2 (f) refer) is, the first NMOS transistor N ₁
As the drain voltage drops, the potential on the output side of the CMOS inverter 2 further drops, and then the output of the inverter 6 further rises, so that a positive feedback is formed. As a result, the drain voltage of the _first NMOS transistor N ₁ is eventually formed. Is ground G
The voltage drops to the ND level (see FIG. 2F), and the potential on the output side of the CMOS inverter 2 also drops to the ground GND level (see FIG. 2B).

Then, the first NMOS transistor N ₁
When the drain voltage of the drops, to shift to the OFF state from the first NMOS transistor N ₁ is turned on,
The output side of the discharge of the CMOS inverter 2 between time t ₂ of t _3, since will be effected only through the NMOS transistor N ₂ smaller second driving force, becomes relatively gentle (FIG. 2 ( b)).

Also, as with the inverter 6, the inverter 5
2 rises (see FIG. 2C), the second PMOS transistor P ₂ whose output is supplied to the gate of the inverter 5 shifts from the on state to the off state, and thereby the first PMOS transistor P ₂ since P ₁ is changed from the oFF state to the oN state, the potential of the first drain side of the PMOS transistor P ₁ becomes a low value by the threshold V _THP of the PMOS transistors P ₁ than the power supply V _CC level (Fig. 2 (e)).

From this state, when the input to the CMOS inverter 2 starts falling at time t ₄ (see FIG. 2A), the PMOS transistor P ₀ shifts from the off state to the on state. Then, the NMOS transistor N ₀ shifts from the on state to the off state. At this time, the first PMOS transistor P ₁ is, self-Dore
Since the in- side potential is supplied to the gate, the second PMOS transistor P ₂ is in the on state, and the output of the CMOS inverter 2 is supplied to the gate of the second PMOS transistor P ₂ via the inverter 5. is there.

Accordingly, the output side of the CMOS inverter 2 is charged through the first PMOS transistor P ₁ and the PMOS transistor P _0. However, since the first PMOS transistor P ₁ is a transistor having a large driving force, the CMOS inverter 2 is charged. The potential on the output side of No. 2 rises relatively steeply (see FIG. 2B). However, at this time the first
The drain-side potential of the PMOS transistor P _1, as described above, the threshold value V of the PMOS transistor N _1
The potential is lower than the power supply V _CC level by _THP (see FIG. 2E).

Therefore, the potential on the output side of the CMOS inverter 2 sharply rises until the threshold value V _THP is reached (until time t ₅ is reached) (FIG. 2 (b)). )reference). On the other hand, when the potential on the output side of the CMOS inverter 2 rises, the output of the inverter 5 falls, so that the gate voltage of the _second PMOS transistor P2 decreases (see FIG. 2 (c)). transistor P ₂ is shifted from the oFF state to the oN state, the first drain voltage of the PMOS transistor P ₁ is increased (see FIG. 2 (e)) is, the first PMOS transistor P
With increasing _first drain voltage further increases the output side potential of the CMOS inverter 2, a result from the output of the inverter 5 to form a positive feedback that further drops, eventually, of the first PMOS transistor P ₁ The drain voltage rises to the power supply V _CC level (see FIG. 2 (f)), and the CMO
The potential on the output side of the S inverter 2 also rises to the power supply V _CC level (see FIG. 2B).

Then, the first PMOS transistor P ₁
When the drain voltage of the increases, since the first PMOS transistor P ₁ that is the transition from the ON state to the OFF state,
Charging of the output side of the CMOS inverter 2 between t ₆ from the time t _5, since will be effected only through the PMOS transistor P ₂ smaller second driving force, becomes relatively gentle (FIG. 2 ( b)).

Further, similarly to the inverter 5, the inverter 6
The output also rises because (see FIG. 2 (d) see), the second NMOS transistor N ₂ which output is supplied to the gate of the inverter 6, shifts from the ON state to the OFF state, whereby the first NMOS transistor since N ₁ is shifted from the oFF state to the oN state, the potential of the first drain of the NMOS transistor N ₁ is the threshold V _THN (see FIG. 2 (f)).

That is, the output of the CMOS inverter 2 is
As is clear from the waveform diagram of FIG. 2 (b), at the time of the fall and the rise, the period (t ₁ → t ₂ , t ₄ → t ₅ ) that changes relatively steeply, and the time is relatively gentle. After a period of change (t ₂ → t ₃ , t ₅ → t ₆ ),
Eventually, it reaches the power supply V _CC level or the ground GND level.

[0030] Then, the output voltage of the CMOS inverter 2, because they reached approximately the power supply V _CC level or ground GND level at the end of the steeply varying period, no hindrance to the driving of the next-stage logic circuit Therefore, the high speed operation of the CMOS inverter 2 is achieved, and the potential is settled to the final potential after a period of gradual change.
The switching of the OS inverter 2 hardly affects the power supply voltage of the power supply line or the ground line.

For this reason, even if a large number of bits are switched at the same time, the fluctuation of the power supply voltage can be extremely small, and the malfunction of the logic circuit due to the fluctuation of the power supply voltage can be prevented. The output device 1 is suitable as a signal output device of a recent semiconductor integrated circuit in which multi-bit operation and high-speed operation are achieved. CMOS inverter 2
Finally settles at the power supply V _CC level or the ground GND level, so that a large through current does not flow even if the next-stage logic circuit is configured by CMOS logic.

FIG. 3 is a view showing a second embodiment of the present invention, in which the present invention is applied to a two-input NAND circuit 7 as a logic gate circuit. The same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals. That is, this NA
The ND circuit 7 has two Ps arranged in parallel on the power supply V _CC side.
It comprises MOS transistors P ₃ and P ₄ and two NMOS transistors N ₃ and N ₄ arranged in series on the ground GND side. One input A is a PMOS transistor P ₃ and an NMOS transistor N ₃ And the other input B is supplied to the gates of a PMOS transistor P ₄ and an NMOS transistor N ₄ ,
The drain side of the MOS transistor P ₃ is an output F.

The first PMOS transistor P ₁ and the second PMOS transistor P ₁ are connected between the sources of the PMOS transistors P ₃ and P ₄ as the charging side of the NAND circuit 7 and the power supply V _CC.
A MOS transistor P ₂ is provided, and a first NMOS transistor N ₁ and a second NMOS transistor N ₂ are provided between the source of the NMOS transistor N ₄ as the discharge side of the NAND circuit 7 and the ground GND. ing. Other configurations are the same as in the first embodiment.

With such a configuration, the output F of the NAND circuit 7 changes relatively steeply and changes relatively slowly when the output F of the NAND circuit 7 changes by the same operation as in the first embodiment. After the period, the power supply voltage finally reaches the power supply V _CC level or the ground GND level, so that high-speed operation can be achieved and fluctuations in the power supply voltage can be suppressed as in the first embodiment.

In each of the above embodiments, the case where the semiconductor circuit according to the present invention is applied to the CMOS inverter 2 or the NAND circuit 7 as a logic gate circuit is shown.
The application of the present invention is not limited to these,
Other logic gate circuits, for example, an OR circuit, an AND circuit, a NOR circuit, and the like may be used.

[0036]

As described above, according to the present invention,
When the output of the logic gate circuit changes, the final level is reached through a period in which the output changes relatively steeply and a period in which the output changes relatively slowly. Is achieved, the fluctuation of the power supply voltage can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a waveform chart showing waveforms at points a to f of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 signal output device (semiconductor circuit) 2 CMOS inverter (logic gate circuit) 5, 6 inverter 7 NAND circuit (logic gate circuit) P ₁ first PMOS transistor P ₂ second PMOS transistor N ₁ first NMOS transistor N ₂ Second NMOS transistor

Claims (1)

(57) [Claims] A first P-type gate having its own drain voltage supplied between a charging side of a logic gate circuit and a power supply;
A channel MOS transistor, and a second P gate whose gate receives the output of the logic gate circuit through an inverter.
A first N-channel MOS transistor having its own drain voltage supplied to the gate between the discharge side of the logic gate circuit and ground; A second N-channel MOS transistor whose output is supplied via an inverter is interposed in parallel, and the first P-channel MOS transistor and the first N-channel MOS transistor have a large driving force, and P
A semiconductor circuit, wherein the channel MOS transistor and the second N-channel MOS transistor have low driving power.