JPH0537321A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce linking of an output signal at the time when a level of an output signal is varied and a fluctuation of a level of a power source wiring and a ground wiring to prevent a malfunction of other circuits and, to execute an operation at a high speed. CONSTITUTION:An output potential control circuit 2 for setting a level of an output terminal TMo to an intermediate level of a high level and a low level at a timing immediately before an output signal Vo is subjected to level variation is provided. The output potential control circuit 2 is constituted of a capacity element C1 of capacity being equal to load capacity Co, a transistor Q3 for executing connection control of this capacity element C1 and the output terminal TMo by a signal phi3, a resistance R1 of a charging/discharging circuit, and transistors Q4-Qn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output circuit for generating a digital output signal in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in this type of output circuit, as shown in FIGS. 3A and 3B as an example, the drain is connected to a first power supply terminal TMp having a power supply voltage Vcc and the source is connected to an output terminal TMo. And a first transistor Q1 which is connected to the gate and inputs and outputs a first signal Φ1 to the gate, and a second source Q2.
A second transistor Q2 which is connected to the ground terminal TMg of the power supply terminal, the drain thereof is connected to the output terminal TMo, and the gate of which receives the second signal Φ2 to turn on and off the first and second signals Φ1. , Φ2, the output stage circuit 1 in which the first and second transistors Q1 and Q2 are simultaneously turned off immediately before the level (Vo) of the output terminal TMo is determined.

The load circuit 10 is connected to the output terminal TMo. The capacitance of the wiring from the output end of the output stage circuit 1 to the input end of the load circuit, the diffusion layer capacitance of the transistors Q1 and Q2, and the load circuit 10 are connected. There is a load capacitance Co including the capacitance of its own input end.

Further, between the power supply terminal TMp and the power supply terminal of the output stage circuit 1, and between the ground terminal TMg and the ground end of the output stage circuit 1, there are inductances L1 and L2 due to the respective wirings. To do.

Next, the operation of this output circuit will be described.

First, it is assumed that the output signal Vo is at a low level. At this time, the signal Φ1 is at the low level, the signal Φ2 is at the high level, and the transistor Q1 is off and the transistor Q2 is on.

Next, in order to change the output signal Vo from the low level to the high level, the signal Φ2 is set to the low level to turn off both the transistors Q1 and Q2, and the signal Φ1 is set to the high level to turn on the transistor Q1. .

To change the output signal Vo from the high level to the low level, the signal Φ1 is set to the low level to turn off both the transistors Q1 and Q2, and then the signal Φ2 is set to the high level to turn on the transistor Q2.

As described above, the reason why both the transistors Q1 and Q2 are once turned off before the level of the output signal Vo is changed is that when the signals Φ1 and Φ2 are changed at the same time, the transistors Q1 and Q2 are turned on at the same time and a through current is generated. This is for the purpose of avoiding this, and for avoiding the inconvenience due to the multi-select state which tends to occur when the address changes in the memory circuit and the like.

[0010]

In the conventional output circuit described above, the output terminal TMo has the load capacitance Co, and the wiring between the power supply terminal TMp and the power supply terminal of the output stage circuit 1 is provided.
Since the inductances L1 and L2 exist in the wiring between the ground terminal TMg and the ground terminal of the output stage circuit 1, when the level of the output signal Vo changes, the inductance L
Since the load capacitance Co and the load circuit 10 are charged and discharged via 1 and L2, linking occurs in the output signal Vo as shown in FIG. The potential Vcc1 and the potential GND1 at the ground end fluctuate, and these are propagated to other circuits as power supply noise and ground line noise, causing a malfunction.

Further, there is a problem that the time (T2) until the linking of the output signal Vo is kept at a predetermined level becomes long and the operation speed is lowered.

An object of the present invention is to reduce the linking of the output signal Vo and the fluctuation of the levels of the power supply wiring and the ground wiring to reduce the noise caused by these, thereby preventing the malfunction of other circuits, and It is to provide an output circuit capable of achieving high speed.

[0013]

In the output circuit of the present invention, one of a source and a drain is connected to a first power supply terminal, the other is connected to an output terminal, and a first signal is input to a gate to turn it on.
A first transistor that is turned off, and one of a source and a drain that is connected to a second power supply terminal and the other is connected to the output terminal, and a second signal that is input to the gate to turn it on and off
Immediately before the level of the output terminal is determined by the first and second signals.
An output stage circuit in which the transistors of are simultaneously turned off,
A capacitance element having a capacitance equivalent to a load capacitance connected to the output terminal, a charging / discharging circuit for charging / discharging one end of the capacitance element to a predetermined level different from the level of the output terminal, and a source and a drain of the capacitance element. An output potential control circuit including a third transistor which is connected between one end and an output terminal and inputs a third signal to a gate and is turned on while the first and second transistors are simultaneously turned off. have.

A charging / discharging circuit is connected between a first resistance element connected between the first power supply terminal and one end of the capacitance element, and between a second power supply terminal and one end of the capacitance element. And a second resistance element, which is configured to charge and discharge one end of the capacitance element to an intermediate level between the high level and the low level of the output terminal.

The charging / discharging circuit has the input terminal connected to the output terminal, the output terminal connected to one end of the capacitive element, and is activated and controlled by the third control signal to turn off the third transistor. It has a configuration in which one end of the capacitive element is formed by a clocked inverter that charges and discharges the output terminal to a level obtained by inverting the level of the output terminal.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A and 1B are a circuit diagram showing a first embodiment of the present invention and a waveform diagram of signals at respective parts for explaining the operation of this embodiment.

This embodiment differs from the conventional output circuit shown in FIG. 3A in that one end is connected to a ground terminal TMg (or ground wiring) and a capacitance element C1 having a capacitance equivalent to the load capacitance Co is provided. And a resistor R connected across the capacitive element C1
1, power supply terminal TMp (or power supply wiring) and capacitive element C1
A resistor element formed of diode-connected transistors Q4 to Qn connected in series with the other end of the capacitor, a source and a drain thereof are connected between the capacitor element C1 and the output terminal TMo, and turned on and off by a third signal Φ3. Third transistor Q3
And a capacitive element C1 is connected to a high level of the output signal Vo (power supply voltage Vc by a resistor R1 and transistors Q4 to Qn).
c) and the low level (OV) intermediate level Vcc / 2 is charged / discharged, and the signal Φ3 turns on the transistor Q3 while the transistors Q1 and Q2 are simultaneously turned off. It is in the point provided.

Next, the operation of this embodiment will be described.

The operation of the output stage circuit 1 is similar to that of the conventional example shown in FIG.

The signal Φ3 is at a high level immediately before the level of the output signal Vo is changed and the transistors Q1 and Q2 are simultaneously turned off, turning on the transistor Q3. The capacitive element C1 is charged or discharged by the resistor R1 and the transistors Q4 to Qn so as to be Vcc / 2 while the transistor Q3 is off.

When changing the output signal Vo from the low level to the high level, both the signals Φ1 and Φ2 are set to the low level to turn off the transistors Q1 and Q2, and the signal Φ3 is set to the high level to turn on the transistor Q3. . Then, the level of the output terminal TMo changes to the potential of the capacitive element C1 (node N
(1 potential) Vcc / 2 rises to a level (approximately Vcc / 4) determined by capacitance division with the load capacitance Co, and is further charged by the transistors Q4 to Qn in the direction of Vcc / 2. After a predetermined period, the signal Φ3 becomes low level and the transistor Q3 is turned off.

When the signal Φ1 goes high and the transistor Q1 turns on, the load capacitance Co and the load circuit 1 are turned on.
0 is charged to the power supply voltage Vcc through the transistor Q1. At this time, the level of the output terminal TMo is Vcc / 2.
Since it is charged from the level close to the Vcc level to the Vcc level, the current flowing through the power supply wiring or the like is from the OV level to the Vcc level or the Vcc level.
This is smaller than the conventional example in which the cc level is changed to OV, and therefore the fluctuation of the linking level of the output signal Vo and the level of the power supply wiring (Vcc1) is small, and the time T1 until the output signal Vo is settled is also short. I will get sick.

Even when the output signal Vo is changed from a high level to a low level, there is a difference in charging and discharging, a difference in power supply wiring and a ground wiring, but the operation is basically the same as described above, and the same effect is obtained. There is.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the charging / discharging circuit has an input terminal connected to the output terminal TMo and an output terminal connected to one end (N) of the capacitive element C1.
1) connected to 1) and activated and controlled by the third control signal Φ3 to charge and discharge one end of the capacitive element C1 to the level obtained by inverting the level of the output terminal TMo when the third transistor Q3 is in the off state. It is formed by CIV1.

In this embodiment, when the output signal Vo (output terminal TMo) is at a low level, the capacitive element C1 is connected to Vc.
It is charged to the c level and discharged to the ground potential when it is at the high level. Therefore, when the transistor Q3 is turned on, the level of the output terminal TMo immediately becomes the Vcc / 2 level. Other operations and effects are basically the same as those in the first embodiment.

[0028]

As described above, according to the present invention, before changing the level of the output terminal (output signal), the level of the output terminal is charged / discharged to an intermediate level between the high level and the low level to control the output potential. By providing a circuit,
Since the level of the output terminal changes from the intermediate level of high level and low level to high level or low level, the charging / discharging current becomes smaller than the conventional example that changes from low level to high level or from high level to low level. Therefore, the level of fluctuation of the output signal linking and the fluctuations of the power supply wiring and the ground wiring becomes smaller, and the time until settling becomes shorter, and the noise resulting from these is reduced, and the malfunction of other circuits can be prevented. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention and a waveform diagram of signals of respective parts.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional output circuit and a waveform diagram of signals of respective parts.

[Explanation of symbols]

1 output circuit 2,2a Output potential control circuit 10 load circuit Co load capacity C1 capacitive element CIV1 clocked inverter IV1 inverter Q1-Qn transistors R1 resistance

Claims (3)

[Claims] 1. A first transistor that connects one of a source and a drain to a first power supply terminal, connects the other to an output terminal, inputs a first signal to a gate to turn on and off, and a source and a drain. A second transistor that connects one to a second power supply terminal and the other to the output terminal and turns on and off by inputting a second signal to the gate; and the output terminal according to the first and second signals Of the output stage circuit in which the first and second transistors are turned off at the same time immediately before the level is determined, and a capacitance element having a capacitance equivalent to the load capacitance connected to the output terminal, and one end of the capacitance element A charging / discharging circuit for charging / discharging to a predetermined level different from the level of the output terminal, a source and a drain are connected between one end of the capacitance element and the output terminal, and a third signal is input to the gate to input the first and Two And an output potential control circuit including a third transistor that is turned on while the transistor is turned off at the same time. 2. A charging / discharging circuit is connected between a first resistance element connected between a first power supply terminal and one end of a capacitance element, and a second power supply terminal is connected between one end of the capacitance element. The second done
2. The output circuit according to claim 1, further comprising: a resistance element according to claim 1, wherein one end of the capacitance element is charged / discharged so that the output terminal has an intermediate level between a high level and a low level. 3. The charging / discharging circuit connects the input terminal to the output terminal, connects the output terminal to one end of the capacitive element, and is activated and controlled by the third control signal to turn off the third transistor. The output circuit according to claim 1, wherein one end of the capacitive element is formed by a clocked inverter that charges and discharges one end of the capacitive element to a level obtained by inverting the level of the output terminal.