JPH05291901A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To detect a fault of a control input of a selector and to reduce a defect in products by sending a logic state of a selection signal to an external device. CONSTITUTION:A selector 2a selects a path for an input pulse 100 to be propagated to a path 101 passing through a delay element 1a or a path 100 not passing the element 1a, and a selector 2b selects a path for an input pulse 100 to be propagated to a path 105 passing through delay elements 1b,1c or a path 102 not passing the elements when the level of a control line 107 is set to '0'. The delay time is varied through the operation. As a result, in the case of testing the variable delay circuit, since a fault of a control input of the selector is detected, the fault detection is attained by a low speed logic test and a defect in products incorporating the variable delay circuit is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit suitable for an electronic measuring device such as a semiconductor test device.

[0002]

2. Description of the Related Art In an electronic measuring device such as a semiconductor test device, a variable delay circuit for controlling a signal propagation delay time is essential.

As such a variable delay circuit, the technique described in "Proceeding of Eye, E, E, International Test Conference (September, 1981), Paper 7.5, pp. 143 to 153" is used. Are known.

This technique will be described below.

FIG. 3 shows the configuration of a variable delay circuit according to this conventional technique. FIG. 4 shows an internal circuit configuration and a truth table of a selector used in the variable delay circuit according to the conventional technique.

As shown in the figure, the conventional variable delay circuit is
A pulse is applied from the input 100 and a delayed output is obtained from the output 106, and includes delay elements 1a, 1b, 1c and selectors 3a, 3b. The input pulse 100 passes through a path defined by control data applied from the outside.
That is, when the B side path is selected by the selector 3a, the pulse propagates with a delay from the A side path by the delay time of the delay element 1a. Similarly, in the next stage, the delay element 1
Delay control is performed for the delay times of b and 1c. If more delay elements and selectors are provided, a variable delay circuit having a larger variable width can be constructed.

On the other hand, in the variable delay circuit of the conventional example, the resolution can be set to the delay time of one stage of the delay element, so that the high resolution variable delay circuit can be realized as the speed of the element increases.

[0008]

Semiconductor devices such as gate arrays are tested for their functional logic and delay time after manufacture. However, with the recent increase in the speed of semiconductor elements, the time resolution of the variable delay circuit built in the gate array or the like has become equal to or less than the time accuracy of the tester used for the test. Therefore, it is difficult to test the function of the variable delay circuit by measuring the delay time control result with a tester.

In the gate array test which is usually performed, only the logic low speed test is performed, so that all the control inputs of the selectors constituting the variable delay circuit become nodes in which a failure cannot be detected. This causes an increase in the defective rate of products incorporating the variable delay circuit.

Therefore, it is an object of the present invention to make it possible to detect a failure in the control input of the selector, and to improve the failure detection rate to reduce product defects.

[0011]

To achieve the above object, the present invention provides means for transmitting the state of the control input of a selector in a variable delay circuit to the outside when testing a semiconductor device having a variable delay circuit. Was established.

[0012]

According to the variable delay circuit of the present invention, since the state of the control input of the selector in the variable delay circuit can be transmitted to the outside, the stack fault of the selector control input can be detected. As a result, the function test of the variable delay circuit can be performed without measuring the change in the output delay time when the delay time of the variable delay circuit is controlled.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an embodiment of a variable delay circuit according to the present invention.
This will be described with reference to FIG.

First, FIG. 1 shows the configuration of a variable delay circuit according to this embodiment.

As shown in the figure, the variable delay circuit according to this embodiment includes delay elements 1a, 1b, 1c and selectors 2a, 2b.
Consists of. The selectors 2a and 2b are shown by the internal circuit configuration and truth table of FIG. First, the operation when the control line 107 is 0 will be described. At this time, the selectors 2a and 2b operate similarly to the selector of the conventional example. The path through which the input pulse 100 propagates is selected by the selector 2a into the path 101 passing through the delay element 1a and the path 100 not passing through it, and the selector 2b does not pass through the path 105 passing through the delay elements 1b and 1c. And the route 102. The delay time can be changed by the above operation.

[0016]

As described above, according to the present invention, since the failure of the control input of the selector can be detected during the test of the variable delay circuit, the failure can be detected by the low-speed logic test. The defects of the built-in product can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a variable delay circuit according to an embodiment of the present invention.

FIG. 2 is a diagram similarly showing a variable delay circuit.

FIG. 3 is a diagram showing a conventional variable delay circuit.

FIG. 4 is a diagram showing an internal circuit configuration and a truth table of a selector used in a conventional variable delay circuit.

[Explanation of symbols]

 1a, 1b, 1c ... Delay element, 2a, 2b ... Selector (with diagnostic function), 3a, 3b ... Selector.

Claims (1)

[Claims] 1. A variable delay circuit for controlling a delay time by selecting a path through which a signal passes, comprising a means for transmitting a logical state of a selection signal applied to a selector to the outside. circuit.