JPH05299348A - Forming method for polysrystalline silicon thin film - Google Patents

Abstract

PURPOSE:To provide the forming method for polycrystalline silicon thin film having excellent electrical characteristics in a large crystalline particle diameter while developing less defects in the crystalline particles. CONSTITUTION:When a polycrystalline silicon thin film 4 is formed by crystallizing an amorphous silicon thin film 3 using heat treatment step, the heat treatment step is to be performed in two phases i.e., the first step at the temperature not exceeding 650 deg.C and the second step at the temperature exceeding 700 deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polycrystalline silicon thin film in which an amorphous silicon thin film is crystallized by heat treatment.

[0002]

2. Description of the Related Art A polycrystalline silicon thin film serves as various electrodes, wiring materials or resistors and plays an important role as a material for forming semiconductor devices. For example, this polycrystalline silicon thin film is applied to a charge storage electrode, a gate electrode in a memory device, or a contact burying material between a device active layer and a wiring layer. Further, in recent years, a polycrystalline silicon thin film transistor (TFT) using a polycrystalline silicon thin film itself as a device active layer has been developed, and is used as a load element of SRAM (static RAM) or a liquid crystal driving element for a liquid crystal display (LCD). It has been put to practical use.

Conventionally, as a method of forming this polycrystalline silicon thin film, a chemical vapor deposition method using a silane-based gas (SiH ₄ , Si ₂ H ₆ ) as a reaction gas is used, and the polycrystalline film is formed at a film forming temperature of about 650 ° C. There is a method of directly depositing a silicon thin film.
Further, the amorphous silicon thin film is deposited at a film forming temperature of about 500 ° C., and then the sample temperature is set to about 600 to 90 ° C.
There is also a method of obtaining a polycrystalline silicon thin film by crystallizing it by a heat treatment of holding it at 0 ° C. In particular, since the polycrystalline silicon thin film formed by the latter method has a larger average crystal grain size than that formed by the former method, it is possible to reduce the resistance,
Further, it has an advantage that the number of crystal grain boundaries that strongly influence the transistor characteristics is smaller than that formed by the former method. For this reason, the latter method of crystallizing the amorphous silicon thin film by heat treatment is currently attracting attention, and is vigorously developed as an application to a thin film for TFT and various electrode forming methods in the future (for example, , Abstra
ctsof the 20th Conference on Solid State Devices a
nd Materials, 1989, pp.57-60).

In the conventional method for forming a polycrystalline silicon thin film which is crystallized by this heat treatment, first, a thermal oxide film is grown and formed to a thickness of about 1000Å on a silicon single crystal substrate, and then a normal LPCVD furnace is used. Using, an amorphous silicon thin film is formed to a thickness of about 3000Å. The film forming conditions are, for example, a pressure of 0.15 Torr,
The temperature is 510 ° C., the reaction gas flow rate is 150 sccm with 100% Si ₂ H ₆ , and 200 sccc with He base 4% PH ₃ .
m. Next, using an electric furnace, for example, in a nitrogen atmosphere, the furnace temperature is kept at 900 ° C. and heat treatment is performed for 20 minutes to crystallize the amorphous silicon thin film to form a polycrystalline silicon thin film.

In this case, since the polycrystalline silicon thin film is composed of a large number of crystal grains, its electrical characteristics are greatly influenced by the characteristics (size, crystallinity) of the crystal grains. For example, the traps existing at the crystal grain boundaries capture the carriers responsible for electrical conduction, so that an energy barrier is formed near the grain boundaries, which greatly affects the electrical conduction of the polycrystalline silicon thin film. Therefore, in order to obtain good electric characteristics (for example, low resistivity or high carrier mobility), the grain boundaries existing in the electric conduction region are reduced by increasing the size of the crystal grains as much as possible. Two important points are to reduce crystal defects in grains.

[0006]

However, the conventional method has a problem that it is not possible to simultaneously satisfy the above-mentioned two important characteristics concerning the crystal grains as described below. As described above, the conventional method is a method of crystallizing an amorphous silicon thin film by heat treatment to form a polycrystalline silicon thin film. The crystal grain characteristics of the polycrystalline silicon thin film formed by this conventional method are mainly determined by the conditions of the crystallization heat treatment. For example, by heat treatment at a relatively low temperature (about 600 ° C.), a polycrystalline silicon thin film having a large crystal grain size can be obtained, but many crystal defects remain in the crystal grain. On the other hand, high-temperature heat treatment at about 900 ° C. makes it possible to obtain a polycrystalline silicon thin film with few crystal defects in the crystal grains, but the crystal grain size becomes small. This is because the lower the heat treatment, the slower the generation rate of crystal nuclei in the crystallization of the amorphous silicon thin film, and the higher the heat treatment promotes the relaxation of crystal defects in the crystal grains. Therefore, in the conventional method, it is difficult to obtain a polycrystalline silicon thin film having a large crystal grain size and few defects in the crystal grain.

The present invention has been made in view of the above problems, and provides a method for forming a polycrystalline silicon thin film having a large crystal grain size, few crystal grain defects, and excellent electrical characteristics. The purpose is to

[0008]

A method for forming a polycrystalline silicon thin film according to the present invention is a method for forming a polycrystalline silicon thin film by crystallizing an amorphous silicon thin film by heat treatment, wherein the heat treatment is performed at a temperature of 650 ° C. or lower. It is characterized in that it is divided into a first heat treatment step of performing heat treatment at 1. and a second heat treatment step of performing heat treatment at a temperature of 700 ° C. or higher.

[0009]

In the present invention, the amorphous silicon thin film is crystallized by the first heat treatment step at 650 ° C. or lower and the second heat treatment step at 700 ° C. or higher. First, in the first heat treatment process at a relatively low temperature, a polycrystalline silicon thin film having a slow generation rate of crystal nuclei and a large crystal grain size is formed. Then, the subsequent second heat treatment at a relatively high temperature can reduce the crystal defects in the crystal grains. Therefore, a high-quality polycrystalline silicon thin film having a large crystal grain size and few crystal defects in the crystal grain can be formed.

[0010]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views showing a method of an embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, for example, the plane orientation is (100) and the resistivity is 10
A P-type silicon substrate 1 of Ω · cm is used, and a thermal oxide film 2 is formed on the silicon substrate 1 with a thickness of about 1000 Å as shown in FIG. In addition, phosphorus (P) was added by a normal batch type LPCVD equipment using a resistance heating furnace.
About 3000 of doped N-type amorphous silicon thin film 3
Deposition is done with a thickness of Å.

The film forming conditions are, for example, a reaction tube temperature of about 510 ° C., a pressure of 0.15 Torr, and a reaction gas of 100% Si ₂ H ₆ and 4% He base P.
H ₃ gas is used at a flow rate of 150 sccm and 200 sccm, respectively. Under this condition, the phosphorus concentration in the amorphous silicon thin film 3 is 5 × 10 ²⁰ / cm ³ or less.

Next, as shown in FIG. 1C, first, 6
The amorphous silicon thin film 3 formed is heat-treated at a temperature of 50 ° C. or lower to form a polycrystalline silicon thin film 4. This polycrystalline silicon thin film 4 has a large grain size, but has defects inside the grain. Therefore, the polycrystalline silicon thin film 4 is further heat-treated at a temperature of 700 ° C. or higher to eliminate this defect. In this case, the second heat treatment is performed for a time period such that the crystal grain size does not decrease. As a result, the polycrystalline silicon thin film 4 having a large crystal grain size and few defects inside the crystal grain is formed.

In this embodiment, the first temperature below 650 ° C.
The amorphous silicon thin film is crystallized by the heat treatment step (1) and the second heat treatment step at 700 ° C. or higher. First, in the first heat treatment process at a relatively low temperature, a polycrystalline silicon thin film having a slow generation rate of crystal nuclei and a large crystal grain size is formed. Then, the subsequent second heat treatment at a relatively high temperature can reduce the crystal defects in the crystal grains. Therefore, a high-quality polycrystalline silicon thin film 4 having a large crystal grain size and few crystal defects in the crystal grain can be formed.

Next, the characteristics of the polycrystalline silicon thin film formed by the method of this example will be described in comparison with those formed by the method of the comparative example. First, the region of the amorphous silicon thin film 3 formed under the conditions of the process shown in FIG. 1B is divided into 5 regions, 4 regions are heat-treated under conventional conditions as a comparative example, and the remaining 1 region is the same as that of this embodiment. A two-step heat treatment was performed to form a polycrystalline silicon thin film 4. Regarding the temperature and time of the heat treatment, the level 1 of the comparative example is 1 at 600 ° C.
80 minutes, level 2 700 ℃ for 20 minutes, level 3 800 ℃
For 20 minutes, the level 4 is 900 ° C. for 20 minutes, and the level 5 of this embodiment is 90 minutes after heat treatment at 600 ° C. for 180 minutes.
It was carried out at 0 ° C. for 20 minutes. Regarding this heat treatment at 600 ° C., the treatment time is set to 180 minutes because it takes a longer time to crystallize as compared with other levels.

Below, the crystal grain size of the polycrystalline silicon thin film,
The results of evaluation of crystallinity and resistivity in crystal grains will be described. First, FIG. 2 is a graph showing the relationship between the heat treatment conditions and the crystal grain size of the polycrystalline silicon thin film. As shown in FIG. 2, the crystal grain size evaluated by the transmission electron microscope is as follows: low-temperature heat treatment level 1 and low-temperature heat treatment followed by high-temperature heat treatment level 5 in this example.
The maximum crystal grain size is obtained in and.

On the other hand, FIG. 3 is a graph showing the crystallinity of the polycrystalline silicon thin film with respect to the heat treatment conditions. As shown in FIG. 3, when the crystallinity in the crystal grains was evaluated from the peak width of the X-ray diffraction line (evaluated by the integral width) by the θ-2θ scan method, the heat treatment temperature was 900 ° C., which was Level 4 and the present example. And the peak width (integral width) of the X-ray diffraction line is minimum. Since the peak width of the diffraction line becomes smaller as the crystallinity becomes better, it is confirmed that the crystallinity is most improved in Level 4 and Level 5.

Further, FIG. 4 is a graph showing the resistivity of the polycrystalline silicon thin film with respect to heat treatment conditions. As shown in FIG. 4, the sheet resistance of the polycrystalline silicon thin film was measured by the 4-probe method, and the obtained sheet resistance was subjected to film thickness correction to calculate the film resistivity. The lowest resistivity is obtained at the level (level 5).

Next, a method for forming a polycrystalline silicon thin film according to the second embodiment of the present invention will be described with reference to FIGS. This embodiment applies the present invention to the manufacture of a TFT. First, as shown in FIG. 5, a thermal oxide film 1 is formed on a P-type silicon single crystal silicon substrate 11 having a plane orientation of (100) and a resistivity of 10 Ω · cm as shown in FIG.
2 is formed, and then an amorphous silicon thin film 13 is formed in the same manner as in the first embodiment. However, P doping is not performed in this embodiment.

Next, as shown in FIG. 7, the amorphous silicon thin film 13 is heat-treated at a temperature of 650 ° C. or lower to form a polycrystalline silicon thin film 14. Since this polycrystalline silicon thin film 14 has a large crystal grain size but contains defects inside the crystal grain, the polycrystalline silicon thin film 1 is further heated at a temperature of 700 ° C. or higher.
4 is heat-treated to reduce crystal defects in crystal grains. As a result, the polycrystalline silicon thin film 14 having a large crystal grain size and few defects inside the crystal grain is formed.

Next, as shown in FIG. 8, this polycrystalline silicon thin film 14 is patterned by a photolithography process and an ion etching process.

Next, as shown in FIG. 9, a gate oxide film 15 is formed on the patterned polycrystalline silicon thin film 14.

Next, after a polycrystalline silicon thin film is formed on this gate oxide film 15 by a normal LPCVD method,
The polycrystalline silicon thin film is patterned by a photolithography process and an ion etching process to form a polycrystalline silicon gate electrode 16 as shown in FIG.

Finally, as shown in FIG. 11, arsenic is implanted using the polycrystalline silicon gate electrode 16 as a mask to form a source region 17 and a drain region 18 in the polycrystalline silicon thin film 14 to form a polycrystalline silicon thin film transistor ( TFT) is completed.

Also in this embodiment, the first temperature below 650 ° C.
Since the amorphous silicon thin film 13 is crystallized to form the polycrystalline silicon thin film 14 by the heat treatment step and the second heat treatment step at 700 ° C. or higher, the obtained polycrystalline silicon thin film 14 has a large crystal grain size, Moreover, the quality of the crystal grain is small with few crystal defects. Therefore, the TFT composed of the polycrystalline silicon thin film 14 has improved mobility and on-current, good responsiveness, and high driving ability.

Next, the characteristics of the polycrystalline silicon thin film formed by the method of this example will be described in comparison with those formed by the method of the comparative example. First, the region of the amorphous silicon thin film 13 formed under the conditions of the process shown in FIG. 6 is divided into two, and one sample is 180 ° C. at 600 ° C. which is the conventional condition.
Heat treatment for 180 minutes, and for the other sample, after heat treatment for 180 minutes at 600 ° C. under the conditions of this embodiment, further 900 ° C.
Then, the amorphous silicon thin film 13 is crystallized by performing a heat treatment for 20 minutes to form a polycrystalline silicon thin film 14 as shown in FIG. The subsequent steps are all performed in the same process as described above to complete the TFT. That is,
In the above TFT forming process, the comparative example and the present example are different only in the crystallization process of the amorphous silicon thin film 13, and the other processes are all the same.

In this example, the crystal grains of the polycrystalline silicon thin film 14 were evaluated in the same manner as in the first example. As in the first example, this example showed that crystal defects in the crystal grains were smaller. It has decreased significantly. Further, when the transistor characteristics of the TFT were evaluated, in particular, the present example shows an improvement in the on-current and the mobility which are considered to be strongly influenced by the crystal grain characteristics. The TFT obtained by the conventional conditions mobility 30cm ² / V · S, but ON current is 100 nA, TFT according to this embodiment, the mobility is 35 cm ² /
V ・ S and ON current are improved to 150nA,
The present embodiment has obtained faster response capability and higher drive capability than the comparative example under the conventional condition.

Although only the phosphorus-doped film has been described in the first embodiment, the same effect (reduction in resistivity) can be obtained even if the dopant impurity is arsenic or boron.

Next, a third embodiment of the present invention will be described. The present embodiment applies the present invention to a contact burying material for a device active layer and a wiring layer in various semiconductor devices, and specifically shows a method for producing a contact resistance evaluation substrate.

12 to 15 are sectional views showing the method of this embodiment in the order of steps. First, as shown in FIG. 12, As is ion-implanted into a predetermined region of the surface of a P-type silicon single crystal substrate 21 having a plane orientation (100) and a resistivity of 10 Ω · cm to form an n ⁺ -type diffusion layer 22. Selectively formed.

Next, as shown in FIG. 13, a thermal oxide film 23 having a thickness of 1 μm is formed on the surface of the substrate 21, and a contact having a diameter of 0.4 mm and a depth of 1 μm is formed by photolithography and ion etching. The hole 31 is formed.

Thereafter, similarly to the first embodiment, while doping P, an amorphous silicon thin film is formed on the entire surface so as to fill the contact hole 31. Then, after heating to 600 ° C for 180 minutes, it is heated to 900 ° C for 2 minutes.
A heat treatment of heating for 0 minutes is performed. As a result, the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film 24 as shown in FIG. After that, the excess polycrystalline silicon thin film on the oxide film is removed by an ion etching process, and the polycrystalline silicon thin film 24 remains only in the contact hole 31.

Next, as shown in FIG. 15, titanium (Ti) having a thickness of, for example, 300 Å is formed by a sputtering method.
Thin film 25, titanium nitride (Ti) with a thickness of, for example, 1000Å
N) Thin film 26, Al-Si- with a thickness of 5500Å, for example
Cu alloy film 27 and Ti thin film 2 having a thickness of, for example, 300 Å
8 are sequentially laminated. Then, these layers were etched in a predetermined pattern to form a separation groove 32 and separated into a plurality of upper electrodes. Thereby, the polycrystalline silicon thin film 2
For example, 2000 contact plug portions composed of 4 are arranged in series.

In this way, in the contact resistance evaluation substrate manufactured by the first level and second level heat treatment,
The only difference is the crystallization heat treatment step of amorphous silicon. Then, in order to investigate the influence of the heat treatment conditions, the substrate (level 1) heated to 900 ° C. for 20 minutes by the conventional method and the substrate of 600 ° C. for 180 minutes and then to 900 ° C. for 20 minutes are heated by the method of this embodiment. As a result of measuring the contact resistance of the heat-treated substrate (level 2), the resistance per contact is the resistance value (800 to 1500Ω) of the one manufactured by the conventional method (level 1).
In contrast, the resistance value of this example (level 2) was remarkably reduced to 235Ω, and a good contact could be formed.

[0035]

According to the present invention, it is possible to form a high quality polycrystalline silicon thin film having large crystal grains and few crystal defects in the crystal grains. This makes it possible to form a polycrystalline silicon thin film having excellent electrical characteristics (low resistivity and high carrier mobility) as compared with the conventional method.

[Brief description of drawings]

FIG. 1A is a sectional view showing one step in a method for forming a polycrystalline silicon thin film according to a first embodiment of the present invention,
FIG. 6B is a sectional view showing another step of the method of this embodiment, and FIG. 8C is a sectional view showing another step of the method of this embodiment.

FIG. 2 is a graph showing the crystal grain size of a polycrystalline silicon thin film with respect to heat treatment conditions.

FIG. 3 is a graph showing the crystallinity of a polycrystalline silicon thin film with respect to heat treatment conditions.

FIG. 4 is a graph showing the resistivity of a polycrystalline silicon thin film with respect to heat treatment conditions.

FIG. 5 is a sectional view of a step illustrating a method for manufacturing a TFT by the method for forming a polycrystalline silicon thin film according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another step of the method of this embodiment.

FIG. 7 is a cross-sectional view showing another process of the method of this embodiment.

FIG. 8 is a sectional view showing another process of the method of this embodiment.

FIG. 9 is a sectional view showing another process of the method of this embodiment.

FIG. 10 is a cross-sectional view showing another process of the method of this embodiment.

FIG. 11 is a sectional view showing another process of the method of this embodiment.

FIG. 12 is a sectional view of a step illustrating a method of forming a contact between a device active layer and a wiring layer by the method of forming a polycrystalline silicon thin film according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing another process of the method of this embodiment.

FIG. 14 is a cross-sectional view showing another process of the method of this embodiment.

FIG. 15 is a cross-sectional view showing another process of the method of this embodiment.

[Explanation of symbols]

 Silicon substrates 2, 12, 23; oxide films 3, 13; amorphous silicon thin films 4, 14, 24; polycrystalline silicon thin films 15; gate oxide films 16; polycrystalline silicon gate electrodes 17; source regions 18 Drain region 22; diffusion layers 25 and 28; titanium thin film 26; titanium nitride thin film 27; Al-Si-Cu alloy film 31; contact hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (4)

[Claims] 1. A method of crystallizing an amorphous silicon thin film by heat treatment to form a polycrystalline silicon thin film, wherein the heat treatment comprises a first heat treatment step of heat treatment at a temperature of 650 ° C. or lower and a heat treatment of 700 ° C. or higher. And a second heat treatment step for forming a polycrystalline silicon thin film. 2. The amorphous silicon thin film,
2. The method for forming a polycrystalline silicon thin film according to claim 1, wherein a material doped with phosphorus, arsenic or boron as an impurity is used. 3. The method for forming a polycrystalline silicon thin film according to claim 1, wherein the polycrystalline silicon thin film is used as an active region for forming a source and a drain of a polycrystalline silicon thin film transistor. 4. The method for forming a polycrystalline silicon thin film according to claim 1, wherein the polycrystalline silicon thin film is used as a contact burying layer between a device active layer and a wiring layer.