JPH05283952A - Differential operational amplifier - Google Patents

Abstract

PURPOSE:To widen the differential output ranges of a fully differential operational amplifier and to reduce in-phase noise. CONSTITUTION:The fully differential operational amplifer has two buffer circuits 17-20, 25-28 inputting the differential output, respectively, partial pressure circuits R1, R2 detecting middle point voltage by performing the partial pressure for the output of the both buffer circuits and feedback circuits 12-16, 21-24 amplifying the difference of the middle point potential and reference voltage VR and performing the feedback to the gates of current source transistors 10, 11 of the fully differential operational amplifier for the difference. Each buffer circuit 17-2O, 25-28 is composed of CMOS inverters 17, 25, 20, 28 and MOS transistors 18, 26, 19, 27 which become the load of the COMS inverters and for which diode connections are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fully differential operational amplifier formed on a MOS integrated circuit, and more particularly to an operational amplifier having a common-mode feedback circuit effective for a Hold Cascode type operational amplifier having a high output impedance. ..

[0002]

2. Description of the Prior Art Fully differential operational amplifiers require a common mode feedback circuit to stabilize the DC operating point of the differential output. An example of a fully differential operational amplifier including a common mode feedback circuit is shown in FIG. In FIG. 3, reference numerals 71 to 75 are n-channel transistors, 76 to 79 are p-channel transistors, and CC1 and CC2.
Is a phase compensation capacitor, R3 and R4 are resistors, IP and IM are positive and negative input terminals for amplification, Vb10 is a bias input terminal, OP is a positive output terminal, and OM is a negative output terminal. This circuit is a general two-stage operational amplifier that obtains a differential output by amplifying the output of a differential pair with a source-grounded amplifier circuit.

If the resistors R3 and R4 are not provided and a constant bias is applied to the gates of the transistors 74 and 75, the gain for the common mode input of this operational amplifier becomes a very high value. As a result, the input terminal I
Even if a small in-phase input is added to P and IM, the output fluctuates greatly and the DC operating point of the output is not stable.

The gain for the in-phase input here is suppressed,
A circuit that stabilizes the output DC operating point is a common-mode feedback circuit. In the case of the circuit of FIG. 3, the differential output O is generated by the resistors R3 and R4.
An in-phase feedback circuit is realized by detecting the midpoint voltage of P and OM and feeding back the midpoint voltage to the gates of the output stage current source transistors 74 and 75.

The method of directly dividing the differential output with an impedance such as a resistance and feeding it back as in the circuit of FIG. 3 has an advantage that a common mode feedback circuit can be realized with a simple circuit configuration.
Since a direct load is applied between the differential outputs, a negative feedback circuit is formed even for differential signals, which causes a decrease in open loop gain and deterioration of frequency characteristics. In order to prevent these deteriorations, it is necessary to make the resistance value of the resistance voltage divider circuit sufficiently larger than the output impedance of the operational amplifier.

However, the above-mentioned common-mode feedback circuit is used in a high-speed switched capacitor circuit or the like in recent years.
code type operational amplifier (R. GREGORIAN and G. TEMES, JOHN
Published by WILEY & SONS, ANALOG MOS INTEGRATED CIRCUITS F
OR SIGNAL PROCESSING See page 255. ) Cannot be used for operational amplifiers with high output impedance.

FIG. 4 shows Holded shown in the above-mentioned reference example.
A Cascode type operational amplifier is shown. The output impedance of a Holded Cascode type operational amplifier is about several MΩ.
Compared with an OS operational amplifier (such as a source-grounded output two-stage operational amplifier shown in FIG. 3), the output impedance is high by about three digits. Therefore, the common mode feedback circuit as shown in FIG. 3 cannot be used.

An example of using the circuit of FIG.
R. NORSWORTHY et al. "A 14bit 80kHz Sigma-Delta A / D Con
verter: Modeling, Design, and Performance Evaluatio
n ", IEEE Jour. of Solid-State Circuits, Vol.24, No.
2, 1989, pp256-266, D.SALLAERT et al., "A single-chip"
U-Interface Transceiver for ISDN ", IEEE Jour.of So
lid-State Circuits, vol.22, No.6, 1987, pp1011-102
There is 1 mag.

Next, the Hold Cascode type operational amplifier shown in FIG. 4 will be described.

In the figure, 81 to 87 are n-channel transistors,
88 to 93 are p-channel transistors, Vb9 to Vb12 are bias voltage input terminals, IP and IM are positive input terminals and negative input terminals of the operational amplifier, and OP and OM are positive output terminals and negative output terminals of the operational amplifier, respectively. .. As aforementioned,
The Holded Cascode type operational amplifier has a very high output impedance, so it is difficult to connect a load directly between the differential outputs. Therefore, in FIG. 4, the in-phase feedback circuit is configured by directly feeding back the differential output to the gates of the two current source transistors 92 and 93 whose drains are commonly connected. In this case, the differential output appearing between the terminals OP and OM is voltage-current converted by the transistors 92 and 93, and current addition is performed at the drains of the transistors 92 and 93.
As a result, the differential output voltages are equivalently added and fed back to the current source, and the DC operating point is stabilized.

[0011]

In the conventional Hold Cascode type operational amplifier using the common mode feedback circuit, since the output voltage is directly fed back to the gate of the current source transistor, one of the current source transistors is operated in a large amplitude operation. Since there is a cutoff region, there is a drawback that the output dynamic range is narrow. There is also a problem that a large common-mode noise is generated due to the influence of the non-linearity of the current source.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an operational amplifier using a common-mode feedback circuit having a wide output dynamic range and a small common-mode noise.

[0013]

A differential operational amplifier according to the present invention comprises a differential amplifier circuit, two buffer circuits for receiving differential outputs of the differential operational amplifier circuit, and the two buffer circuits. A voltage divider circuit that divides the output of the circuit to output the midpoint potential, and a circuit that amplifies the difference between the output of the voltage divider circuit and the reference voltage and feeds back to the gate of the current source transistor of the differential amplifier circuit , The two buffer circuits each have a source connected to a first power supply, a gate connected to a corresponding differential output terminal of the differential amplifier circuit, and a drain connected to the voltage dividing circuit. And a source connected to a second power supply, a gate connected to the corresponding differential output terminal, and a drain connected to the voltage dividing circuit.
A channel transistor, and a second gate having a gate and a drain connected to the voltage dividing circuit and a source connected to the first power supply.
And a second n-channel transistor whose gate and drain are connected to the voltage dividing circuit and whose source is connected to the second power supply.

In the above structure, for example, the first power supply is set to the power supply voltage Vdd and the second power supply is set to the ground voltage GND, and the first p-channel transistor and the first n-channel transistor forming one buffer circuit are set. Is connected to the positive output terminal, and the gates of the first p-channel transistor and the first n-channel transistor forming the other buffer circuit are connected to the negative output terminal. The second p-channel transistor and the second n-channel transistor are diode-connected, respectively.

[0015]

In the present invention, each buffer circuit is a CMO.
This is an inverting buffer that combines an S inverter and a diode-connected MOS transistor, and can realize a common-mode feedback circuit that can operate in the entire power supply voltage range. Further, since the midpoint potential of the differential output is fed back to the current source transistor, the influence of the non-linearity of the buffer circuit is small. Further, since the reference voltage is used, it is possible to suppress the fluctuation of the DC operating point due to the process fluctuation.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numerals 1 to 7 and 1
2 to 20 are n-channel transistors, 8 to 11 and 29
˜28 are p-channel transistors, R1 and R2 are resistors, CL1 and CL2 are load capacitors, Vb1 to Vb4 are bias voltage input terminals, VR is a reference voltage input terminal, and IP and I.
M indicates the positive input terminal and the negative input terminal of the operational amplifier, respectively, and OP and OM indicate the positive output terminal and the negative output terminal of the operational amplifier, respectively.

In the circuit shown in FIG. 1, the transistors 1 to 11 form a normal Hold Cascode type operational amplifier shown in FIG. 4, and the transistors 12 to 28 and the resistors R1 and R2 form a common-mode feedback circuit.

This common mode feedback circuit includes a transistor 12,
A first inverting buffer circuit composed of 21, 13, 22 and a second inverting buffer circuit composed of transistors 17, 25, 18, 26, and transistors 18, 26,
A third inverting buffer circuit composed of 19, 27, a differential pair composed of transistors 14-16, 23, 24, and a resistance voltage dividing circuit composed of resistors R1, R2.

The first inverting buffer circuit includes CMOS inverters 12 and 21 connected between a power supply voltage Vdd and a ground voltage GND, a diode-connected n-channel transistor 13 and a p-channel transistor 22 serving as loads of the CMOS inverter. It consists of CMOS
The reference voltage VR is supplied to the gates of the transistors 12 and 21 forming the inverter.

The second inverting buffer circuit has a power supply voltage Vd.
It is composed of CMOS inverters 17 and 25 connected between d and the ground voltage GND, a diode-connected n-channel transistor 18 and a p-channel transistor 26 which are loads of the CMOS inverter. The gates of the transistors 17 and 25 forming the CMOS inverter are connected to the positive output terminal OP.

The third inverting buffer circuit has a power supply voltage Vd.
It is composed of CMOS inverters 20 and 28 connected between d and the ground voltage GND, a diode-connected n-channel transistor 19 and a p-channel transistor 27 which are loads of the CMOS inverter. The negative output terminal OM is connected to the gates of the transistors 20 and 28 forming the CMOS inverter.

The resistance voltage dividing circuits R1 and R2 are connected between the output points of the second and third inverting buffer circuits.

The output of the first inverting buffer circuit is connected to the gates of the transistors 15 forming a differential pair, and resistors R1 and R2 are provided.
Are connected to the gates of the transistors 16 forming the differential pair. Further, the voltage Vb4 is applied to the gate of the transistor 14. The output of the differential pair is
Holded Cascode type operational amplifier current source transistor 1
It is applied to the gates of 0 and 11.

Next, the operation of the operational amplifier configured as described above will be described.

In the configuration of FIG. 1, the gain and threshold voltage of each inverting buffer are determined by the size of four transistors forming the inverting buffer. In this embodiment, the gain is 1 or less and the threshold voltage is approximately Vdd /
The transistor size is chosen to be 2. By setting the gain of the inverting buffer to 1 or less, it is possible to configure a buffer whose output is not saturated with respect to the input in the entire power supply voltage range.

The second inverting buffer circuit inverts and amplifies the positive output of the operational amplifier and outputs it. The third inverting buffer circuit inverts and amplifies the negative output of the operational amplifier and outputs it. By connecting the resistance voltage dividing circuits R1 and R2 between the output terminals OP and OM via the second and third inverting buffers, the midpoint potential can be detected without degrading the characteristics of the operational amplifier.

The reference voltage VR is a reference voltage that gives a DC operating point of the operational amplifier, and this reference voltage is input to the differential pair via the first inverting buffer. With this differential pair,
The outputs of the resistance voltage dividing circuits R1 and R2 (the potential at the connection point of R1 and R2) are compared with the reference voltage VR via the first inverting buffer, and the voltage obtained by inverting and amplifying the difference is output. The outputs of this differential pair are the current source transistors 10 and 1 of the operational amplifier.
It is returned to 1 and the DC operating point is stabilized.

The reason why the reference voltage VR is used is to suppress the fluctuation of the DC operating point due to the process fluctuation. Further, the reason for disposing the first inverting buffers 12, 13, 21, 22 between the reference voltage VR and the differential pairs 14-16, 23, 24 is that the second and third inverting buffers 17-20, 25.
This is to remove the offset generated at −28.

Next, a second embodiment of the present invention will be described. FIG. 2 realizes the resistance voltage dividing resistance of FIG. 1 by utilizing the on resistance of a MOS transistor. In the figure, 49,
Reference numeral 50 is an n-channel transistor, and 59 and 60 are p-channel transistors, and these four transistors form a voltage dividing circuit. The reason for connecting the n-channel transistor and the p-channel transistor in parallel is to cancel the voltage dependence of the on-resistance. As described above, by using the MOS transistor instead of the resistor, high resistance can be realized in a small area, and the common-mode feedback circuit can be downsized.

The above-mentioned first and second embodiments are the Holded Casc
Although the present invention is applied to an ode type operational amplifier, the present invention may be applied to other fully differential operational amplifiers. For example, even in the two-stage operational amplifier shown in FIG. 3, a low power consumption type has a high output impedance. By using the common mode feedback circuit according to the present invention, it is possible to prevent characteristic deterioration due to connection of the common mode feedback circuit.

Next, the operation of the present invention will be described using simulation results. FIG. 5 shows a circuit configuration of the fully differential inverting amplifier. In the figure, 100 is a fully differential operational amplifier, R5 to R8.
Indicates resistance. As described above, the Hold Cascode type operational amplifier has a very high output impedance, and therefore is rarely used in such a resistance feedback type circuit. Therefore, in order to confirm the characteristics, use the circuit of FIG.
In order to avoid the influence of the output impedance, all the resistance values were simulated with 100 MΩ.

FIGS. 6 and 7 show DC input / output characteristics of the operational amplifier of the conventional example (FIG. 4) and the operational amplifier of the present application (FIG. 1), respectively. In the figure, OP and OM represent the positive output and negative output of the operational amplifier, respectively, and OP-OM represents the differential output.

As is apparent from FIGS. 6 and 7, the output operation range of the characteristic shown in FIG. 7 is wider than the characteristic of the conventional example shown in FIG. Further, comparing the linearity of OP and OM, it can be seen that the present invention is superior. The effect of this non-linearity appears in the form of common-mode noise.

A differential sine wave input is added to the circuit of FIG. 5 to simulate the in-phase noise. The results are shown in FIGS. 8 and 9. FIG. 8 shows a simulation result when the conventional (FIG. 4) operational amplifier is used, and FIG. 9 shows a simulation result when the operational amplifier of the present application (FIG. 1) is used. O in the figure
P and OM indicate the positive output and the negative output of the operational amplifier, respectively, and COM indicates the common mode noise (midpoint waveform of OP and OM).

As is apparent from FIGS. 8 and 9, the common mode noise COM of the present application shown in FIG. 9 is smaller than the common mode noise COM of the conventional example shown in FIG. In the case of a fully differential circuit, this common mode noise is ideally not a problem. However, considering the signal path due to parasitic capacitance and the like, the symmetry of the fully differential circuit is not completely maintained, and the in-phase noise becomes anti-phase noise due to wraparound and the like, which deteriorates the S / N of the circuit. Since such effects depend on the circuit configuration, layout, etc.,
Although it cannot be expressed quantitatively, it is better to minimize common-mode noise as much as possible. Also in this respect, the present invention is superior to the conventional example.

FIG. 10 is a result of simulating the DC input / output characteristics of the operational amplifier of the second embodiment of FIG. 2 of the present invention, showing that the characteristics similar to those of the first embodiment can be obtained. There is.

[0038]

As described above, the present invention is a CMOS
By using an inverting buffer in which an inverter and a diode-connected MOS transistor are combined, a common-mode feedback circuit that can operate in the entire power supply voltage range can be realized. As a result, the differential output range of the operational amplifier is increased as compared with the conventional one. Further, in the past, a large common-mode noise is generated due to the non-linearity of the current source transistor, but in the present invention, since the midpoint potential of the differential output is fed back to the current source transistor, the influence of the non-linearity is small. In the case of the present invention, the common mode noise is generated due to the influence of the non-linearity of the inverting buffer, but the value is sufficiently smaller than the conventional common mode noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a Hold Cascode type operational amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a Hold Cascode type operational amplifier according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional two-stage operational amplifier.

FIG. 4 is a circuit diagram showing a configuration of a conventional Hold Cascode type operational amplifier.

FIG. 5 is a circuit diagram of a conventional fully differential inverting amplifier circuit.

6 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG.

FIG. 7 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG.

8 is a graph showing a simulation result of common mode noise of the operational amplifier of FIG.

9 is a graph showing a simulation result of common mode noise of the operational amplifier of FIG.

10 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG.

[Explanation of symbols]

IP; Positive input terminal IM; Negative input terminal OP; Positive output terminal OM; Negative output terminal VR; Reference voltage input terminal Vb1 to Vb12; Bias voltage input terminal CL1 to CL6; Load capacitance R1 to R8; Resistor INP; Positive input INM ; Negative input 1-7, 12-20, 31-37, 42-52, 71-
75, 81-87; n-channel transistors 8-11, 21-28, 38-41, 53-62, 76
-79, 88-93; p-channel transistor 100; fully differential operational amplifier

Claims (1)

[Claims] 1. A differential amplifier circuit, two buffer circuits for inputting differential outputs of the differential amplifier circuit, and a voltage divider for dividing outputs of the two buffer circuits to output a midpoint potential. A circuit for amplifying a difference between the output of the voltage dividing circuit and the reference voltage and feeding back to the gate of the current source transistor of the differential amplifier circuit, wherein the two buffer circuits each have a source as a first source. Connected to the power source of the differential amplifier, the gate thereof is connected to the corresponding differential output terminal of the differential amplifier circuit, and the drain thereof is connected to the voltage dividing circuit.
A p-channel transistor, a source connected to a second power supply, a gate connected to the corresponding differential output terminal, and a drain connected to the voltage dividing circuit, and a gate and a drain connected to the first n-channel transistor. Connected to the voltage divider circuit,
A second p-channel transistor whose source is connected to the first power supply, and a second n-channel transistor whose gate and drain are connected to the voltage dividing circuit and whose source is connected to the second power supply. A differential operational amplifier characterized by the above.