JPH0527261B2 - - Google Patents
Info
- Publication number
- JPH0527261B2 JPH0527261B2 JP58236154A JP23615483A JPH0527261B2 JP H0527261 B2 JPH0527261 B2 JP H0527261B2 JP 58236154 A JP58236154 A JP 58236154A JP 23615483 A JP23615483 A JP 23615483A JP H0527261 B2 JPH0527261 B2 JP H0527261B2
- Authority
- JP
- Japan
- Prior art keywords
- guide
- resin
- lead
- header
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011347 resin Substances 0.000 claims abstract description 64
- 229920005989 resin Polymers 0.000 claims abstract description 64
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005452 bending Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、絶縁型パワートランジスタの製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing an insulated power transistor.
レジンバツケージ型半導体装置（トランジス
タ）の一つとして、電子材料、1981年11月号、42
〜46頁にも記載されているように、絶縁型のパワ
ートランジスタが知られている。このトランジス
タは、放熱用のヘツダの主面に半導体素子（チツ
プ）が固定されるとともに、ヘツダの上面および
下面さらにはヘツダに設けられた取付孔内周面が
レジンで被われた構造となつている。ヘツダの下
面のレジンは熱抵抗が大きくならないように極め
て薄く形成されている。
As a resin bag-type semiconductor device (transistor), Electronic Materials, November 1981 issue, 42
As described on pages 46 to 46, insulated power transistors are known. This transistor has a structure in which a semiconductor element (chip) is fixed to the main surface of a heat dissipating header, and the top and bottom surfaces of the header as well as the inner peripheral surface of the mounting hole provided in the header are covered with resin. There is. The resin on the bottom surface of the header is made extremely thin so as not to increase thermal resistance.
しかし、このような絶縁型のパワートランジス
タはヘツダに連る細いガイド（フレーム支え）端
部がレジンハツケージから突出するため、電子機
器等に組み込んだ場合、隣接する電子部品等の導
電体部分にこのガイド端部が近接すると、放電を
生じるおそれがあり、高密度実装ができにくくな
るという問題が生じることが、本発明者によつて
あきらかとされた。 However, in such isolated power transistors, the thin guide (frame support) end that connects to the header protrudes from the resin cage, so when it is incorporated into electronic equipment, it may come into contact with the conductive parts of adjacent electronic components. The inventor of the present invention has found that if the guide ends are brought close together, there is a risk of electric discharge occurring, making it difficult to perform high-density packaging.
また、前記ガイドは、レジンモールド後のリー
ドフレームの一部を切断してリードフレームの枠
部からレジンパツケージを切り離す際に、ガイド
の突出長さを短かくするために、切断箇所はでき
るだけレジンパツケージの外表面に近接した位置
が選ばれる。この結果、切断時の外力がこのガイ
ドに大きく加わることから、レジンパツケージを
形作るレジンとガイドとの界面にクラツクが入
り、耐湿性が低下するという問題も生じるという
ことが本発明者によつてあきらかとされた。 In addition, when cutting a part of the lead frame after resin molding and separating the resin package cage from the frame of the lead frame, the guide should be cut as close to the resin package cage as possible in order to shorten the protruding length of the guide. A location close to the outer surface of is chosen. As a result, the inventor has found that a large external force is applied to this guide during cutting, which causes cracks at the interface between the resin and the guide that form the resin package, resulting in a problem of reduced moisture resistance. It was said that
本発明の目的は、他の導体物に近接して実装が
できる高耐圧の絶縁型パワートランジスタの製造
方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a high-voltage insulated power transistor that can be mounted close to other conductive objects.
本発明の他の目的は、絶縁型パワートランジス
タの取付板とガイドの絶縁が維持され、高電圧使
用でも放電が起きなくすることが可能な技術を提
供することにある。 Another object of the present invention is to provide a technique that maintains the insulation between the mounting plate and the guide of an insulated power transistor and prevents discharge from occurring even when high voltage is used.
本発明の他の目的は、耐湿性の優れた絶縁型パ
ワートランジスタの製造方法を提供することにあ
る。 Another object of the present invention is to provide a method for manufacturing an insulated power transistor with excellent moisture resistance.
本発明の前記ならびにそのほかの目的と新規な
特徴は、本明細書の記述および添付図面からあき
らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば、下記のとおりであ
る。
A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明の絶縁型パワートランジスタ
の製造方法は、その製造に用いられるリードフレ
ームの枠部に連るガイドの分断箇所に、あらかじ
めＶ字溝をその幅員全域に亘つて設けておくこと
から、レジンモールド時にヘツダの下面と同一側
となるガイド下面および側面をもレジンで被つて
も、枠部等を上方に突き上げることによつて、ガ
イドをレジン上に載る分断箇所で応力集中を利用
して容易かつ確実に分断することができる。この
結果、本発明のトランジスタはガイドの下面およ
び側面には絶縁効果の大きいレジンが存在し、か
つガイドの先端はレジンパツケージの周面よりも
内側に深く引つこんでいることから、トランジス
タ実装時の取付板とガイドとの絶縁が維持され、
高電圧使用でも放電が起きなくなり、耐圧向上が
図れる。 That is, in the method for manufacturing an insulated power transistor of the present invention, a V-shaped groove is previously provided over the entire width of the guide connected to the frame of the lead frame used for manufacturing the same. Even if the lower and side surfaces of the guide, which are on the same side as the lower surface of the header, are covered with resin during resin molding, by pushing up the frame etc., stress concentration can be utilized at the part where the guide rests on the resin. It can be separated easily and reliably. As a result, in the transistor of the present invention, resin with a high insulating effect exists on the lower and side surfaces of the guide, and the tip of the guide is recessed deeper inside than the peripheral surface of the resin package cage, so when mounting the transistor, The insulation between the mounting plate and the guide is maintained.
Even when high voltage is used, no discharge occurs and the withstand voltage can be improved.
また、本発明のトランジスタは、リードフレー
ムからのガイドの分断が、ガイドの分断箇所に設
けられたくびれ部分を利用して分断されるため、
ガイドには大きな応力は加わらず、レジンとガイ
ドとの密着性は良好な状態が維持されることから
耐湿性の向上が達成できる。 Further, in the transistor of the present invention, the guide is separated from the lead frame using the constricted portion provided at the part where the guide is separated.
No large stress is applied to the guide, and good adhesion between the resin and the guide is maintained, making it possible to improve moisture resistance.
第１図ａ〜ｄは本発明の一実施例による絶縁型
パワートランジスタの製造方法を示す斜視図およ
び断面図である。
1A to 1D are a perspective view and a sectional view showing a method of manufacturing an insulated power transistor according to an embodiment of the present invention.
本実施例の絶縁型パワートランジスタは第１図
ｄに示すように、略矩形のレジンパツケージ（樹
脂封止パツケージ）１と、このレジンパツケージ
１の一端面から突出する３本のリード２とからな
つている。また、レジンパツケージ１にはトラン
ジスタの実装時にねじを挿し込む取付孔３が設け
られている。この取付孔３は絶縁性のレジンパツ
ケージ１によつて形成されている。 As shown in FIG. 1d, the insulated power transistor of this embodiment consists of a substantially rectangular resin package (resin-sealed package) 1 and three leads 2 protruding from one end surface of the resin package 1. ing. Further, the resin package 1 is provided with a mounting hole 3 into which a screw is inserted when mounting a transistor. This mounting hole 3 is formed by an insulating resin package 1.
つぎに、第１図ａ〜ｄを参照しながら、このト
ランジスタの製造方法（組立方法）について説明
しながら、このトランジスタの細部について説明
する。 Next, details of this transistor will be explained while explaining a manufacturing method (assembling method) of this transistor with reference to FIGS. 1a to 1d.
このトランジスタの組立にあつては、第１図ａ
に示すようなリードフレーム４が用いられる。こ
のリードフレーム４は放熱性の優れた金属板、た
とえば銅板を精密プレス等でパターニングして形
成される。この金属板は板厚が部分的に異る異形
板となつている。このため、リードフレーム４の
後述するヘツダ５は厚く、その他のヘツダ５の両
端側に延在する、リードフレーム２およびガイド
６等は薄く、かつヘツダ５、リード２、ガイド６
の上面（主面）は同一面となつている。したがつ
て、ガイド６およびリード２の下面はヘツダ５の
下面よりも高い位置にある。これは、リード２が
レジンパツケージ１の中間高さから突出するよう
にするためと、リード２およびガイド６によつて
レジンモールド時にヘツダ５をモールド型のキヤ
ビテイ内に浮かせ、ヘツダ５の下面にもレジンが
流れ込むようにするためである。 When assembling this transistor, please refer to Figure 1a.
A lead frame 4 as shown in is used. This lead frame 4 is formed by patterning a metal plate with excellent heat dissipation properties, such as a copper plate, using a precision press or the like. This metal plate is an irregularly shaped plate with partially different thicknesses. For this reason, the header 5, which will be described later, of the lead frame 4 is thick, and the other lead frames 2, guides 6, etc. that extend to both ends of the header 5 are thin, and the headers 5, leads 2, guides 6, etc.
The upper surfaces (principal surfaces) of are the same surface. Therefore, the lower surfaces of the guide 6 and the leads 2 are located at a higher position than the lower surface of the header 5. This is so that the leads 2 protrude from the middle height of the resin package 1, and also because the leads 2 and guides 6 float the header 5 in the cavity of the mold mold during resin molding, and the lower surface of the header 5 is also This is to allow the resin to flow.
つぎに、リードフレーム４の具体的形状につい
て説明する。すなわち、リードフレーム４は細い
枠部７と、この枠部７の一側から平行に延在する
３本のリード２（中央はコレクタ用リード、両側
はエミツタ・ベース用リード）を有している。３
本のリード２は前記枠部７と平行に延在する細い
ダム片８によつて連結されている。 Next, the specific shape of the lead frame 4 will be explained. That is, the lead frame 4 has a thin frame portion 7 and three leads 2 extending in parallel from one side of the frame portion 7 (the center lead is a collector lead, and both sides are emitter/base leads). . 3
The book lead 2 is connected by a thin dam piece 8 extending parallel to the frame 7.
このダム片８はリードフレーム４の取り扱い時
には補強部材の役割を果たし、レジンモールド時
には注入されたレジンの流出を防止するダムの約
割を果たす。両側のリード２の先端部分は部分的
にくびれるとともに、先端は幅広となり、ワイヤ
接続部９を構成している。前記細いくびれは、レ
ジンパツケージ１内にリード２の先端が位置した
際、レジンにワイヤ接続部９が喰い込んで抜けな
いようにするために設けられている。 This dam piece 8 plays the role of a reinforcing member when handling the lead frame 4, and plays approximately 10% of the role of a dam that prevents the injected resin from flowing out during resin molding. The ends of the leads 2 on both sides are partially constricted and wide, forming a wire connection part 9. The narrow constriction is provided to prevent the wire connection portion 9 from biting into the resin and coming out when the tip of the lead 2 is located inside the resin package cage 1.
一方、中央のリード２は厚くかつ幅広のヘツダ
５に連なつている。このヘツダ５はリード２に近
い幅広のチツプ取付部１０と、このチツプ取付部
１０よりもわずかに幅が狭く中央に貫通孔１１を
有する取付孔形成部１２とからなつている。この
貫通孔１１は前記レジンパツケージ１の取付孔３
よりも直径が大きくなつている。貫通孔１１と取
付孔３の間のレジンは取付孔３に挿入するねじと
ヘツダ５との間の絶縁部材となることから、必要
な耐圧に合せて貫通孔１１と取付孔３の直径を選
択する必要がある。また、ヘツダ５の取付孔形成
部１２側の先端にはダム片８および枠部７と平行
に延在する細いガイド６が設けられている。この
ガイド６の取付孔形成部１２側面から外れかつチ
ツプ取付部１０の側面の内側に位置するして幅員
に沿つてＶ字断面の溝１３が設けられ応力集中が
生じ易くなつている。 On the other hand, the central lead 2 is connected to a thick and wide header 5. This header 5 consists of a wide chip mounting part 10 close to the lead 2, and a mounting hole forming part 12 which is slightly narrower than the chip mounting part 10 and has a through hole 11 in the center. This through hole 11 is the mounting hole 3 of the resin package 1.
The diameter is larger than that of the Since the resin between the through hole 11 and the mounting hole 3 serves as an insulating member between the screw inserted into the mounting hole 3 and the header 5, select the diameters of the through hole 11 and the mounting hole 3 according to the required pressure resistance. There is a need to. Further, a thin guide 6 extending parallel to the dam piece 8 and the frame portion 7 is provided at the tip of the header 5 on the attachment hole forming portion 12 side. A groove 13 having a V-shaped cross section is provided along the width of the guide 6, which is located outside the side surface of the mounting hole forming portion 12 and inside the side surface of the chip mounting portion 10, so that stress concentration is likely to occur.
このようなリードフレーム４を用いてトランジ
スタを組立てる場合には、第１図ａに示すよう
に、リードフレーム４のチツプ取付部１０にチツ
プ（半導体素子）１４が固定される。つぎに、チ
ツプ１４の電極と所定リード２の先端とはワイヤ
１５で電気的に接続される。その後、ダム片８か
ら先端のヘツダ部分はレジンモールドされる。こ
の際、第１図ｂで示すように、リードフレーム４
は反転状態でモールド型の下型１６と上型１７間
に挟持されて保持され、キヤビテイ１８内にレジ
ン１９が注入されることによつて、第１図ｃに示
すようにレジンパツケージ１で部分的に被われ
る。レジンパツケージ１はリードフレーム４の貫
通孔１１に対応する位置に貫通孔１１よりも直径
の小さな取付孔３が設けられる必要があることか
ら、この取付孔３に対応する上・下型１７，１６
部分はキヤビテイとはなつていない。また、ガイ
ド６の溝１３が設けられた上面部分は、第１図ｂ
の破線で示すように下型１６によつて支えられる
ため、第１図ｃで示すように、レジンパツケージ
１の隅部に形成された窪み２０の底に露出する。 When assembling a transistor using such a lead frame 4, a chip (semiconductor element) 14 is fixed to a chip mounting portion 10 of the lead frame 4, as shown in FIG. 1a. Next, the electrode of the chip 14 and the tip of the predetermined lead 2 are electrically connected by a wire 15. Thereafter, the header portion from the dam piece 8 to the tip is resin molded. At this time, as shown in FIG. 1b, the lead frame 4
is held between the lower die 16 and the upper die 17 of the mold in an inverted state, and by injecting the resin 19 into the cavity 18, the resin package 1 is partially formed as shown in FIG. 1c. covered. Since the resin package 1 needs to have a mounting hole 3 smaller in diameter than the through-hole 11 at a position corresponding to the through-hole 11 of the lead frame 4, the upper and lower molds 17, 16 corresponding to this mounting hole 3 must be provided.
The part is not aligned with the cavity. In addition, the upper surface portion of the guide 6 where the groove 13 is provided is shown in FIG.
Since it is supported by the lower mold 16 as shown by the broken line, it is exposed at the bottom of the depression 20 formed at the corner of the resin package 1, as shown in FIG. 1c.
上・下型１７，１６は逆でもよいが、この実施
例の場合にはガイド６の宙吊り長さが短かくな
り、キヤビテイ内におけるヘツダ５の高さが最も
安定すると考えられる。このレジンモールド時、
トランジスタの熱放散性を良好とするために、ヘ
ツダ５の下面に設けられるレジンの厚さは所望の
絶縁性を維持する範囲でできるだけ薄く、かつ均
一厚さとなるようにする必要がある。 Although the upper and lower molds 17 and 16 may be reversed, in this embodiment, the suspended length of the guide 6 is shortened, and the height of the header 5 within the cavity is considered to be the most stable. When using this resin mold,
In order to improve the heat dissipation properties of the transistor, the thickness of the resin provided on the lower surface of the header 5 needs to be as thin as possible and uniform within a range that maintains the desired insulation properties.
つぎに、第１図ｃに示すように、レジンパツケ
ージ１の側面から突出するガイド６は矢印で示す
ように、上方に突き上げられ窪み２０の壁側に折
り曲げられ、前記壁によつて固定された溝１３部
分で応力集中のため分断される。また、リードフ
レーム４の不要部分、すなわち、ダム片８および
枠部７は切断除去され、第１図ｄに示すようなト
ランジスタが製造される。 Next, as shown in FIG. 1c, the guide 6 protruding from the side surface of the resin package cage 1 is pushed upward as shown by the arrow, bent toward the wall of the recess 20, and fixed by the wall. The groove 13 is divided due to stress concentration. Further, unnecessary portions of the lead frame 4, ie, the dam piece 8 and the frame portion 7, are cut and removed, and a transistor as shown in FIG. 1d is manufactured.
(1) 本発明の絶縁型トランジスタはガイド６の下
面および側面は絶縁性のレジン１９で被われて
いる。また、ガイド６の先端はレジンパツケー
ジ１の側面から奥深く内側に引つ込んでいる。
また、ガイド６の上面はレジンパツケージ１の
主たる上面よりも低い窪み２０の底面に位置し
ている。この結果、トランジスタを図示しない
導電性の取付板上に載置固定しても、コレクタ
電位と等電位となるガイド６と取付板間には絶
縁性のレジン１９が介在しかつガイド６の周面
部分は取付板に対して遮蔽されるため、放電は
起きなくなり、トランジスタの高耐圧化にも充
分対応できる高い絶縁性が達成できる。これに
より、絶縁型パワートランジスタ実装時の取付
板とガイド６との絶縁が維持され高電圧使用で
も放電が起きなくなり、耐圧向上を計ることが
できる。例えば、コンピユータの電源回路に用
いられるものにおいては、絶縁型パワートラン
ジスタのコレクタ電極と同電位にあるガイド６
は、取付板との間に400ボルト程度の電圧が印
加される場合がある。このような場合の電圧に
も耐えることができる。
(1) In the insulated transistor of the present invention, the lower and side surfaces of the guide 6 are covered with an insulating resin 19. Further, the tip of the guide 6 is recessed deeply inward from the side surface of the resin package cage 1.
Further, the upper surface of the guide 6 is located at the bottom surface of the recess 20 which is lower than the main upper surface of the resin package 1. As a result, even if the transistor is placed and fixed on a conductive mounting plate (not shown), the insulating resin 19 is interposed between the guide 6 and the mounting plate, which have the same potential as the collector potential, and the circumferential surface of the guide 6 Since the portion is shielded from the mounting plate, no discharge occurs, and high insulation properties sufficient to support higher voltage resistance of transistors can be achieved. This maintains the insulation between the mounting plate and the guide 6 when the insulated power transistor is mounted, prevents discharge from occurring even when high voltage is used, and improves the withstand voltage. For example, in a power supply circuit for a computer, a guide 6 that is at the same potential as the collector electrode of an insulated power transistor is used.
A voltage of approximately 400 volts may be applied between the unit and the mounting plate. It can withstand voltages in such cases.
(2) 上記(1)で示すように、ガイド６の周面はレジ
ンパツケージ１の周面から内方に引つ込んでい
る。このため、トランジスタの実装時レジンパ
ツケージ１の周面に接触するように、他の導電
体を配置しても、この導電体とガイド周面との
間にはレジンあるいは空気による充分な絶縁体
が介在するため、放電は起きなくなり、トラン
ジスタの近接実装による高密度実装化が達成で
きる。(2) As shown in (1) above, the circumferential surface of the guide 6 is recessed inward from the circumferential surface of the resin package 1. Therefore, even if another conductor is placed in contact with the circumferential surface of the resin package 1 when a transistor is mounted, there is sufficient insulating material such as resin or air between this conductor and the circumferential surface of the guide. Because of this, no discharge occurs, and high-density packaging can be achieved by closely mounting transistors.
(3) 本発明のトランジスタはその製造時におい
て、レジンモールド後のガイド６の分断は、レ
ジンパツケージ１の窪み２０の壁に沿つてその
ガイド６に設けられた応力集中箇所（溝１３を
設けた箇所）を利用して行われる。すなわち、
ガイド６をレジンパツケージ１の窪み２０の壁
側に向けて折り曲げることで、その壁が押えと
なつて、壁に沿つた溝１３のところでガイド６
が分断する。この結果、ガイド６は弱い力によ
つて分断し、ガイド６には大きな応力が加わら
ない。(3) During manufacture of the transistor of the present invention, the guide 6 is separated after resin molding at stress concentration points (grooves 13) provided in the guide 6 along the wall of the recess 20 of the resin package 1. It is carried out using the following. That is,
By bending the guide 6 toward the wall of the recess 20 of the resin package cage 1, the wall acts as a presser and the guide 6 is bent at the groove 13 along the wall.
divides. As a result, the guide 6 is separated by a weak force, and no large stress is applied to the guide 6.
したがつて、ガイド分断時にガイド６とレジ
ン１９との間にクラツク等が入ることもなく、
両者の密着度は高く維持され、トランジスタの
高耐湿性が達成できる。 Therefore, no cracks or the like will occur between the guide 6 and the resin 19 when the guide is separated.
The degree of adhesion between the two is maintained high, and high moisture resistance of the transistor can be achieved.
(4) 従来のカツトパンチ等による剪断を行う場合
には、レジンパツケージ１に接した位置で切断
を行うために、通常の切断ではレジンパツケー
ジ１と切断箇所の間のリードによつて吸収され
る外力が直接にレジンパツケージ１に伝わつて
いたが、本発明では、前述のように折り曲げに
よつて分断するので、ガイド分断時にガイド６
とレジン１９との間にクラツク等が入ることも
なく、両者の密着度は高く維持され、トランジ
スタの高耐湿性が達成できる。(4) When performing shearing using a conventional cut punch, etc., the external force is absorbed by the lead between the resin package 1 and the cutting point in normal cutting because the cut is made at a position in contact with the resin package 1. was directly transmitted to the resin package cage 1, but in the present invention, the guide 6 is divided by bending as described above, so the guide 6 is
There are no cracks or the like between the substrate and the resin 19, and the degree of adhesion between the two is maintained at a high level, making it possible to achieve high moisture resistance of the transistor.
(5) 上記(1)〜(4)から、本発明によれば高性能高信
頼性のトランジスタの提供が達成できる。(5) From the above (1) to (4), according to the present invention, it is possible to provide a transistor with high performance and high reliability.
以上発明者によつてなされた発明を実施例にも
とづき具体的に説明したが、本発明な上記実施例
に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもな
い。第３図に示すような形状のリードフレーム４
を用いて第２図に示すように、レジンパツケージ
１の上面が三段となるように形成したトランジス
タであつても、前記実施例と同様な製造工程を経
て同様な効果が得られる。レジンパツケージ１の
最上面はチツプおよびワイヤ等を被うために必要
であり、最下段の上面は前記実施例と同様にヘツ
ダ５から延在するガイド６のレジンモールド時の
ヘツダ高さ決定の結果生じる。 Although the invention made by the inventor has been specifically explained above based on examples, it should be noted that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. Not even. Lead frame 4 shaped as shown in Fig. 3
As shown in FIG. 2, even if the transistor is formed so that the top surface of the resin package 1 has three stages, the same effects can be obtained through the same manufacturing process as in the previous embodiment. The uppermost surface of the resin package 1 is necessary for covering chips, wires, etc., and the upper surface of the lowermost layer is the result of determining the height of the header during resin molding of the guide 6 extending from the header 5 as in the previous embodiment. arise.
なお、この実施例では、ガイド６の変形例とし
て溝１３を有するガイド６はリード２の延在方向
に沿つて延び、かつその先端は他の枠部２１に連
なつている。また、中段の面には取付孔形成部１
２が形成されている。 In this embodiment, as a modified example of the guide 6, the guide 6 having the groove 13 extends along the extending direction of the lead 2, and its tip is connected to the other frame portion 21. In addition, there is a mounting hole forming part 1 on the middle surface.
2 is formed.
したがつて、このトランジスタは取付孔３を有
する面がレジンパツケージ１の最上面よりも一段
低くなつていることから、ねじを取り付けた際、
ねじ頭がレジンパツケージ１の最上面よりも突出
しない、あるいはわずかに突出するというように
なることから、実装高さが低くなり、多段状にこ
れらのトランジスタを組み込む電子機器類の背丈
低下が達成できる。 Therefore, since the surface with the mounting holes 3 of this transistor is one step lower than the top surface of the resin package 1, when the screws are attached,
Since the screw head does not protrude or protrudes slightly beyond the top surface of the resin package cage 1, the mounting height is lowered, and the height of electronic equipment incorporating these transistors in multiple stages can be reduced. .
また、この実施例ではリードフレーム４は一枚
の薄い金属板のパターニングおよび段付成形によ
つて形成されている。このため、リードフレーム
４のコストが異形材から製作する場合に比較して
安価となり、トランジスタ製造コストの低減化が
達成できる効果も奏する。 Further, in this embodiment, the lead frame 4 is formed by patterning and step forming a single thin metal plate. Therefore, the cost of the lead frame 4 is lower than that in the case where the lead frame 4 is manufactured from a deformed material, and there is also an effect that the transistor manufacturing cost can be reduced.
また、前記２つの実施例におけるリードフレー
ム４の溝１３は、いずれもヘツダ５のチツプ取付
面側に形成されているが、溝１３をチツプ取付面
側でなく、裏面に形成しても前記実施例と同様な
効果が得られる。 Furthermore, although the grooves 13 of the lead frame 4 in the two embodiments described above are both formed on the chip mounting surface side of the header 5, the grooves 13 may be formed on the back surface instead of the chip mounting surface side. The same effect as in the example can be obtained.
以上の説明では主として本発明者によつてなさ
れた発明をその背景となつた利用分野である技術
に適用した場合について説明したが、それに限定
されるものではなく、たとえば、ダイオード、集
積回路装置等他の半導体装置にも同様に適用でき
同様な効果が得られる。
The above explanation has mainly been about the application of the invention made by the present inventor to the technology that is the background field of application, but the invention is not limited to this, and examples include diodes, integrated circuit devices, etc. It can be similarly applied to other semiconductor devices and similar effects can be obtained.
第１図ａ〜ｄは本発明の一実施例による絶縁型
パワートランジスタの製造方法を示す斜視図およ
び断面図、第２図は他の実施例による絶縁型パワ
ートランジスタの斜視図、第３図は同じくその製
造に用いられるリードフレームの斜視図である。
１……レジンパツケージ、２……リード、３…
…取付孔、４……リードフレーム、５……ヘツ
ダ、６……ガイド、７……枠部、８……ダム片、
９……ワイヤ接続部、１０……チツプ取付部、１
１……貫通孔、１２……取付孔形成部、１３……
溝、１４……チツプ、１５……ワイヤ１６……下
型、１７……上型、１８……キヤビテイ、１９…
…レジン、２０……窪み、２１……枠部。
1A to 1D are perspective views and cross-sectional views showing a method of manufacturing an insulated power transistor according to an embodiment of the present invention, FIG. 2 is a perspective view of an insulated power transistor according to another embodiment, and FIG. FIG. 3 is a perspective view of a lead frame similarly used for manufacturing the same. 1...Resin package cage, 2...Lead, 3...
...Mounting hole, 4... Lead frame, 5... Header, 6... Guide, 7... Frame, 8... Dam piece,
9... Wire connection part, 10... Chip mounting part, 1
1...Through hole, 12...Mounting hole forming part, 13...
Groove, 14... Chip, 15... Wire 16... Lower die, 17... Upper die, 18... Cavity, 19...
...resin, 20...dent, 21...frame.
Claims (1)
延在する３本のリード２と、それらリード２に
連結し、前記枠部７と平行に延在するダム片８
と、前記３本のリード２の中央に位置したリー
ド２に連結し、主面にチツプ取付部１０及び貫
通孔１１を有する取付孔形成部１２とから成る
ヘツダ５と、前記取付孔形成部１２に連結し、
それぞれの主面に溝１３を有する一対のガイド
６とから成るリードフレーム４を用意する工程
と、 ｂ 前記チツプ取付部１０に半導体チツプ１４を
固定する工程と、 ｃ 前記半導体チツプ１４一主面に設けられた電
極と前記中央リード２の両側に位置したリード
２の先端とをワイヤ１５で接続する工程と、 ｄ モールドすべきリードフレーム４の部分に対
応して段部をもつたキヤビテイ１８を形作るモ
ールド上下型１６，１７により、前記モールド
上下型１６，１７の一方のモールド型１６で前
記溝１３が設けられた一対のガイド６主面を支
えるようにしてリードフレーム４を挾持し、そ
のモールド上下型１６，１７のキヤビテイ１８
内にレジン１９を注入し、前記半導体チツプ１
４、前記ワイヤ１５、前記ヘツダ５の一主面と
は反対の主面を含むヘツダ５全体をレジン１９
でモールドし、前記溝１３から先端側のガイド
６の上面が窪み２０の角部において露出するレ
ジンパツケージ１を形成する工程と、しかる
後、 ｅ 前記ガイド６を前記窪み２０の壁側に向かつ
て折り曲げ前記ガイド６の溝１３において分
断、および前記リード２に連結する前記ダム片
８および前記枠部７を切断除去する工程と、か
らなる絶縁型パワートランジスタの製造方法。[Claims] 1 a A frame portion 7, three leads 2 extending in parallel from one side of the frame portion 7, and three leads 2 connected to the leads 2 and extending parallel to the frame portion 7. Dam piece 8
and a header 5, which is connected to the lead 2 located at the center of the three leads 2 and has a chip mounting part 10 and a through hole 11 on its main surface, and a mounting hole forming part 12; connected to,
a step of preparing a lead frame 4 consisting of a pair of guides 6 having grooves 13 on each main surface; b. a step of fixing the semiconductor chip 14 to the chip mounting portion 10; c. a step of fixing the semiconductor chip 14 on one main surface. Connecting the provided electrodes with the ends of the leads 2 located on both sides of the central lead 2 using wires 15; d) Forming a cavity 18 having a stepped portion corresponding to the portion of the lead frame 4 to be molded; The upper and lower mold molds 16 and 17 hold the lead frame 4 in such a way that one of the upper and lower mold molds 16 supports the main surfaces of the pair of guides 6 provided with the grooves 13, and the upper and lower mold molds Cavity 18 of molds 16 and 17
A resin 19 is injected into the semiconductor chip 1.
4. The entire header 5 including the wire 15 and the main surface opposite to the one main surface of the header 5 is coated with resin 19.
molding to form a resin package 1 in which the upper surface of the guide 6 on the distal side from the groove 13 is exposed at the corner of the recess 20, and then e) directing the guide 6 toward the wall side of the recess 20. A method for manufacturing an insulated power transistor comprising the steps of bending and dividing the guide 6 at the groove 13, and cutting and removing the dam piece 8 and the frame portion 7 connected to the lead 2.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236154A JPS60128646A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device and lead frame used for manufacturing the same device |
| GB08429620A GB2151845A (en) | 1983-12-16 | 1984-11-23 | A semiconductor memory |
| KR1019840007370A KR930007518B1 (en) | 1983-12-16 | 1984-11-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236154A JPS60128646A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device and lead frame used for manufacturing the same device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60128646A JPS60128646A (en) | 1985-07-09 |
| JPH0527261B2 true JPH0527261B2 (en) | 1993-04-20 |
Family
ID=16996560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58236154A Granted JPS60128646A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device and lead frame used for manufacturing the same device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS60128646A (en) |
| KR (1) | KR930007518B1 (en) |
| GB (1) | GB2151845A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60172346U (en) * | 1984-04-23 | 1985-11-15 | 新電元工業株式会社 | Resin-sealed semiconductor device |
| JPS61207040U (en) * | 1985-06-17 | 1986-12-27 | ||
| JPS62180957U (en) * | 1986-05-06 | 1987-11-17 | ||
| JPH079917B2 (en) * | 1987-05-11 | 1995-02-01 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| JPH0824156B2 (en) * | 1987-05-25 | 1996-03-06 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| JPH0744194B2 (en) * | 1989-02-17 | 1995-05-15 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| US5028741A (en) * | 1990-05-24 | 1991-07-02 | Motorola, Inc. | High frequency, power semiconductor device |
| JP3598579B2 (en) * | 1995-04-17 | 2004-12-08 | 株式会社デンソー | Solenoid valve block |
| US20040113240A1 (en) | 2002-10-11 | 2004-06-17 | Wolfgang Hauser | An electronic component with a leadframe |
| JP4953205B2 (en) * | 2007-05-01 | 2012-06-13 | 三菱電機株式会社 | Semiconductor device |
| US11602055B2 (en) | 2018-09-04 | 2023-03-07 | Apple Inc. | Overmolded components having sub-flush residuals |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57188858A (en) * | 1981-05-18 | 1982-11-19 | Matsushita Electronics Corp | Plastic molded type semiconductor device |
| JPS58143538A (en) * | 1982-02-19 | 1983-08-26 | Matsushita Electronics Corp | Manufacture of resin seal type semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS615818Y2 (en) * | 1979-06-07 | 1986-02-21 | ||
| US4451973A (en) * | 1981-04-28 | 1984-06-05 | Matsushita Electronics Corporation | Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor |
-
1983
- 1983-12-16 JP JP58236154A patent/JPS60128646A/en active Granted
-
1984
- 1984-11-23 GB GB08429620A patent/GB2151845A/en not_active Withdrawn
- 1984-11-24 KR KR1019840007370A patent/KR930007518B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57188858A (en) * | 1981-05-18 | 1982-11-19 | Matsushita Electronics Corp | Plastic molded type semiconductor device |
| JPS58143538A (en) * | 1982-02-19 | 1983-08-26 | Matsushita Electronics Corp | Manufacture of resin seal type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR850005152A (en) | 1985-08-21 |
| GB2151845A (en) | 1985-07-24 |
| KR930007518B1 (en) | 1993-08-12 |
| GB8429620D0 (en) | 1985-01-03 |
| JPS60128646A (en) | 1985-07-09 |
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