JPH05235332A - Thyristor with insulated gate - Google Patents

Abstract

PURPOSE:To provide a thyristor with an insulated gate, the turn-OFF performance of which is improved. CONSTITUTION:In thyristor structure composed of a p-type emitter layer 4, an n-type base layer 1, a p-type base layer 2 and an n-type emitter layer 3, a drain electrode 8 brought into contact with the p-type base layer 2 is formed at a position adjacent to one side of the n-type emitter layer 3, and an n-type drain electrode 7 short-circuited with the p-type base layer 2 by the drain electrode 8 is shaped. An n-type source layer 11 is formed separated at a fixed distance from the n-type drain layer 7, and an insulated gate electrode 10 for turn-off is formed between these n-type source layer 11 and n-type drain layer 7. A source electrode 12 is connected to a cathode electrode 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thyristor with an insulated gate.

[0002]

2. Description of the Related Art A power IC in which a driving circuit and a protection circuit are integrally formed on a power element of high withstand voltage and large current,
It will become the mainstream of power devices in the future. For gate driving in such a power device, a voltage control type using an insulated gate electrode (MOS gate) is preferable. This is because the gate can be driven with a small current as compared with the current drive type.

FIG. 25 shows the structure of a turn-off insulated gate portion of a conventional insulated gate thyristor. High resistance n
The p-type base layer 2 is formed on one surface of the mold base layer 1,
An n-type emitter layer 3 is formed in this p-type base layer 2. A p-type emitter layer 4 is formed on the other surface of the n-type base layer 1. The cathode electrode 5 is provided on the n-type emitter layer 3.
However, an anode electrode 6 is formed on the p-type emitter layer 4.

An n-type drain layer 7 is formed at a predetermined distance from the n-type emitter layer 3 of the p-type base layer 2, and the p-type base layer between the n-type drain layer 7 and the n-type cathode layer 3 is formed. A gate electrode 10 is formed on the gate electrode 2 via a gate insulating film 9. The gate electrode 10 is for turn-off, and is an n-channel MOS with the n-type emitter layer as a source.
The FET is configured. The drain electrode 8 that contacts the n-type drain layer 7 is also in contact with the p-type base layer 2 at the same time, and the p-type base layer 2 and the n-type drain layer 7 are short-circuited by the drain electrode 8.

Although not shown in the drawing, a gate electrode for turn-on is formed, for example, in the peripheral portion of the p-type base layer 2 selectively diffused and formed, with a MOS structure similar to that for turn-off.

In the insulated gate thyristor having such a structure, a positive voltage with respect to the cathode is applied to the insulated gate electrode 10 at turn-off. Thereby, the gate electrode 1
N-type channel is formed below the n-type channel, and part of the hole current flowing from the p-type base layer 2 directly into the n-type emitter layer 3 is absorbed by the drain electrode 8 as shown by the broken line in the figure, and the n-type channel is formed. The n-type emitter layer 3 is bypassed to the cathode electrode 5 through the drain layer 7 and the channel below the gate electrode 10. Due to this bypass of the hole current, electron injection from the n-type emitter layer 3 to the p-type base layer 2 is stopped, and the device is turned off.

This conventional thyristor with an insulated gate has a problem that a sufficient turn-off ability cannot be obtained. This is due to the resistance of the Hall current bypass path shown by the broken line in FIG. The resistance of the hole current bypass path is mainly the lateral resistance of the p-type base layer 2 and the on-resistance of the channel below the insulated gate electrode 10. When the voltage drop determined by these resistances and the bypass current becomes equal to or higher than the built-in voltage between the n-type emitter layer 3 and the p-type base layer 2, the electron injection from the n-type emitter layer 3 is not stopped. Therefore, when the main current becomes large, it cannot be turned off.

Among integrated circuits (IC) in which a plurality of semiconductor elements are integrated on one semiconductor substrate, one including a high breakdown voltage element is called a power IC. Including a MOS gate generally used as the high breakdown voltage element (power MOS
FETs, IGBTs, etc. are usually DSA (diffusion se)
lf-alignment) structure to form the channel part. this is,
This is a method of forming a source diffusion layer and a channel diffusion layer of opposite polarity by using one end face of the same polysilicon gate electrode as a diffusion window.

FIG. 39 shows a cross section of a lateral power MOSFET manufactured by a conventional technique. First, using the polysilicon film to be the gate electrode 32 as a mask, impurities are diffused into the n-type substrate 31 from the left side of the position A (in the figure) to form the p-type channel layer 33. Next, impurities are diffused into the p-type channel layer 33 from the same location to form an n-type diffusion layer 34 serving as a source. At the same time, the n-type diffusion layer 35 to be the drain is simultaneously formed by diffusion. As a result, a lateral power MOSFET as shown in the figure is formed.

By the way, in a power IC, it is necessary to form a low breakdown voltage element such as CMOS for forming a logic circuit on the same substrate as such a high breakdown voltage element. FIG. 40 shows a cross section of an n-channel type low breakdown voltage MOSFET. First, p on the same n-type substrate 31 as the high breakdown voltage element
A type well diffusion layer 36 is formed. Next, the gate electrode 37
Using the polysilicon film to be the mask as a mask, n-type diffusion layers 38 and 39 to be the source and the drain are formed on both sides thereof. As a result, a low breakdown voltage MOSFET as shown in the figure is formed.

In the process of manufacturing the high breakdown voltage element and the low breakdown voltage element, the p-type channel layer 33 of the high breakdown voltage element and the p-type well diffusion layer 36 of the low breakdown voltage element are diffusion layers for forming a channel portion. is there. However, these need to be formed in separate steps for the following reasons. This is because the p-type channel portion of the high breakdown voltage element uses the lateral diffusion region of the diffusion layer, whereas the p-type channel portion of the low breakdown voltage element uses the vertical diffusion region of the diffusion layer. It is due to the essential difference. Therefore, both layers 33
And 36 differ in the amount of implant dose. Furthermore, since the p-type channel portion of the high breakdown voltage element uses the lateral diffusion region of the diffusion layer 33, the channel length L is determined by the diffusion depth. Therefore, it is necessary to design the diffusion depth of the high breakdown voltage element independently of the low breakdown voltage element.

As described above, the conventional lateral withstand voltage element used in the power IC has a manufacturing process independent from that of the low withstand voltage element which is integrated at the same time. There was a problem that the process had to be complicated.

[0013]

As described above, the conventional thyristor with an insulated gate has a problem that a large energizing current cannot be passed.

An object of the present invention is to provide a thyristor with an insulated gate capable of passing a larger current.

[0015]

A thyristor with an insulated gate according to the present invention is a high-resistance first conductivity type base layer, a first resistance type first base layer.
A second conductivity type base layer formed on one surface of the conductivity type base layer, a second conductivity type emitter layer connected to the second conductivity type base layer through the first conductivity type base layer, and a second conductivity type. P of the first conductivity type emitter layer formed in the type base layer
It has an npn structure.

In this basic structure, the present invention provides a first
A drain electrode is formed on the second conductive type base layer adjacent to the first conductive type emitter layer, and a first conductive type drain layer short-circuited with the second conductive type base layer by the drain electrode is formed. To be done. In the second conductivity type base layer,
A first conductivity type source layer is formed at a predetermined distance from the first conductivity type drain layer. A turn-off insulated gate electrode is formed on the second conductive type base layer between the first conductive type drain layer and the first conductive type source layer with a gate insulating film interposed therebetween. A first main electrode is formed on the second conductivity type emitter layer, a second main electrode is formed on the first conductivity type emitter layer, and the second main electrode is connected on the first conductivity type source layer. Characterized in that the formed source electrode is formed.

In the second aspect of the present invention, the first conductivity type emitter layer is divided into a plurality of layers, and the drain electrode is in contact with the second conductivity type base layer at a position adjacent to one side of the first conductivity type emitter layer. And a first conductivity type drain layer short-circuited with the second conductivity type base layer by the drain electrode is formed at a position adjacent to the other side of the first conductivity type emitter layer. A turn-off insulated gate electrode is provided between the first conductivity type emitter layers.

Thirdly, according to the present invention, the first conductive type first and second conductive layers are sandwiched between the second conductive type base layer and the first conductive type emitter layer.
A drain layer of the first conductivity type and a second conductivity type emitter layer
An insulated gate electrode is formed on the second conductivity type base layer between the drain layers, a first main electrode is on the second conductivity type emitter layer, and a second main electrode is on the first conductivity type emitter layer. Is formed, and a short-circuit electrode connecting the first and second drain layers is formed.

[0019]

In the conventional structure shown in FIG. 25, since the turn-off MOSFET is constructed with the n-type emitter layer as the source layer, the drain electrode n-type emitter layer for absorbing the hole current is formed separately. On the other hand, in the first invention, the n-type source layer and the n-type source layer of the turn-off MOSFET are
The type emitter layer is separated, and the drain layer and the drain electrode are formed adjacent to the n-type emitter layer. The drain electrode, which is a hole current sinking electrode at the time of turn-off, is also in direct contact with the p-type base layer in the immediate vicinity of the n-type emitter layer.

In the second invention, the n-type source layer and the n-type emitter layer are common as in the conventional case, but the n-type emitter layer is divided into a plurality of parts, and the n-type emitter layer and the n-type emitter layer are adjacent to one side thereof. A drain electrode that contacts the two-conductivity-type base layer is provided, and an n-type drain layer is provided adjacent to the other side.

Further, in the third invention, the n-type drain layers of the turn-on and turn-off MOSFETs are divided into the first and second drain layers with the n-type emitter layer interposed therebetween. As a result, the hole current when turned on flows directly into the cathode electrode without passing laterally under the n-type emitter layer.

Therefore, in the thyristor with an insulated gate according to the present invention, there is no lateral resistance of the p-type base layer in the hole current bypass path at the time of turn-off, which allows a larger energizing current to flow than in the conventional case. In addition, a thyristor with an insulated gate that can turn off even a large current can be obtained.

[0023]

1 shows the structure of the turn-off gate portion of a thyristor with an insulated gate according to the first embodiment of the present invention.
The parts corresponding to those in the conventional FIG. 25 are denoted by the same reference numerals as those in FIG. As is apparent from comparison with FIG. 25, in this embodiment, the drain electrode 8 is provided in contact with the p-type base layer 2 at a position adjacent to the n-type emitter layer 3. The n-type drain layer 7 is short-circuited with the p-type base layer 2 by the drain electrode 8. An n-type source layer 11 is formed at a predetermined distance from the n-type drain layer 7, and an insulated gate electrode 10 is formed between the drain layer 7 and the source layer 11. The source electrode 12 is formed integrally with the cathode electrode 5 and is electrically connected to the cathode electrode 5. The source electrode 12 is also arranged so as to contact the p-type base layer 2 at the same time as the drain electrode 8 in this embodiment. However, the source electrode 12 may be provided so as to contact only the source layer 11.

In the thyristor with an insulated gate of this embodiment, a positive voltage with respect to the cathode is applied to the insulated gate electrode 10 at turn-off. The bypass path of the Hall current at this time is shown by a broken line. As shown in the figure, a part of the hole current is absorbed by the drain electrode 8 in the immediate vicinity of the n-type emitter layer 3, passes through the channel under the gate electrode 10, and is discharged to the source electrode 12, that is, the cathode electrode 5.

In this embodiment, as apparent from comparison with the conventional structure of FIG. 25, the lateral resistance of the p-type base layer 2 does not enter the hole current bypass path. Therefore, the voltage drop due to the bypassed hole current is smaller than that of the conventional structure, and a high turn-off capability can be obtained.

The power IC is preferably a horizontal thyristor using a semiconductor substrate having a dielectric isolation structure in order to integrate a logic circuit and the like. The present invention can be applied to such a horizontal type thyristor with an insulated gate. An example of a horizontal type thyristor with an insulated gate will be described below. In the following embodiments, parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. 1 and detailed description thereof will be omitted.

FIG. 2 is a layout of a horizontal type thyristor with an insulated gate according to a second embodiment of the present invention, and FIG. 3 is a layout of FIG.
It is a III-III sectional view taken on the line. The n-type base layer 1 is formed on the silicon substrate 21 while being separated by the oxide film 22. This structure is obtained, for example, by the technique of directly bonding two silicon substrates. On the surface of the n-type base layer 1, a p-type base layer 2 and a p-type emitter layer 4 that are opposed to each other in a stripe shape are formed. In the p-type base layer 2, an n-type emitter layer 3, an n-type drain layer 7 and an n-type source layer 11 are formed in a stripe pattern. The drain electrode 8 is the n-type drain layer 7
The striped pattern is formed so as to contact the p-type base layer 2 in the immediate vicinity of the n-type emitter layer 3 as well. The turn-off insulated gate electrode 10 is formed between the n-type drain layer 7 and the n-type source layer 11 in a stripe pattern. The cross-sectional structure of the turn-off MOSFET portion is the same as that of the embodiment shown in FIG.

The gate insulating film 2 is formed on the region of the p-type base layer 2 sandwiched by the n-type emitter layer 3 and the n-type base layer 1.
Gate electrode 2 with a stripe pattern through 3
4 are formed. The gate electrode 24 is a gate electrode for turn-on which is omitted in the embodiment of FIG.

The cathode electrode 5 and the source electrode 12 are shown in FIG.
As shown in FIG. 3, they are integrally formed in a state that they are connected at the peripheral portion.

In the thyristor with a lateral insulated gate of this embodiment, when turned on, the gate electrode 10 is set to zero or a negative bias, and a positive voltage is applied to the gate electrode 24. As a result, n under the gate electrode 24 is n-type emitter layer 3
Electrons are injected into the n-type base layer 1 through the n-type channel,
Holes corresponding to this are injected from the p-type emitter layer 4 into the n-type base layer 1 and turned on. At turn off,
A positive voltage is applied to the gate electrode 10 with the gate electrode 24 set to zero or a negative bias. As a result, the hole current is bypassed and turned off as described in the previous embodiment.

Also in this embodiment, since the drain electrode 8 is arranged adjacent to the n-type emitter layer 3, a large current can be turned off as in the previous embodiment. FIG. 4 is a layout of a thyristor of a third embodiment of the present invention which is a modification of FIG. In this embodiment, the n-type emitter layer 3 is divided into a plurality of regions, and the drain electrodes 8 are inserted in a comb shape in the divided space regions to make contact with the p-type base layer 2.

According to this embodiment, the voltage drop due to the lateral resistance of the p-type base layer below the n-type emitter layer 3 is also reduced, and a higher turn-off capability can be obtained.

FIG. 5 is a perspective view of a thyristor with a lateral insulated gate according to a fourth embodiment of the present invention. In this example,
The turn-off gate electrode 10 has a zigzag pattern to ensure a sufficiently long channel width of the turn-off MOSFET. In this embodiment, the p-type emitter layer 4 is also used.
An n-type buffer layer 25 for increasing the withstand voltage is provided in the periphery of, and a high-concentration p-type layer 26 for reducing the resistance is formed between the n-type emitter layer 3 and the n-type drain layer 7.

According to this embodiment, the turn-off MOS is
The channel resistance of the FET is also reduced, and higher turn-off capability is obtained.

In the above-described embodiments, the n-type source layer is n
It is provided separately from the type emitter layer, and the hole current drawn from the drain electrode is made to flow to the cathode via the MOS transistor and the source layer. In the embodiments described below, the conventional structure in which the n-type emitter layer and the n-type source layer are shared is adopted and improved.

FIG. 6 is a cathode side layout of such a thyristor with an insulated gate according to a fifth embodiment of the present invention,
7 and 8 are VII-VII and VIII of FIG. 6, respectively.
It is a VIII line sectional view. Also in this embodiment, the dielectric isolation substrate is used as in the previous embodiment. In this example,
In the p-type base layer 2, a plurality of divided n-type emitter layers 3 are arranged. Then, the n-type drain layer 7 is formed in the region sandwiched by the n-type emitter layers 3,
An insulated gate electrode 10 forming a turn-off MOSFET is formed between the type drain layer 7 and the n-type emitter layer 3.

The drain electrode 8 is arranged so as to run in parallel with the arrangement of the n-type emitter layer 3 and the turn-off MOSFET. That is, the drain electrode 8 directly contacts the p-type base layer 2 at a position adjacent to the side of the n-type emitter layer 3 where the turn-off MOSFET is formed and another side. The stripe-shaped drain electrode 8 is
It is disposed across the n-type drain layer 7 in a branched state, and is also in contact with the n-type drain layer 7.

The insulated gate electrode 24 for turn-on is a p-layer between the divided n-type emitter layer 3 and n-type base layer 1.
It is formed on the mold base layer 2. The drain electrode 8 is
Even in the region between the turn-off insulated gate electrodes 24,
It is in contact with the p-type base layer 2.

Also in this embodiment, at the time of turn-off, the hole current is p in the vicinity of one side of the n-type emitter layer 3.
It is sucked from the mold base layer 3 to the drain electrode 8 and discharged to the cathode through the channel of the turn-off MOSFET. Therefore, a large current can be turned off.

9 to 11 are layouts of a sixth embodiment of the present invention which is a modification of the embodiments of FIGS. 6 to 8 and XX of FIG.
FIG. 3 is a sectional view taken along line XI-XI. In this embodiment, the turn-on insulated gate electrode 24 is arranged in stripes without being divided as in the previous embodiment. Also in this embodiment, the same effect as the previous embodiment can be obtained.

12 to 14 are layouts of the seventh embodiment of the present invention which is a modification of the embodiments of FIGS. 6 to 8 and FIG.
2 is a sectional view taken along line XIII-XIII and XIV-XIV of FIG. In this embodiment, the island-shaped n-type emitter layer 3 is not completely separated but is formed so as to be continuous at the end of the p-type base layer 2. The turn-on insulated gate electrode 24 is p
It is arranged in a striped pattern at the end of the mold base layer 2.

Since the n-type emitter layers are completely separated in the embodiments of FIGS.
The channel width of the OSFET is reduced accordingly.
This is the same as the gate electrode 24 as in the embodiment of FIGS.
Forming a striped pattern does not change. On the other hand, in this embodiment, the channel width of the turn-on MOSFET can be made sufficiently large, and the turn-on characteristics can be prevented from deteriorating when the split emitter structure is adopted.

15 to 17 are layouts of the thyristor with an insulated gate according to the eighth embodiment of the present invention and XVI-of FIG.
It is a XVI and XVII-XVII sectional view taken on the line. In this embodiment, the relationship between the turn-off MOSFET for the divided n-type emitter layer 3 and the contact position of the drain electrode 8 with respect to the p-type base layer 2 in the embodiment of FIGS. 6 to 8 is reversed. That is, the n-type emitter layer 3 is divided and arranged.
The n-type drain layer 7 is formed in a stripe shape so as to run in parallel with the n-type drain layer 7 and the n-type emitter layer 3.
The insulated gate electrode 10 for turn-off is disposed between the two.
The drain electrode 8 that contacts the n-type drain layer 7 is
It is formed in a stripe shape along the n-type drain layer 7 and is inserted in a region between the divided n-type emitter layers 3 in a branched state. It is in contact with the p-type base layer 2.

According to this embodiment, since the drain electrode 8 is in contact with the p-type base layer 2 adjacent to the two sides of the n-type emitter layer 3, a higher turn-off ability can be obtained as compared with the previous embodiment. .

18 to 20 are layouts of a thyristor with an insulated gate according to the ninth embodiment of the present invention and XIX of FIG.
FIG. 6 is a sectional view taken along line -XIX and XX-XX. In this example,
The n-type emitter layer 3 is continuously formed in a stripe pattern. The n-type drain layer 7 is formed with an uneven pattern on the n-type emitter layer 3 side. The turn-off insulated gate electrode 10 is formed so as to cover only the protrusion of the n-type drain layer 7, and the turn-off MOSFET is configured only in this protrusion (cross section in FIG. 19). That is, the turn-off MOSFETs are formed substantially discretely. The recess of the n-type drain layer 7 is not covered by the gate electrode 10 (cross section in FIG. 20), and the drain electrode 8 patterned in a stripe shape is exposed in a region not covered by the gate electrode 10. It is in contact with the p-type base layer 2.

According to this embodiment, the hole current during turn-off does not flow laterally below the n-type drain layer 7 from the p-type base layer 2 in the region where the turn-off MOSFET is not substantially formed. It is directly sucked to the drain electrode 8. Therefore, also in this embodiment, at the time of turn-off, the hole current can be drained without causing a large voltage drop, and a high turn-off capability can be obtained.

Although the embodiments in which the present invention is applied to the horizontal type thyristor have been described except for the example of FIG. 1, the structures of the embodiments of the horizontal type thyristor can be applied to the vertical type thyristor as it is. In addition, although the dielectric isolation substrate is used in the embodiment of the lateral thyristor, it is needless to say that the pn junction isolation may be used and the present invention can be applied to a single thyristor. Furthermore, high resistance n
The n-type buffer layer may be provided on the p-type base layer side of the mold base layer, or the turn-off speed may be increased by short-circuiting the emitter to the base using a transistor structure, and various modifications may be made.

FIG. 21 shows a thyristor with an insulated gate according to the tenth embodiment of the present invention. In this embodiment, the n-type first drain layer 7a and the n-type first drain layer 7b are provided adjacent to both sides of the n-type emitter layer 3. The emitter layer 3 is short-circuited with the p-type base layer 2 by the cathode electrode 5.
A gate electrode 10 is formed on the p-type base layer 2 between the n-type emitter layer 3 and the second drain layer 7b via a gate insulating film 9. The drain electrode 8a provided on the first drain layer 7a and the drain electrode 8b provided on the second drain layer 7b are connected to each other to form a short-circuit electrode, but the drain electrode 8a on the first drain layer 7a side is While contacting only the first drain layer 7a, the drain electrode 8b on the second drain layer 7b side also contacts the p-type base layer 2 at the same time.

In the thyristor with an insulated gate of this embodiment, at the time of turn-on, a positive voltage is applied to the cathode to the gate electrode 10 in addition to the trigger gate electrode (not shown). The path of the electron current at this time is shown by a broken line. At the time of turn-off, the hole current is directly sucked and discharged from the p-type base layer 2 to the cathode electrode 5 in the immediate vicinity of the n-type emitter layer 3, as shown by the chain line. Therefore, in this embodiment, the lateral resistance of the p-type base layer 2 below the n-type emitter layer 3 does not enter the hole current bypass path, and a high turn-off capability can be obtained.

FIG. 22 is a layout of the eleventh embodiment of the present invention in which the device of FIG. 21 is made horizontal, and FIG.
It is a III-XXIII line sectional view. The n-type base layer 1 is formed on the silicon substrate 21 while being separated by the oxide film 22. This structure is obtained, for example, by the technique of directly bonding two silicon substrates. On the surface of the n-type base layer 1, a p-type base layer 2 and a p-type emitter layer 4 that are opposed to each other in a stripe shape are formed. In the p-type base layer 2, an n-type emitter layer 3 having a striped pattern, and an n-type first drain layer 7a and a second drain layer 7b sandwiching this are formed. The cathode electrode 5 is patterned in a stripe shape so as to contact the n-type emitter layer 3 and simultaneously contact the p-type base layer 2. n-type emitter layer 3 and n-type second
The turn-on and turn-off insulated gate electrodes 10 are formed in a stripe pattern between the drain layers 7b. The cross-sectional structure of this MOSFET part is shown in FIG.
It is the same as the example.

The n-type first drain layer 7a of the p-type base layer 2
A gate electrode 24 having a stripe pattern is formed on a region sandwiched by the n-type base layer 1 and the gate insulating film 23. The gate electrode 24 is a gate electrode for turn-on which is omitted in the embodiment of FIG. The drain electrodes 8a and 8b are integrally formed in a state where they are connected at the peripheral portion as shown in the figure. The drain electrode 8b is not connected to the p-type base layer 2 in the illustrated embodiment, but may be connected to the same layer 2.

In the thyristor with a lateral insulated gate of this embodiment, a positive voltage is applied to the gate electrode 10 and the gate electrode 24 when turned on. As a result, electrons are injected from the n-type emitter layer 3 into the n-type base layer 1 through the n-type channel under the gate electrode 10 and the n-type channel under the gate electrode 24, and holes corresponding to the electrons are injected into the p-type emitter. Layer 4
Is injected into the n-type base layer 1 and turned on. At turn-off, zero or negative voltage is applied to the gate electrodes 10 and 24. The hole current is bypassed and turned off in the same manner as described in the previous embodiment.

Also in this embodiment, since the cathode electrode 5 protrudes from the n-type emitter layer 3 and contacts the p-type base layer 2, a large current can be turned off as in the previous embodiment.

FIG. 24 is a perspective view of a thyristor with a horizontal insulated gate according to a twelfth embodiment of the present invention. In this embodiment, the turn-on and turn-off gate electrodes 10 have a zigzag pattern to ensure a sufficiently long channel width of the MOSFET. In this embodiment, the n-type buffer layer 25 for increasing the breakdown voltage is also provided around the p-type emitter layer 4.
Are provided, and the n-type emitter layer 3 and the n-type first drain layer 7 are provided.
A high-concentration p-type layer 26 for reducing the resistance is formed between a.

According to this embodiment, the channel resistance of the turn-on and turn-off MOSFETs is reduced and a low on-voltage can be obtained.

Next, another viewpoint of the present invention applicable to the structure in the vicinity of the turn-on gate electrode 24 shown in FIGS.

FIG. 26 shows a lateral high withstand voltage MOSFET according to the thirteenth embodiment of the present invention. This is because the p-type channel layer 42 is formed in the low impurity concentration, that is, the high-resistance n-type silicon substrate 41.
And a high impurity concentration n-type source layer 43 therein.
Have. Further, an n-type drain layer 44 having a high impurity concentration is provided at another position in the n-type substrate 41. Although these layers are the same as those in the conventional example, the present invention further has another impurity high-concentration n-type diffusion layer 46 on the opposite side of the n-type source layer 43 with the gate electrode 45 interposed therebetween. The n-type diffusion layer 46 is formed so as to straddle the p-type channel layer 42 and the n-type substrate 41 as shown in the figure.

FIG. 27 shows, in sequence, the manufacturing process of the embodiment shown in FIG.

First, impurities are diffused into the n-type substrate 41 from the left side of the position B (in the figure) by a known selective diffusion method,
The p-type channel layer 42 is formed (FIG. 27A). Next, an oxide film 47 and a polysilicon film 48 to be a gate electrode are formed on the entire surface (FIG. 27B). Then, the polysilicon film 48 is processed into the shape of the gate electrode 45 (FIG. 2).
7 (c)). Next, using the gate electrode 45 as a mask, an n-type source layer 43 and a new n-type diffusion layer 46 are formed on both sides of the gate electrode 45 by a self-alignment technique, similarly to a normal low breakdown voltage CMOS. At the same time, the n-type drain layer 44 is also formed by diffusion (FIG. 27D). Then, unnecessary portions of the oxide film 47 are removed and the source electrode 51 and the drain electrode 52 are formed, whereby the structure shown in FIG. 26 is completed.

In the above manufacturing process, the n-type diffusion layer 46 is used.
Is formed so as to straddle the p-type channel layer 42 and the n-type substrate 41 as shown in the figure. Thereby, the n-type source layer 1
The electrons injected from 3 pass through the n-type diffusion layer 46
It is injected into the mold substrate 41.

In the lateral high breakdown voltage MOSFET shown in FIG. 26, the lateral diffusion region of the p-type channel layer 42 is not used as a channel portion. That is, high voltage MOSFE
The channel portion of T uses the vertical diffusion region of the diffusion layer, similarly to the channel portion of the low breakdown voltage MOSFET. Therefore, since the channel layers of the high breakdown voltage MOSFET and the low breakdown voltage MOSFET have the same implant dose, both channel layers can be manufactured in one step.
Furthermore, the channel length can be shortened and the high breakdown voltage M can be achieved by utilizing the fine processing technology that can be realized in the normal low breakdown voltage CMOS manufacturing process.
It is also possible to reduce the on resistance of the OSFET.

FIG. 28 shows a lateral high withstand voltage MOSFET according to the fourteenth embodiment of the present invention. In the figure, the parts corresponding to the members in FIG. 26 are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is the MO shown in the embodiment of FIG.
In this example, the SFET is formed on the dielectric isolation substrate. That is, the substrate or wafer has the support layer 55 and the n-type active layer 41 insulated by the oxide film 60. This type of substrate can be obtained by a wafer direct bonding method, a SIMOX method, or the like.

The active layer 41 includes a high breakdown voltage MOSFET,
An oxide film 61 and a polysilicon burying layer 62 are provided for dielectric isolation from other high breakdown voltage elements or low breakdown voltage elements. As the lateral dielectric isolation structure, a trench or V-groove isolation structure can be adopted.

In FIG. 28, only the portion on the high breakdown voltage MOSFET side, which is an essential part of the present invention, is shown. The relationship with other high breakdown voltage elements or low breakdown voltage elements is as shown in FIGS. 37 and 38.

FIG. 29 shows a MOSFET of the embodiment shown in FIG.
2 shows the spread of the depletion layer d when the gate and source electrodes are short-circuited and 10 V is applied between the drain and the source. As described above, since the additional n-type diffusion layer 46 is surrounded by the depletion layer d at a low voltage, it is a feature of the present invention that dielectric breakdown does not occur even at a high breakdown voltage.

30 to 36 show the 15th to 21st embodiments of the present invention in the same manner as FIG. 28. In these figures, parts corresponding to the members in FIG. 28 and the preceding figures are assigned the same reference numerals and explanations thereof are omitted.

The fifteenth embodiment shown in FIG. 30 is a lateral high withstand voltage IGB.
T (or horizontal high withstand voltage thyristor). 28 M
The n-type drain layer 44 of the OSFET is changed to a high-concentration impurity p-type drain layer 65, and holes are injected from the drain layer to reduce the on-voltage. Here, the n-type buffer layer 64 for suppressing the spread of the depletion layer and the high impurity concentration p-type layer 63 for preventing the latch-up of the n-type source layer 43.
Are formed, but these can be omitted.

The sixteenth embodiment of FIG. 31 is also a horizontal type high withstand voltage IGB.
T (or lateral high withstand voltage thyristor), in which the substrate is composed of a support layer 55 and a p-type active layer 66 which are insulated by an oxide film 60. The n-type base layer 41 is formed on the p-type active layer 66.

The seventeenth embodiment of FIG. 32 is also a horizontal type high withstand voltage IGBT.
T (or horizontal high withstand voltage thyristor), here p
And the n-type buffer layer 64 is the oxide film 6.
It is formed so as to extend to a position in contact with 0.

The eighteenth embodiment of FIG. 33 is also a horizontal type high withstand voltage IGBT.
T (or horizontal type high breakdown voltage thyristor), in which an impurity low concentration n type RESURF layer 67 is added to optimize the breakdown voltage design.

The nineteenth embodiment shown in FIG. 34 is also a horizontal type high withstand voltage IGB.
T (or horizontal type high withstand voltage thyristor)
Although the withstand voltage design is optimized by the mold resurf layer 67, the mode is slightly different from the embodiment of FIG.

The twentieth embodiment of FIG. 35 is also a horizontal type high withstand voltage IGBT.
T (or horizontal high withstand voltage thyristor), where n
The type diffusion layer and the n-type RESURF layer 67 are integrated.

The twenty-first embodiment shown in FIG. 36 is also a horizontal type high withstand voltage IGBT.
T (or horizontal high withstand voltage thyristor), where n
The type diffusion layer 46 is formed so as to fit inside the p-type channel layer 42. Then, with respect to the first gate electrode 45a between the n-type source layer 43 and the n-type diffusion layer 46, the n-type diffusion layer 46 is formed.
And the n-type RESURF layer 67 between the second gate electrode 45b.
Is provided.

37 and 38 show the relationship between the high breakdown voltage element and other high breakdown voltage element or low breakdown voltage element. In these figures, the parts corresponding to the members in the preceding figures are designated by the same reference numerals and the description thereof will be omitted.

In the 22nd embodiment of FIG. 37, the lateral high breakdown voltage I shown in FIG. 30 is provided on the right side of the isolation structures 61 and 62 in the figure.
The GBT 40 is formed. On the left side, CM with low withstand voltage
The OS 70 is formed. Here, the p-type channel layers 42 and 72 of the high breakdown voltage and low breakdown voltage elements can be formed in the same process.

In the twenty-third embodiment of FIG. 38, the n-channel lateral high breakdown voltage IGBT 4 shown in FIG. 30 is formed on the same substrate.
0, the p-channel lateral high breakdown voltage IGBT 80 is integrated.

Similar to the n-channel type high breakdown voltage element of FIGS. 26 to 36, the p-channel type high breakdown voltage element also has a low breakdown voltage C.
It can be integrated on the same substrate as the MOS. It is obvious that the structure in which the polarities of the respective parts are inverted can be formed as a p-channel type.

In the high breakdown voltage element structure shown in FIGS. 26 to 38, the channel portion formed in the channel diffusion layer is made low by adding a diffusion layer having the same polarity as the source diffusion layer to the channel diffusion layer. Like the channel portion of the breakdown voltage element, it can be arranged in the vertical diffusion region. Therefore,
The channel diffusion layers of the high breakdown voltage element and the low breakdown voltage element can be formed with high accuracy in a single process, and it is not necessary to use the DSA structure used in the conventional lateral high breakdown voltage element.

41 and 42 show an EST for improving the voltage drop in the IGBT and the latch-up withstanding capability of the parasitic thyristor. In these figures, parts corresponding to the members in FIG. 36 are designated by the same reference numerals.

The twenty-fourth embodiment of the present invention shown in FIG. 41 is characterized in that the high impurity concentration n-type (n +) diffusion layer 46 is in contact with the oxide film 60. In the structure of FIG. 41, the holes emitted from the p-type drain layer 65 are blocked by the n-type layer 46 and hardly reach below the heavily-doped n-type source layer 43. In the EST of the conventional structure, the latch-up of the parasitic thyristor is n
Since the voltage drop caused by the hole current flowing through the type source layer 43 is the cause, latch-up is essentially eliminated when the hole current flowing under the n-type source layer 43 disappears.

Therefore, according to this EST, since the n-type diffusion layer 46 acting as the emitter of the npnp4 layer which operates as a thyristor has a deeper diffusion depth than the conventional structure, the injection efficiency as the emitter is high and the voltage drop of the element is low. it can.

In the manufacture of the EST of this embodiment, first, a dielectric isolation substrate, that is, a substrate or wafer having the support layer 55 insulated by the oxide film 60 and the n-type active layer 41 is prepared. This type of substrate can be obtained by the wafer direct bonding method, the SIMOX method, or the like, as described above.

More specifically, first, a high resistance n-type (n-
) The wafer to be the active layer 41 is oxidized to form a 2 μm oxide film 60. A wafer to be the support layer 55 is directly bonded to this, and the active layer 41 is further thinned to about 2 μm. Next, a trench is formed in the active layer 41 until the oxide film 60 is reached, and then an oxide film 61 is formed by surface oxidation and a polysilicon layer 62 is embedded to form a lateral dielectric isolation structure.

Next, gate electrodes 45a and 45b are formed by the gate oxide film and the polysilicon gate. Then, the n-type buffer layer 64, the p-type layer 42, and the p-type layer 42
A deep n-type layer 46 is formed therein by diffusion. next,
High impurity concentration p-type (p +) layer 63 and drain layer 6
5. Further, the high-concentration impurity type n-type source layer 43 is formed by diffusion. And finally, the source and drain electrodes 5
1 and 52 are formed, and the illustrated structure is completed.

In the twenty-fifth embodiment of FIG. 42, in addition to the structure of FIG. 41, a high impurity concentration n-type (n +) diffusion layer 46 is further used.
An electrode 75 is formed on the above. This electrode is the n-type layer 4
6 serves to increase the recombination of electrons and holes at the surface of 6. That is, the hole current flowing under the n-type source layer 43 can be further reduced as compared with the structure of FIG.

[0087]

As described above, according to the present invention, the voltage drop of the current bypass path in the ON state is reduced by considering the layout of the diffusion layer and the gate electrode of each part, and a large current is passed. It is possible to provide a thyristor with an insulated gate that makes it possible.

[Brief description of drawings]

FIG. 1 is a sectional view of a thyristor with an insulated gate according to a first embodiment of the present invention.

FIG. 2 is a layout view of the cathode side of the thyristor according to the second embodiment of the present invention.

3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a cathode side layout diagram of a thyristor according to a third embodiment of the present invention.

FIG. 5 is a perspective view of a thyristor according to a fourth embodiment of the present invention.

FIG. 6 is a cathode side layout view of a thyristor according to a fifth embodiment of the present invention.

7 is a sectional view taken along line VII-VII of FIG.

8 is a sectional view taken along line VIII-VIII of FIG.

FIG. 9 is a cathode side layout diagram of a thyristor according to a sixth embodiment of the present invention.

10 is a sectional view taken along line XX of FIG.

11 is a sectional view taken along line XI-XI of FIG.

FIG. 12 is a layout diagram of a cathode side of a thyristor according to a seventh embodiment of the present invention.

13 is a sectional view taken along line XIII-XIII in FIG.

14 is a sectional view taken along line XIV-XIV in FIG.

FIG. 15 is a cathode side layout view of a thyristor according to an eighth embodiment of the present invention.

16 is a sectional view taken along line XVI-XVI of FIG.

17 is a sectional view taken along line XVII-XVII in FIG.

FIG. 18 is a cathode side layout view of a thyristor according to a ninth embodiment of the present invention.

FIG. 19 is a sectional view taken along line XIX-XIX in FIG. 18.

20 is a sectional view taken along line XX-XX in FIG.

FIG. 21 is a sectional view showing a thyristor according to a tenth embodiment of the present invention.

FIG. 22 is a layout diagram of the cathode side of the thyristor according to the eleventh embodiment of the present invention.

23 is a sectional view taken along line XXIII-XXIII of FIG.

FIG. 24 is a perspective view of a thyristor according to a twelfth embodiment of the present invention.

FIG. 25 is a sectional view of a conventional thyristor with an insulated gate.

FIG. 26 is a lateral high withstand voltage MOSF according to a thirteenth embodiment of the present invention.
Sectional drawing which shows ET.

FIG. 27 is a cross-sectional view showing the manufacturing process of the embodiment shown in FIG. 26 in order.

FIG. 28 is a lateral high withstand voltage MOSF according to a fourteenth embodiment of the present invention.
Sectional drawing which shows ET.

29 is a sectional view showing the spread of the depletion layer d in the embodiment of FIG. 28.

FIG. 30 is a lateral high withstand voltage IGBT according to a fifteenth embodiment of the present invention.
FIG.

FIG. 31 is a lateral high withstand voltage IGBT according to a sixteenth embodiment of the present invention.
FIG.

FIG. 32 is a lateral high withstand voltage IGBT according to a seventeenth embodiment of the present invention.
FIG.

FIG. 33 is a lateral high withstand voltage IGBT according to the eighteenth embodiment of the present invention.
FIG.

FIG. 34 is a lateral high withstand voltage IGBT according to a nineteenth embodiment of the present invention.
FIG.

FIG. 35 is a lateral high withstand voltage IGBT according to the twentieth embodiment of the present invention.
FIG.

FIG. 36 is a lateral high withstand voltage IGBT according to the twenty-first embodiment of the present invention.
FIG.

FIG. 37 is a sectional view of a twenty-second embodiment of the present invention, showing a mode in which the lateral high breakdown voltage IGBT and the low breakdown voltage CMOS shown in FIG. 30 are integrated on the same substrate.

FIG. 38 is a cross-sectional view of a twenty-third embodiment of the present invention, showing a mode in which n-type and p-type lateral high-voltage IGBTs are integrated on the same substrate.

FIG. 39 is a sectional view showing a conventional high breakdown voltage MOSFET.

FIG. 40 is a sectional view showing a conventional low breakdown voltage MOSFET.

41 is an EST (Emitter Sw) of the twenty-fourth embodiment of the present invention. FIG.
Sectional drawing which shows itching Thyristor.

FIG. 42 is a sectional view showing the EST of the 25th embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... High resistance n-type base layer, 2 ... p-type base layer, 3 ... n-type emitter layer, 4 ... p-type emitter layer, 5 ... cathode electrode, 6 ... anode electrode, 7 ... n-type drain layer, 7a ... n Type first drain layer 7b ... n type second drain layer 8 ... drain electrode, 9 ... gate insulating film, 10 ... gate electrode (for turn-off), 11 ... n type source layer, 12 ... source electrode, 21 ... silicon substrate, 22 ... Oxide film, 23 ... Gate insulating film, 24 ... Gate electrode (for turn-on).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshihiro Yamaguchi 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute Co., Ltd. (72) Inventor Norio Yasuhara Komukai-Toshiba, Kawasaki-shi, Kanagawa No. 1 town, Toshiba Research Institute, Inc. (72) Inventor Tomoko Sueshiro No. 1, Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture

Claims (4)

[Claims] 1. A high resistance first conductivity type base layer, a second conductivity type base layer formed on one surface of the first conductivity type base layer, and the first conductivity type base layer interposed therebetween. A second conductive type emitter layer connected to the second conductive type base layer; a first conductive type emitter layer formed in the second conductive type base layer; and a first conductive layer on the second conductive type base layer. A drain electrode formed adjacent to the conductive type emitter layer; a first conductive type drain layer formed on the second conductive type base layer and short-circuited to the second conductive type base layer by the drain electrode; A first conductive type source layer formed on the second conductive type base layer at a predetermined distance from the first conductive type drain layer; and the first conductive type drain layer between the first conductive type drain layer and the first conductive type source layer. Formed on the two-conductivity-type base layer through a gate insulating film. An insulated gate electrode for turn-off, a first main electrode formed on the second conductive type emitter layer, a second main electrode formed on the first conductive type emitter layer, the first main electrode formed on the first conductive type emitter layer, A thyristor with an insulated gate, comprising: a source electrode formed on a conductive type source layer and connected to the second main electrode. 2. A high resistance first conductivity type base layer, a second conductivity type base layer formed on one surface of the first conductivity type base layer, and the first conductivity type base layer interposed therebetween. A second conductive type emitter layer connected to the second conductive type base layer; a first conductive type emitter layer formed in a plurality of divisions in the second conductive type base layer; and a first conductive type A position adjacent to one side of the emitter layer and a position adjacent to the other side of the first conductivity type emitter layer of the second conductivity type base layer, and a drain electrode disposed on the second conductivity type base layer. A first conductivity type drain layer formed on the first conductivity type drain layer and shorted to the second conductivity type base layer by the drain electrode, and the second conductivity type base between the first conductivity type drain layer and the first conductivity type emitter layer. Turn-off insulator formed on the layer through the gate insulating film. A gate electrode; a first main electrode formed on the second conductivity type emitter layer; and a second main electrode formed on the first conductivity type emitter layer. Thyristor with insulated gate. 3. The second conductive type base layer is selectively formed on the surface of the first conductive type base layer, and is sandwiched between the first conductive type emitter layer and the first conductive type base layer at the terminal end thereof. 3. A turn-on insulated gate electrode is formed on the region via a gate insulating film.
A thyristor with an insulated gate according to any one of 1. 4. A high resistance first conductivity type base layer, a second conductivity type base layer formed on one surface of the first conductivity type base layer, and the first conductivity type base layer interposed therebetween. A second conductivity type emitter layer connected to a second conductivity type base layer; a first conductivity type emitter layer formed in the second conductivity type base layer; and a first conductivity type of the second conductivity type base layer. A first drain layer of a first conductivity type formed at a position adjacent to the first emitter layer, and a second drain layer of the second conductivity type base layer adjacent to the first conductivity type emitter layer and on the opposite side of the first drain layer. A first conductive type second drain layer formed at a position, and an insulation formed on the second conductive type base layer between the first conductive type emitter layer and the second drain layer via a gate insulating film. A gate electrode, and a first main electrode formed on the second conductivity type emitter layer. An insulated gate, comprising: a pole, a second main electrode formed on the first conductivity type emitter layer, and a short-circuit electrode connecting the first drain layer and the second drain layer. Thyristor.