JPH05181431A - Liquid crystal dlsplay data controller - Google Patents

Abstract

PURPOSE:To keep excellent display quality by increasing the frame frequency of a liquid crystal display panel at the acting speed of a low-speed signal driving driver even when the display resolution of the liquid crystal display panel becomes high, display data is increased, and the transferring speed of the display data is made higher. CONSTITUTION:This controller is provided with two memories 3 having the storage capacity of one line or L-number of signal driving drivers and a memory control means 5 controlling the memory 3, and display data is temporarily stored in the memory 3 and transferred to the L-number of signal driving drivers 8 at the same time. Thus, the display data transferring speed to the driver 8 is made low without changing the transferring speed of the display data of one line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display data control device suitable for displaying a large amount of high-speed display data on a liquid crystal display panel such as a personal computer or a workstation.

[0002]

2. Description of the Related Art As a conventional technique for displaying display data of a personal computer, a workstation or the like on a liquid crystal panel, the configuration and the latch timing of the display data are as described in Hitachi LCD Driver LSI Data Book p661 and 662. Hereinafter, description will be made with reference to FIGS. 2, 3, 4, and 12.

FIG. 2 is a block diagram of a liquid crystal display data control device according to the prior art. Reference numeral 1 is a display data generating means for generating display data of 6a and a synchronizing signal of 7a of a personal computer or a workstation, and 10 is liquid crystal display data control. apparatus,
8 is a signal drive driver, 4 is a liquid crystal display data control device 1
Control signal generating means for generating a synchronization signal 7d for controlling the signal driving driver 8 among 0s, and 2 converting input display data 6a into display data in a format according to the input interface of the signal driving driver 8. Data conversion means.

FIG. 3 is a system configuration diagram in the case of driving a color liquid crystal panel having 12 horizontal pixels, 640 pixels for each of R, G, B, 1920 pixels in total, and 480 pixels for vertical pixels. .. The signal drive drivers 8a and 8b are Hitachi HD66310, which has 160 output lines as described in the Hitachi LCD Driver LSI Data Book.
4 pixel data parallel input, maximum operating frequency 15 MHz. Therefore, since the horizontal pixels are simultaneously driven, 8a
6 and 8b are required respectively. Reference numeral 11 is a scan drive driver.

FIG. 4 shows the data conversion means 2 shown in FIG.
Serialize input display data 6a to output display data 6d
It is the figure which showed the timing which performs parallel data conversion.

FIG. 12 shows the signal drive driver 8 shown in FIG.
It is the figure which showed the connection state of a.

Next, returning to FIG. 2 again, the operation of this system configuration will be described. The R, G, B 3 pixel parallel display data 6a generated by the display data generating means 1 is converted into the control signal 7a,
As shown in FIG. 4, the data converting means 2 performs serial / parallel conversion in synchronization with 7b and 7d, and a total of 8 pixels of upper and lower 4 pixels according to the input format of the signal drive drivers 8a and 8b. Convert to output data. Input 3
8 cycles of R, G, B data of a pixel are converted into 4 cycles of 8 pixel data having a cycle twice as long as the input data. Next, the operation of sequentially latching the 8-pixel output data in the signal drive driver will be described with reference to FIG. EI
O1 is a chip enable signal input and EIO2 is a chip enable signal output.
O1 is connected in cascade, and the signal drive driver in the subsequent stage is activated by the EIO2 signal in the previous stage. The six signal driving drivers 8a use the input chip enable signal EIO.
When 1 is enabled, the display data of 4 pixels is 4
Display data for 160 pixels in total is fetched 0 times, and the output chip enable signal EIO2 to the next stage is enabled. Further, the six signal driving drivers 8b are similarly connected and perform the same operation. In this manner, when the display data is sequentially latched by the signal drive driver and the display data for one line is latched by the signal drive drivers 8a and 8b,
One line is output to the liquid crystal panel 12 at the same time and displayed. Therefore, in this configuration, the display data for one line, that is, the six signal drive drivers 8a and 8b for each of the upper and lower sides is transferred in series with four signal drive drivers in parallel with four pixels.

As described above, in the example of the prior art, the output data cycle is twice as long as the input data cycle. Therefore, the maximum operating frequency of the signal driver 8a, 8b is 15
The maximum frequency of input data is 30 MHZ for MHz
z. At this time, the frame frequency, which is a frequency for scanning one screen of the liquid crystal panel, is about 97 Hz at maximum (= 30 MH).
z / 640/480).

However, today, the panel resolution tends to be high, and a high-definition color liquid crystal panel having a horizontal pixel count of R120, G, B pixels of 1120 pixels, a total of 3360 pixels, and a vertical pixel count of 780 pixels has been conventionally used. When displaying by technology, 11 signal drive drivers are required for each of the upper and lower sides. At this time,
When the display data for one line is transferred in parallel with four signal driving drivers with four pixels in parallel, the frame frequency drops to about 34 Hz in order to satisfy the maximum operating frequency of 15 MHz of the signal driving driver. 6
In the current liquid crystal panel that requires 0Hz or more,
There is a problem that flicker occurs and display quality is degraded.

[0010]

In the above prior art, the display data is transferred in accordance with the operation speed of the signal drive driver of the liquid crystal display panel. Therefore, when the display resolution is increased and the display data is increased, it is possible to deal with it. There is a problem in that the frame frequency of the liquid crystal display panel becomes slow and flickering easily occurs.

An object of the present invention is to increase the display frequency of a liquid crystal display panel, increase the amount of display data, and increase the display data transfer speed. By raising the value, it is to maintain good display quality.

[0012]

As means for solving the above-mentioned problems, in a liquid crystal display data control device, a control means for generating liquid crystal display data and a control signal has a display data capacity of one horizontal line. Two storage means having a storage capacity are provided, and each storage means has a storage area L (<
M) A means for dividing and inputting display data to each storage area in order, and a display data stored in each storage means for L
Means for simultaneously reading from the respective areas, and when one of the two storage means performs a write operation of the display data for one horizontal line, the other storage means performs a read operation for the display data of one line before. The control means for controlling the above-mentioned manner and the switching means for switching the data bus read from the two storage means are provided. Alternatively, the control means for generating the liquid crystal display data and the control signal is provided with two storage means having a storage capacity for display data driven by L (<M) signal driving drivers, and each of the storage means stores An area is divided into L areas, means for writing the input display data into each storage area in order, and means for simultaneously reading the display data stored in each memory means from the L areas are provided, and one of the two memory means is provided. When the display data write operation driven by one signal drive driver is performed, the other storage means stores the previous 1
Control means for controlling to perform a read operation of display data driven by each signal driver and switching means for switching the data bus read from the two storage means are provided. Alternatively, in addition to the above means, a data time division control means for time division of display data to the signal drive driver is provided.

[0013]

According to the above means, it is possible to drive L signal drive drivers at the same time, and the display data transfer speed to the signal drive driver is reduced without changing the display data transfer speed for one line. be able to. In other words, even if the display resolution of the liquid crystal display panel increases, the display data increases, and the display data transfer speed increases,
The frame frequency of the liquid crystal display panel can be increased at a low operation speed of the signal drive driver, and good display quality can be maintained.

[0014]

[Example] A storage means having a storage capacity of two lines is provided.
First Embodiment FIG. 1, FIG. 5, FIG. 6, FIG. 7, FIG.
Will be explained.

FIG. 1 is a block diagram showing an embodiment of the present invention. 1 is a personal computer, workstation, or the like 6a.
Is a display data generation means for generating the display data of 7a and the synchronization signal of 7a, 8 is a signal drive driver, 10 is the display data of 6a and the display data of 6d and 7d of which the signal drive driver 8 is driven from the synchronization signal of 7a. It is a liquid crystal display data control device for generating a synchronization signal. 6a, 6b, 6c, 6
d is display data, and 7a, 7b, 7c and 7d are synchronization control signals. 2a and 2b are data conversion means, and 3 is a memory. 4 is a control signal 7b from the synchronizing signal 7a to the data converting means 2a, 2b and the memory controlling means 5.
And 5 is a control signal generating means for generating a synchronizing signal 7d to the signal driving driver 8, and 5 is a memory controlling means for generating a control signal 7c for controlling read / write of the memory 3.

FIG. 5 is a detailed block diagram of the memory control means 5, and 52 is a control signal generation means for generating a control signal from the control signal 7b. 55a and 55b are control signals generated by the control signal generating means 52. 50 is a control signal 55
A memory read address generating means for generating a memory read address from a, 51 is a memory write address generating means for generating a memory write address from the control signal 55a, and 56a and 56b are a memory read address and a memory write address. Reference numerals 53 and 54 are selection means for selecting the memory read address 56a and the memory write address 56b by the control signal 55b. Reference numerals 30 and 31 denote memories for storing the display data 6b. The read / write operation is controlled by the control signal 7c, and the read data is output as the display data 6c.

FIG. 6 is a system configuration diagram for driving a high-definition color liquid crystal panel having 12 horizontal pixels, 1120 pixels for each of R, G, and B, 3360 pixels in total, and having 780 vertical pixels. 8a and 8b are signal drive drivers for converting the synchronizing signal 7d and the display data 6d into liquid crystal driving voltage and outputting the same. Hitachi HD66310, output number 1
60 lines, 4-pixel data parallel input, maximum operating frequency 15M
Hz. Therefore, 11 per 8a (≈3360 ÷ 2 ÷
160) and 11 in 8b (≈3360 / 2/2/160), respectively. Further, the signal drive drivers 8a and 8b are
Driver numbers 1, 2, 3 and 4, 5, 6 and 7, 8, 9 and 1
The display data buses of 0 and 11 are common. That is, the system configuration is such that the display data is transferred to the four driver groups at the same time. 11 is a synchronization signal 7
This is a scanning drive driver that generates a vertical scanning signal from d and drives the liquid crystal panel 12.

FIG. 7 is a diagram showing the read / write timing of the memory, and FIG. 13 is a diagram showing the connection state of the signal drive driver 8a shown in FIG.

Next, returning to FIG. 1, the operation of this embodiment for simultaneously transferring display data to the upper and lower four signal drive drivers will be described. The display data 6a of the R, G, B 3 pixels in parallel generated by the display data generating means 1 is the control signal 7b.
In synchronism with the above, serial / parallel conversion is performed by the data conversion means 2a to convert into parallel 8 pixel display data 6b. Here, the reason why the display data is converted into 8 pixels in parallel is that since the input interfaces of the upper and lower signal drive drivers 8a and 8b are 4 pixels each, continuous display data is controlled every 8 pixels. Then, as shown in FIG. 7, the display data 6b is written into the memory A30 and the memory B31 alternately for each line in units of 8 pixels. The memory A30 and the memory B31 are divided into four areas respectively corresponding to four driver groups (driver numbers 1, 2, 3 and 4,5, 6 and 7, 8, 9 and 10, 11). The display data is written in the area of the signal driving driver. Then, the display data written in the memory A30 and the memory B31 are sequentially read from the four areas alternately in the next line written, and become the display data 6c as shown in FIG. The display data 6c is the data conversion means 2b.
Then, the upper and lower four drivers (driver numbers 1, 4, 7,
10 and 2, 5, 8, 11, and 3, 6, 9) are converted into parallel 32 pixel display data 6d so that the display data can be transferred simultaneously for each 4 pixels. Then, the panel drive control signal 7
The display data 6d is transferred to the signal drive driver 8 in synchronization with d.

Next, the operation of sequentially latching the 32 pixel output data in the signal driving driver will be described with reference to FIG. EIO1 is a chip enable signal input,
EIO2 is the output of the chip enable signal, and when the input chip enable signal EIO1 is enabled, it internally outputs 4
The display data of the pixel is fetched 40 times, totaling the display data of 160 pixels, and output to the next stage Chip enable signal EI
O2 is enabled. In the signal driver 8a,
EIO1 of driver numbers 1, 4, 7 and 10 is common, and driver numbers 1, 2, 3 and 4, 5, 6 and 7, 8, 9 and 1 are common.
The front EIO2 and the rear EIO1 of 0 and 11 are cascade-connected, and the rear EIO2 signal activates the rear signal drive driver. The eleven signal drive drivers 8b are also connected in the same manner and perform the same operation.

The following display data transfer is performed by the connection and operation of the signal driving driver as described above. First, the display data 6d is simultaneously transferred to the signal driving drivers of driver numbers 1, 4, 7, and 10, and when the 160 pixel transfer is completed to each signal driver, then the driver numbers 2,
Display data 6 simultaneously for 5, 8 and 11 signal drive drivers
When d is transferred and the transfer of 160 pixels to each signal driver is completed, then the display data 6d is simultaneously transferred to the signal drive drivers of driver numbers 3, 6 and 9, and when the transfer of 160 pixels to each signal driver is completed, one line is displayed. Minute data transfer is completed. In this way, the operation for one line is similarly repeated thereafter. In this way, when the display data 6d is sequentially latched by the signal drive driver and the display data for one line is latched by the signal drive drivers 8a and 8b, one line is simultaneously output to the liquid crystal panel 12 for display. Therefore, in this configuration, 1
For each line, that is, 11 signal drive drivers for each of the top and bottom
Display data for a and 8b can be transferred in series with four signal driving drivers in parallel with four pixels.

Next, in the first embodiment, the storage capacity of one line, that is, the capacity of 22 drivers was used. However, the second storage means has two storage means each having a storage capacity of eight drivers equal to or less than one line. About an Example, FIG. 1, FIG. 5, FIG. 8, FIG.
Will be explained. The block configuration of this embodiment is similar to that of the first embodiment and is shown in FIGS.

FIG. 8 is a system configuration diagram in the case of driving a high-definition color liquid crystal panel having 12 horizontal pixels, 1120 pixels for each of R, G, and B, 3360 pixels in total, and having 780 vertical pixels. 8a and 8b are signal drive drivers for converting the synchronizing signal 7d and the display data 6d into liquid crystal driving voltage and outputting the same. Hitachi HD66310, output number 1
60 lines, 4-pixel data parallel input, maximum operating frequency 15M
Hz. Therefore, 11 per 8a (≈3360 ÷ 2 ÷
160) and 11 in 8b (≈3360 / 2/2/160), respectively. Further, the signal drive drivers 8a and 8b are
Driver numbers 1, 5, 9 and 2, 6, 10 and 3, 7, 11
The display data buses of 4 and 8 are common. That is, the system configuration is such that the display data is transferred to the four driver groups at the same time. 11 is a synchronization signal 7
This is a scanning drive driver that generates a vertical scanning signal from d and drives the liquid crystal panel 12.

FIG. 9 is a diagram showing the read / write timing of the memory, and FIG. 14 is a diagram showing the connection state of the signal drive driver 8a shown in FIG.

Next, the operation of this embodiment for simultaneously transferring display data to the upper and lower four signal drive drivers will be described. The operation of converting the display data to the parallel 8-pixel display data 6b shown in FIGS. 1 and 5 is the same as that of the first embodiment. Then, as shown in FIG. 9, the memories A30 and B31 correspond to four driver groups (driver numbers 1, 5, 9 and 2, 6, 10 and 3, 7, 11 and 4, 8). Each is divided into four areas. Then, the display data 6b is added to the area of the corresponding signal driver 8
Driver numbers 1, 2, 3, 4 and 5, 6, 7, in pixel units
The signal drive driver 4 is alternately provided to the memories A30 and B31 in units of driver groups of 8 and 9, 10, and 11.
Write for each or every three. First, the display data of the signal drive drivers of driver numbers 1, 2, 3, 4 are written in the memory A30, and then driver numbers 5, 6,
The display data of the signal drive drivers 7 and 8 are stored in the memory A31.
, And at the same time, during this period, driver numbers 1, 2,
Display data of the signal driving drivers 3 and 4 is stored in the memory A30.
The four areas are sequentially read out. Next, driver number 9,1
Display data of the signal drive driver of 0 and 11 is stored in the memory A3.
0, and at the same time, driver number 5,
Display data of 6, 7, and 8 signal drive drivers are stored in the memory A.
31 is sequentially read from the four areas, and when this is finished, the display data of the signal drive drivers of driver numbers 9, 10, and 11 are sequentially read from the four areas of the memory A30. In this way, the operation for one line is similarly repeated thereafter. That is,
The memory A30 and the memory B31 each require a storage capacity for eight signal drive drivers, for a total of sixteen. The display data 6c alternately read from the memory A30 and the memory B31 is read by the data conversion means 2b, and the upper and lower four drivers (driver numbers 1, 2, 3, 4 and 5, 6, 7, 8, and 9, 10, In 11), the parallel display data 6d of 32 pixels is converted so that the display data of each 4 pixels can be transferred simultaneously. Then, the display data 6d is transferred to the signal drive driver 8 in synchronization with the panel drive control signal 7d.

Next, the operation of sequentially latching the 32 pixel output data in the signal drive driver will be described with reference to FIG. EIO1 is a chip enable signal input,
EIO2 is the output of the chip enable signal, and when the input chip enable signal EIO1 is enabled, it internally outputs 4
The display data of the pixel is fetched 40 times, totaling the display data of 160 pixels, and output to the next stage Chip enable signal EI
O2 is enabled. In the signal driver 8a,
EIO1 of driver numbers 1, 2, 3, and 4 is common.
Then, the EIO 2 having the driver number 4 is replaced with the driver number 5,
The EIO1s of the driver numbers 4, 6, 7 and 8 are activated in cascade connection with the EIO1s of the driver numbers 6, 7, and 8. Similarly, the EIO2 having the driver number 8 is cascade-connected to the EIO1 having the driver numbers 9, 10, and 11, and the EIO2 having the driver number 8 activates the signal-driven drivers having the driver numbers 9, 10, and 11. The eleven signal drive drivers 8b are also connected in the same manner and perform the same operation.

The following display data transfer is performed by the connection and operation of the signal driving driver. First, the display data 6d is simultaneously transferred to the signal driving drivers of the driver numbers 1, 2, 3 and 4, and when the 160 pixel transfer is completed to each signal driver, then the driver numbers 5, 6, 6 are transferred.
When the display data 6d is transferred to the signal drive drivers 7 and 8 at the same time, and the 160 pixel transfer is completed to each signal drive driver, the display data 6d is transferred to the signal drive drivers of driver numbers 9, 10, and 11 at the same time. When the transfer of 160 pixels to each signal driver is completed, the data transfer for one line is completed. In this way, the operation for one line is similarly repeated thereafter. In this way, when the display data 6d is sequentially latched by the signal drive driver and the display data for one line is latched by the signal drive drivers 8a and 8b, one line is simultaneously output to the liquid crystal panel 12 for display. Therefore, in this configuration, one line, that is, 11 upper and lower signal drive drivers 8 are provided.
Display data for a and 8b can be transferred in series with four signal driving drivers in parallel with four pixels.

Next, a third embodiment for halving the number of output data buses of the second embodiment will be described with reference to FIGS. 5, 9, 10, 11, 15, and 16. ..

FIGS. 5 and 15 are block configuration diagrams of this embodiment. In FIG. 15, 20 is a data time division control means for time-division controlling the display data 6a, and 6e is time division display data. ..

In FIG. 10, the number of 12 horizontal pixels is R, G, B.
A system configuration diagram for driving a high-definition color liquid crystal panel having 1120 pixels each, 3360 pixels in total, and having 780 vertical pixels, 8a and 8b are synchronization signals 7d.
And a signal drive driver for converting the display data 6e into liquid crystal drive voltage and outputting the same. Hitachi HD66310, 160 output lines, 4 pixel data parallel input, maximum operating frequency 15
MHz. Therefore, 11 in 8a (≈3360 / 2)
÷ 160), 11 in 8b (≈3360 ÷ 2 ÷ 160)
Each is required. In addition, the signal drive drivers 8a and 8b
Are driver numbers 1, 2, 5, 6, 9, 10 and 3, 4,
The display data buses of 7, 8, and 11 are common. That is,
This system configuration is configured to transfer the display data which is time-shared to the two driver groups at the same time. 1
Reference numeral 1 denotes a scan drive driver that drives the liquid crystal panel 12 by generating a vertical scan signal from the synchronization signal 7d.

FIG. 9 is a diagram showing the read / write timing of the memory, FIG. 11 is a diagram showing the latch timing of the time-divided display data of the signal drive driver, and FIG.
FIG. 11 is a diagram showing a connection state of the signal drive driver 8a shown in FIG.

Next, the operation of this embodiment for simultaneously transferring display data to the upper and lower four signal drive drivers will be described. The display data shown in FIG. 5, FIG. 9, and FIG.
The operation of converting the display data 6d of 2 pixels is the same as that of the second embodiment. And the display data 6d of parallel 32 pixels
Is further converted into time-division display data 6e by the data time-division control means 20. The data time division control and the data latch timing of the signal drive driver will be described with reference to FIG. The data latch clocks are provided with φ1 and φ2, which are 180 ° out of phase with each other, and φ1 is connected to the signal driver having an odd driver number and φ2 is connected to the even driver. Odd-numbered driver data and even-numbered driver data are transferred to the display data bus in a time division manner with a half cycle of the data latch clock. Odd-numbered driver data is data latch clock φ1 and even-numbered driver data is data latch clock φ2. Latch at the falling edge of. That is, the display data bus can be shared and the number of buses can be reduced by performing the time-division control for halving the cycle of the display data while keeping the operating frequency of the signal driver. Then, the display data 6e thus time-division controlled is transferred to the signal drive driver 8 in synchronization with the panel drive control signal 7d.

Next, the operation of sequentially latching the 32 pixel output data in the signal drive driver will be described with reference to FIG. EIO1 is a chip enable signal input,
EIO2 is the output of the chip enable signal, and when the input chip enable signal EIO1 is enabled, it internally outputs 4
The display data of the pixel is fetched 40 times, totaling the display data of 160 pixels, and output to the next stage Chip enable signal EI
O2 is enabled. In the signal driver 8a,
EIO1 of driver numbers 1, 2, 3, and 4 is common.
Then, EIO2 of driver number 3 is replaced with driver number 5,
Cascade connection to EIO1 of 7 and E of driver number 3
The signal drive driver of driver numbers 5 and 7 is started by IO2. Similarly, the EIO2 having the driver number 4 is cascade-connected to the EIO1 having the driver numbers 6 and 8, and the EIO2 having the driver number 4 activates the signal driving driver having the driver numbers 6 and 8. 11 is connected to EIO1 in cascade, EIO2 of driver number 7 activates the signal drive driver of driver numbers 9 and 11, EIO2 of driver number 8 is cascade connected to EIO1 of driver number 10, and driver is driven by EIO2 of driver number 8. The signal drive driver of number 10 is activated. The eleven signal drive drivers 8b are also connected in the same manner and perform the same operation.

The following display data transfer is performed by such connection and operation of the signal driving driver. First, the display data 6e is simultaneously transferred to the signal driving drivers of driver numbers 1, 2, 3 and 4, and when the 160 pixel transfer is completed to each signal driver, then the driver numbers 5, 6 and 6.
When the display data 6e is simultaneously transferred to the signal drive drivers 7 and 8 and the transfer of 160 pixels to each signal driver is completed,
Next, the display data 6e is simultaneously transferred to the signal driving drivers of driver numbers 9, 10, and 11, and 1 is sent to each signal driver.
When the transfer of 60 pixels is completed, the data transfer for one line is completed. In this way, the operation for one line is similarly repeated thereafter. In this manner, when the display data 6e is sequentially latched by the signal drive driver and the display data 6e for one line is latched by the signal drive drivers 8a and 8b, one line is simultaneously output to the liquid crystal panel 12 for display. Therefore, in this configuration, one line, that is, 11 upper and lower signal drive drivers 8 are provided.
Display data for a and 8b can be transferred in series with four signal driving drivers in parallel with four pixels.

In the case of the first, second and third embodiments described above, the operating frequency is 15 MHz for the maximum operating frequency of the signal drive driver, and the dot clock is 120 MHz.
The maximum frame frequency is 137Hz (= 120MHz ÷ 1)
Therefore, even if the panel resolution increases, the frame frequency does not decrease, and good display quality can be obtained.

In the above embodiment, the Hitachi HD66310 is used as the signal driver, but the number of output data is
The present invention can be realized by changing the number of divisions of the signal driving driver or the configuration of the memory even if the signal driving driver having a different interface such as the operating frequency or the number of data input pixels is used.

[0037]

According to the present invention, L signal drive drivers can be simultaneously driven, and the display data transfer rate to the signal drive driver can be reduced without changing the display data transfer rate for one line. Even if the display resolution of the display panel increases, the display data increases, and the display data transfer speed increases, the operating speed specifications of the low-speed signal drive driver are satisfied and the frame frequency of the liquid crystal display panel increases. Therefore, good display quality can be maintained. Further, since the transfer rate of the display data can be suppressed low, the electromagnetic radiation can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional technique.

FIG. 3 is a system configuration diagram in a conventional technique.

FIG. 4 is a diagram showing display data timing conversion in the conventional technique.

FIG. 5 is a block diagram of a memory control unit.

FIG. 6 is a system configuration diagram of the first embodiment.

FIG. 7 is a diagram showing read / write timing of the memory of the first embodiment.

FIG. 8 is a system configuration diagram of a second embodiment.

FIG. 9 is a diagram showing the read / write timing of the memory of the second embodiment.

FIG. 10 is a system configuration diagram of a third embodiment.

FIG. 11 is a diagram showing a data latch timing of a signal drive driver.

FIG. 12 is a detailed configuration diagram of a conventional signal drive driver.

FIG. 13 is a detailed configuration diagram of a signal drive driver of the first embodiment.

FIG. 14 is a detailed configuration diagram of a signal drive driver according to a second embodiment.

FIG. 15 is a block diagram showing a third embodiment.

FIG. 16 is a detailed configuration diagram of a signal drive driver according to a third embodiment.

[Explanation of symbols]

 1 ... Display data generating means, 2, 2a, 2b ... Data converting means, 3, 30, 31 ... Memory, 4 ... Control signal generating means, 5 ... Memory control means, 6a, 6b, 6c, 6d, 6e ... Display data , 7a, 7b, 7c, 7d, 55a, 55b ... Control signal, 8, 8a, 8b ... Signal drive driver, 10 ... Liquid crystal data control device, 11 ... Scan drive driver, 12 ... Liquid crystal panel, 20 ... Data time division control Means, 50 ... Memory read address generation means, 51 ... Memory write address generation means, 52 ... Control signal generation means, 53, 54 ... Selection means, 56a ... Memory read address, 56b ... Memory write address.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Furuhashi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd. Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Koji Takahashi 3300 Hayano, Mobara-shi, Chiba Co., Ltd Hitachi Ltd. Mobara factory

Claims (5)

[Claims] 1. A control means for inputting display data and a synchronizing signal to generate liquid crystal display data and control signals for driving liquid crystal, and liquid crystal display data for one line are sequentially input and converted into liquid crystal driving voltage. Output signal output driver M (M
Is an integer of 2 or more), and a liquid crystal display device comprising an active matrix type liquid crystal panel in which each display pixel portion is composed of a switching element and a liquid crystal, in a control means for generating the liquid crystal display data and the control signal. 1
Two storage means having a storage capacity of display data for horizontal lines are provided, and each storage means has a storage area L
(<M) Division, means for writing the input display data into each storage area in order, and means for simultaneously reading the display data stored in each storage means from the L areas are provided, and one of the two storage means is provided. When performing the write operation of the display data for one horizontal line, the control means for controlling the other storage means to perform the read operation of the display data of one line before and the switching for switching the data bus read from the two storage means A liquid crystal display data control device, characterized in that L signal drive drivers can be simultaneously driven. 2. A control means for inputting display data and a synchronizing signal to generate liquid crystal display data and a control signal for driving liquid crystal, and liquid crystal display data for one line are sequentially input and converted into a liquid crystal driving voltage. Output signal output driver M (M
Is an integer greater than or equal to 2), and a liquid crystal display device including an active matrix type liquid crystal panel in which each display pixel section includes a switching element and a liquid crystal, M signal drive drivers are input in the order of input display data. (<M)
A liquid crystal display module, characterized in that the display data is transferred to the L signal driving drivers at the same time by being divided into groups. 3. The storage means according to claim 2, wherein two storage means having a storage capacity for display data driven by L (<M) signal drive drivers are provided, and each storage means divides the storage area into L areas. When the display data to be input are sequentially written in each storage area and the display data stored in each storage means is read out simultaneously from L areas, one of the two storage means performs a writing operation. The liquid crystal is characterized in that a control means for controlling the other storage means to perform a read operation and a switching means for switching the data bus read from the two storage means are provided so that L signal drive drivers can be simultaneously driven. Display data controller. 4. The liquid crystal display data according to claim 1, wherein the storage means is capable of writing and reading asynchronously, and the display data is simultaneously written into and read from the storage means. Control device. 5. A data time division control means for time division of display data to a signal drive driver according to claim 1, wherein each of the time division display data is 180 ° in phase with each other. A liquid crystal display data control device characterized in that data is latched by a shifted display data latch clock.