JPH05180906A - Logical waveform generating device - Google Patents

Abstract

PURPOSE:To properly generate a test pattern at a double clock following pattern data by separately providing interleave circuits for generating waveforms and interleave circuits for the double clock. CONSTITUTION:A fifth and sixth interleave circuits 227 and 228 are provided in addition to a first and second interleave circuits 207 and 208 for generating waveforms and third and fourth interleave circuits 209 and 211 for controlling drivers. The logical outputs of a first and second pattern decoders 203 and 203 are respectively given to the circuits 227 and 228. By controlling the opening/closing of each AND gate G, H, I, and J of a third clock extracting means 229 by means of the circuits 227 and 228, clocks DREL and DRET for controlling drivers are extracted. Therefore, two types of waveforms are generated at a double clock in one cycle following the sequence of test pattern data even in a waveform mode RZO/RZO or RZZ/RZZ.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic waveform generator used for testing a logic circuit, for example.

[0002]

2. Description of the Related Art When performing a functional test of a logic circuit, the circuits under test are RZO, / RZO, RZZ, / RZZ, RZ.
It is necessary to apply and test a signal having a logical waveform such as X, / RZX. For this reason, the IC test apparatus has conventionally been provided with a logic waveform generation device.

FIG. 5 shows the configuration of a conventional logic waveform generator. In the figure, 100 is a pattern generator, 200 is a logic waveform generator, 300 is a driver, 400 is a timing generator, and 500 is a double clock generation switching circuit. Although not shown in the figure, a circuit under test (mainly an IC) is connected to the output side of the driver 300, and the logic waveform generating device 2
The test pattern signal having the actual waveform generated at 00 is given and the test is performed.

The logic waveform generator 200 includes a waveform generator 201 for a test pattern signal applied to a circuit under test and a driver control signal generator 202 for controlling the state of the driver 300.
Composed of and. The waveform generator 201 includes a first pattern data decoder 203, a second pattern data decoder 204, and first and second clocks for synchronizing the outputs of the first and second pattern data decoders 203 and 204 with the operation of the circuit under test. The first and second interleave circuits 207 and 208 for converting into the waveform data timed by CLKA and CLKB, and the output of the first and second interleave circuits 207 and 208 extract the clock synchronized with the operation of the circuit under test. First clock extracting means 212
And a flip-flop 213 which is supplied with the clock extracted by the first clock extraction means 212 and generates an actual waveform of the test pattern signal.

First and second pattern data decoders 203
And 204 are set value input terminals VA, as shown in FIG.
It has VB, AS, AR, BS, BR, and these set value input terminals VA, VB, AS, AR, BS, BR are shown in FIG.
By applying the setting values shown in FIG. 8, the pattern data input to the input terminal PAT according to each waveform mode is output to the output terminals ASET, ARESET, BSET, and BRESET as the logic signals shown in FIG.

Output terminals ASET, ARESET, BSE
The logic signals output to T and BRESET are the first
Interleave circuit 207 and second interleave circuit 2
08 interleave circuits 207A and 207B
And 208A, 208B are applied to the AND gates A, B, C, D constituting the first clock extraction circuit 212 to control the opening / closing of the AND gates A, B, C, D. That is, the AND gate A is opened when the output terminal ASET is at "1" logic, the AND gate B is opened when the output terminal ARESET is at "1" logic, and the AND gate C is opened when the output terminal BSET is at "1" logic. Output terminal BRESE
The AND gate D is opened when T is "1" logic.

When the clock CLKA is input with the AND gate A opened, the clock CLKA passes through the AND gate A and is input to the set terminal S of the flip-flop 213. The output of the AND gate B is input to the reset terminal R of the flip-flop 213, and the output of the AND gate C is the set terminal S of the flip-flop 213.
To the reset terminal R of the flip-flop 213.

The clocks CLKA and CLKB are output from the timing generator 400 and given to the AND gates A, B, C and D through the double clock generation switching circuit 500. The double clock generation switching circuit 500 includes AND gates X ₁ , Y ₁ and X ₂ , Y ₂ and an OR gate O.
It is composed of R ₁ and OR ₂ . In the normal mode, the AND gates Y ₁ and Y ₂ are controlled to be open, and X ₁ and X ₂ are controlled to be closed. Therefore, in this state, the AND gates A, B and C, D are supplied with only the clocks CLKA and CLKB. At this time, the driver control clock DREL
And DRET are input to the flip-flop 213 through AND gates Y ₁ and Y ₂ and AND gates E and F, and the output of the flip-flop 213 determines the state of the driver 300, that is, the operation mode of the driver 300 in the waveform output mode and the high impedance mode. And control.

The high impedance mode is the test
Indicates a state in which a circuit terminal operates as an output terminal. Toko
If the circuit under test is a high-speed operation type IC, input terminal
Is used as an input-only pin, and high-speed test pattern
Give a number and test. For this reason,
Lock mode is available. Double clock mode
Then, driver control clocks DREL and DRET
This is notable for the original purpose
The driver control clocks DREL and DRET.
In addition to lock CLKA and CLKB, double clock
Generate and 1 test cycle by this double clock
Two test patterns are generated inside. For this
A double clock generation switching circuit 500 is provided.
It AND gate X in double clock mode₁And X₂
Is controlled to open and AND gate Y₁And Y₂Is closed
Be done. As a result, the driver control clock DREL is
NAND gate X₁Through OR gate OR₁Given to
AND gates A and B added to clock CLKA
To the set terminal S of the flip-flop 213.
Or applied to the reset terminal R. Also for driver control
Clock DRET is AND gate X ₂Through oage
OR₂And is added to clock B. Croot
The driver control clock DRET added to the clock
Flip-flop 213 through the NAND gate C or D
To the set terminal S or reset terminal R of
Two test patterns are generated within the strike cycle.

FIG. 9 shows the waveforms of the test pattern signals in the clocks CLKA and CLKB and each waveform mode. The upper row shows the normal mode, and the lower row shows the double clock mode.

[0011]

The waveform of the double clock mode shown in FIG. 9 shows only the RZX mode and the / RZX mode. In other words, conventionally, RZO mode,
The / RZO mode, the RZZ mode, and the / RZZ mode have a drawback that they do not operate normally due to the double clock.

The reason is that the pattern data decoder 20
The interleave circuits 207A, 207B, 208A, and 208B arranged in the next stage of 3 and 204 exist. Interleave circuits 207A, 207B, 208
A and 208B are respectively configured as shown in FIG. 10, and output terminals ASE of the pattern data decoders 203 and 204 according to the operation clock SNC on the test apparatus side.
The pattern data output to T, ARESET, BSET, and BRESET are flip-flops 21 and 2 respectively.
It is divided into two paths I and J by 2. As shown in C of FIG. 11, the distributed signal has a cycle twice as long as the cycle of the input logic signal (FIG. 11A).
That is, it is divided into two paths I and J and converted into a low speed signal, and this low speed signal is taken out in synchronization with the clock CLKA or the clock CLKB synchronized with the operation of the circuit under test or the driver control clocks DREL and DRET. As a result, the extracted logic signal output is clocked by the clock (CLKA or CLKB, as shown in F of FIG. 11).
Alternatively, it becomes a logic signal (test pattern data) synchronized with DREL, DRET).

The interleave circuits 207A and 207
The reason why B, 208A, and 208B exist is as follows. The test pattern signal applied to the circuit under test must be synchronized with the operating clock of the circuit under test. For this synchronization, clocks CLKA, CLKB, DREL, DRET synchronized with the operation clock of the IC under test are generated, and these clocks CLKA, CLKB, DREL,
The test pattern data is cut out by DRET. When the cutting operation is performed at the speed shown in FIG. 11A during this cutting operation, the clocks CLKA and CLK are generated because the cycle is short.
Even if the phase of B or DREL, DRET fluctuates a little, it will deviate from the position of the data to be cut out. Therefore, the test pattern data is once converted into a low speed signal, and the signal is cut out in the state of the low speed signal.

For the reasons explained above, the interleave circuits 207A, 207B, 208A, 208B and 2
09, 211 exist, but when it is attempted to operate in the double clock mode described above, the waveform mode RZO, /
In RZO, RZZ, and / RZZ, interleave circuits 207A, 207B, 208A, and 208B malfunction, causing a problem that a test pattern signal cannot be generated normally.

How the interleave circuit malfunctions will be described with reference to FIG. The logic signal (test pattern data) shown in FIG. 12 is input to the interleave circuit. This logic signal is distributed to the low-speed signals of the secondary paths I and J by the clock SNC on the tester side. This clock C
The logical sum of LKA and DREL is generated to generate the double clock DCLK shown in FIG. 12E.
Is applied to the clock input terminal of the flip-flop 21 of the interleave circuit shown in FIG. By supplying the double clock DCLK to the clock input terminal of the flip-flop 21 of the interleave circuit shown in FIG.
The flip-flop 21 has rectangular waves K and L shown in F of FIG.
Is output. These rectangular waves K and L are the gate 2 shown in FIG.
4 and 25, the low speed signal (see FIG.
Cut out C). FIG. 12G shows the logic signals cut out by the gates 24 and 25. The order of the data of the logic signals shown in FIG. 12G should be correct.
It should be ... but actually ...
The phenomenon that the order of test pattern data is out of order, such as The reason is that two clocks are given to the same interleave circuit in one test cycle.

In the RZX and / RZX waveform modes, since the set value DFIX shown in FIG. 6 is set to "1", whether all test pattern data is "1" or "0" (throughout the entire test cycle). is there. Therefore, even if the order of the test pattern data is out of order, the data is not out of order, and the double clock mode can be operated.

[0017]

According to the present invention, a double clock interleave circuit and a clock extracting means are provided separately from a waveform generating interleave circuit and a clock extracting means, and a waveform is formed by the double clock interleaving circuit and the clock extracting means. A set signal and a reset signal for generation are generated, and in the double clock mode, the set signal and the reset signal are merged with the set signal and the reset signal generated by the waveform generation device, and the result is given to a flip-flop for waveform generation. It is a thing.

According to the structure of the present invention, since the interleave circuit for waveform generation and the interleave circuit for double clock are separately provided, the double clock is not applied to the interleave circuit for waveform generation. Therefore, the interleave circuit for waveform generation uses the original clock CLKA.
And CLKB are given. As a result, the interleave operation operates normally, and the inconvenience that the order of data is out of order is avoided.

Further, the double clock interleave circuit operates in synchronization with the driver control clock to generate a double clock according to the pattern data. By supplying the double clock to the waveform generation flip-flop, the test pattern signal by the double clock can be correctly generated according to the pattern data.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a logic waveform generator according to the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals. In the present invention, in addition to the first and second interleave circuits 207 and 208 and the third and fourth interleave circuits 209 and 211 for driver control, the fifth and sixth interleave circuits 227 and 228 are provided.
It is characterized by a structure provided with.

The fifth interleave circuit 227 is supplied with the logic output of the first pattern data decoder 203 for the clock CLKA, and the interleave output side time adjustment clock (clock applied to the flip-flop 21 shown in FIG. 10) is controlled by the driver. Clock DREL (Fig. 2
(See C). The sixth interleave circuit 228 includes the second pattern data decoder 20 for the clock CLKB.
4 is provided, and the driver control clock DRET (FIG. 2E) is used as a time adjustment clock on the interleave output side.
Reference).

The output of the fifth interleave circuit 227 is given to the third clock extracting means 229. The third clock extracting means 229 is composed of four AND gates G, H, I,
Can be constructed by J. AND Gate G and H
Is controlled to open and close according to the logic (pattern data) output from the fifth interleave circuit 227, and gate-controls the driver control clock DREL. The AND gates I and J are open / close controlled according to the logic (pattern data) output from the sixth interleave circuit 228 to gate-control the driver control clock DRET.

The clock extracted by the third clock extracting means 229 is applied to the mode switching means 231, and applied to the set terminal S and the reset terminal R of the test pattern generating flip-flop 213 according to the mode setting state of the mode switching means 231. The state is switched to the state applied to the set terminal S and the reset terminal R of the driver control signal generation flip-flop 214.

That is, in the normal mode, the AND gates K, L and N, O are controlled to be closed, and the AND gate M.
And P are controlled to open. In the double clock mode, AND gates K, L and N, O are controlled to be open, and AND gates M and P are controlled to be closed. According to the configuration described above, in the normal mode, the first clock extraction means 212 outputs the first waveform generation clocks CLKA and CLKB by the outputs of the first and second interleave circuits 207 and 208.
And the extracted clocks CLKA and CLKB according to the logic (test pattern data) output from the second interleave circuits 207 and 208, and apply the extracted clocks CLKA and CLKB to the set terminal S and the reset terminal R of the test pattern signal waveform generation flip-flop 213. .. Therefore, the normal mode operates similarly to the normal mode shown in FIG.

On the other hand, when the first and second pattern data decoders 203 and 204 are set to the waveform mode RZO with the set values shown in FIG. 7, the first and second pattern data decoders 203 and 204 are set to the waveform mode RZO. In the test cycle in which the value of the input pattern A is “1”, the clocks CLKA and CLKB are the first clock extraction means 212.
2 is supplied to the set terminal S of the flip-flop 213, and the clock CLKB is supplied to the reset terminal of the flip-flop 213.
The waveform RZO1 shown in is generated.

Further, the fifth and sixth interleave circuits 22
The driver control clocks DREL and DRET are extracted from the third clock extraction means 229 in response to the logic signals (test pattern signals) output from 7 and 228. The driver control clocks DREL and DRET are set terminals S of the flip-flop 213 through AND gates K, L and N, O which constitute the mode switching means 231.
And a reset terminal R to generate a waveform RZO2 as shown in FIG. 2F.

Further, in the waveform mode RZZ, when the input pattern data is "0" as shown in FIG. 2G, the waveform RZZ1 is generated by the waveform generation clocks CLKA and CLKB.
Is generated, and driver control clocks DREL and DRE are generated.
The waveform RZZ2 is generated by T. Waveform mode RZX
Then, the pattern data input as in the past is "0".
However, even if it is "1", "1" is given to the set value DFIX shown in FIG. 7, so that the first and second interleave circuits 2
"1" in all test cycles for 07 and 208
Since the logic is given, the waveforms RZX1 and RZX2 are generated in every test cycle.

As described above, according to the present invention, the fifth interleave circuit 227 and the sixth interleave circuit 228 are provided separately from the first and second interleave circuits 203 and 204 for the double clock, and these interleave circuits 227 and 227 are provided. Since the AND gates G, H, I, and J of the third clock extraction means 229 are controlled to be opened and closed by 228 to extract the driver control clocks DREL and DRET, the waveform modes RZO, / RZO and RZZ, / R are extracted.
Also in each of the ZZ modes, two waveforms can be generated in one test cycle by the double clock according to the order of the test pattern data.

FIG. 3 shows a modified embodiment of the present invention. In this embodiment, pattern data PATA and P output from the pattern generator 100 are used for waveform generation by a double clock.
A case is shown in which the coincidence and non-coincidence of both ATBs are detected and whether or not a double clock waveform is output is controlled based on the coincidence and the non-coincidence detection result. For this purpose, an exclusive OR circuit 234 for detecting the match / mismatch of the pattern data PATA and PATB and pattern data decoders 232, 233 for decoding the detection output are provided, and the decode outputs of the pattern data decoders 232, 233 are provided. Are provided to the fifth and sixth interleave circuits 227 and 228.

According to the implementation structure of FIG. 3, as shown in FIG. 4, a test cycle in which no waveform is output depending on the values of the pattern data PATA and PATB, a test cycle in which two waveforms are output, and a waveform with a double clock. R
It is possible to generate four types of patterns: a test cycle that outputs only ZO2 or RZZ2 and a test cycle that outputs only the waveform RZO1 or RZZ1 generated by the waveform generation clocks CLKA and CLKB. As a result, it is possible to judge pass / fail for four test patterns in one test. Therefore, there is an advantage that it is possible to carry out a multi-item test in a short time.

[0031]

As described above, according to the present invention, the logical waveform generating device which has been conventionally capable of correctly operating only in the waveform modes RZX and / RZX in the double clock mode is provided with the RZO, / RZO and RZZ, / RZZ
It can be operated normally by double clock in each waveform mode. Therefore, the number of items that can be tested at one time increases, which has the advantage of shortening the time required for the test.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a modified embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of FIG.

FIG. 5 is a block diagram for explaining a conventional technique.

FIG. 6 is a connection diagram for explaining the internal structure of the pattern data decoder used in FIG.

FIG. 7 is a diagram for explaining the value of a setting signal given to the pattern data decoder shown in FIG.

FIG. 8 is a diagram for explaining the operation of the pattern data decoder shown in FIG.

FIG. 9 is a waveform diagram for explaining the operation of the conventional logic waveform generation device.

10 is a connection diagram for explaining the internal structure of the interleave circuit shown in FIG.

11 is a waveform diagram for explaining the operation of the interleave circuit shown in FIG.

FIG. 12 is a waveform diagram for explaining the drawbacks of the conventional technique.

[Explanation of symbols]

 100 pattern generator 200 logic waveform generator 300 driver 400 timing generator 201 waveform generator 202 driver control signal generator 203 first pattern data decoder 204 second pattern data decoder 205 third pattern data decoder 206 fourth pattern data decoder 207 First interleave circuit 208 Second interleave circuit 209 Third interleave circuit 210 Second clock extraction means 211 Fourth interleave circuit 212 First clock extraction means 213,214 Flip-flop 227 Fifth interleave circuit 228 Sixth interleave circuit 229 Third clock Extraction means 231 Mode switching means

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[Procedure amendment]

[Submission date] December 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 5 shows the configuration of a conventional logic waveform generator. In the figure, 100 is a pattern generator, 200 is a logic waveform generator, 300 is a driver, 400 is a per-pin timing generator, and 500 is a double clock generation switching circuit. Although not shown in the figure, a circuit under test (mainly an IC) is connected to the output side of the driver 300, and a test pattern signal having an actual waveform generated by the logical waveform generation device 200 is given to perform a test.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008] The clock CLKA and CLKB is output from the per-pin data <br/> timing generator 400, the AND gate A through the double clock generating switching circuit 500, B, C,
Given to D. Double clock generation switching circuit 500
Is constituted by AND gates X ₁ , Y ₁ and X ₂ , Y ₂ and OR gates OR ₁ , OR ₂ . In the normal mode, the AND gates Y ₁ and Y ₂ are controlled to be open, and X ₁ and X ₂ are controlled to be closed. Therefore, in this state, AND gate A,
Only clocks CLKA and CLKB are supplied to B, C and D. At this time, the driver control clock DR
EL and DRET are flip-flops 214 through AND gates Y ₁ and Y ₂ and AND gates E and F.
And the output of the flip-flop 214 controls the state of the driver 300, that is, the operation mode of the driver 300 to the waveform output mode and the high impedance mode.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

How the interleave circuit malfunctions will be described with reference to FIG. The logic signal (test pattern data) shown in FIG. 12 is input to the interleave circuit. This logic signal is distributed to the low-speed signals of the secondary paths I and J by the clock SNC on the tester side. This clock C
The logical sum of LKA and DREL is generated to generate the double clock DCLK shown in FIG. 12E.
10 is a flip-flop of the interleave circuit shown in FIG.
23 to the clock input terminal. By supplying the double clock DCLK to the clock input terminal of the flip-flop 23 of the interleave circuit shown in FIG.
The flip-flop 23 has rectangular waves K and L shown in F of FIG.
Is output. These rectangular waves K and L are the gate 2 shown in FIG.
4 and 25, the low speed signal (see FIG.
Cut out C). FIG. 12G shows the logic signals cut out by the gates 24 and 25. The order of the data of the logic signals shown in FIG. 12G should be correct.
It should be ... but actually ...
The phenomenon that the order of test pattern data is out of order, such as The reason is that two clocks are given to the same interleave circuit in one test cycle.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The fifth interleave circuit 227 is provided with the logic output of the first pattern data decoder 203 for the clock CLKA, and the time adjustment clock on the interleave output side (clock provided to the flip-flop 23 shown in FIG. 10) is controlled by the driver. Clock DREL (Fig. 2
(See C). The sixth interleave circuit 228 includes the second pattern data decoder 20 for the clock CLKB.
4 is provided, and the driver control clock DRET (FIG. 2E) is used as a time adjustment clock on the interleave output side.
Reference).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Reference Signs ] 100 pattern generator 200 logical waveform generator 300 driver 400 per-pin timing generator 201 waveform generator 202 driver control signal generator 203 first pattern data decoder 204 second pattern data decoder 205 third pattern data decoder 206 4th pattern data decoder 207 1st interleave circuit 208 2nd interleave circuit 209 3rd interleave circuit 210 2nd clock extraction means 211 4th interleave circuit 212 1st clock extraction means 213, 214 Flip-flop 227 5th interleave circuit 228 6th Interleave circuit 229 Third clock extraction means 231 Mode switching means

[Procedure correction 6]

[Document name to be corrected] Drawing

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[Figure 1]

[Procedure Amendment 7]

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[Figure 3]

[Procedure Amendment 8]

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[Procedure Amendment 9]

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[Figure 9]

[Procedure Amendment 10]

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[Figure 10]

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Correction target item name] Figure 12

[Correction method] Change

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[Fig. 12]

Claims (1)

[Claims] 1. A. B. First and second pattern data decoders for converting pattern data given from a pattern generator into a plurality of logic signals and outputting the plurality of logic signals according to the setting of a waveform mode to be generated; First and second interleave circuits for converting the outputs of the first and second pattern data decoders into waveform data timed by the first and second clocks synchronized with the operation of the circuit under test; First clock extracting means for extracting a waveform setting clock and a waveform reset clock synchronized with the operation of the circuit under test by the outputs of the first and second interleave circuits, and D. A flip-flop that is set and reset by the waveform setting clock and the waveform reset clock extracted from the first clock extracting means to generate the actual waveform of the test pattern signal; A driver having a three-state function that amplifies the test pattern signal output from the flip-flop and gives it to the circuit under test; The output of the third and fourth pattern data decoders is converted into driver control waveform data timed by a driver control clock synchronized with the operation of the circuit under test.
A fourth interleave circuit, G. Second clock extraction means for extracting a driver control signal set clock and a driver control signal reset clock synchronized with the operation of the circuit under test by the outputs of the third and fourth interleave circuits; A flip-flop which receives the set clock and the reset clock of the driver control signal extracted from the second clock extraction means, and which generates a driver control signal to be given to the control terminal of the driver; The fifth and sixth interleave circuits which are timed by the driver control clock by the outputs of the first and second pattern data decoders; By the outputs of the fifth and sixth interleave circuits,
Third clock extracting means for applying a double clock to the flip-flop for generating the waveform of the test pattern signal, and K. The double clock extracted from the third clock extracting means is shut off, and in that state, the set clock and the reset clock of the driver control signal extracted by the second clock extracting means are converted into a flip-flop for generating the driver control signal. A logical waveform generation device configured by mode switching means for switching to a supply state.