JPH05119121A - Waveform generating apparatus - Google Patents

Abstract

PURPOSE:To prevent malfunction by providing a storage circuit, storing encoded data with a format encoding circuit beforehand, and avoiding the generation of an invalid time. CONSTITUTION:Data Da, i.e., pattern data Pda, are inputted into a terminal Di1 of an FiFo 4A for leading in an FiFo (first-in first-out) part. Pattern data Pda, i.e., Dc, which are inverted with an inverter 321 of a format encoding circuit 32 are inputted into a terminal Di2. Meanwhile, data Db of an AND gate 322 are inputted into a terminal Di1 of an FiFo 4B for trailing, and data Dd of an AND gate 323 are inputted into a treminal Di2. The data stored in the FiFo beforehand are outputted into an RS flip-flop 35 based on a leading CLK and a trailing clock TCK. Therefore, an invalid time, which is generated when the data are switched with the format encoding circuit 32, is not formed, and the malfunction can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator for, for example, an LSI tester, and more particularly to a digital pulse by eliminating an unvalidated period which cannot be set by switching the output of a format encoder. The present invention relates to a waveform generator capable of arbitrarily setting a waveform.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the configuration of a conventional waveform generator. In the figure, 1 is a timing generator for generating a test rate signal S which serves as a reference for operation timing.
2 is a pattern generator, and a timing generator 1
Of the test rate signal S, and outputs the pattern data Pda generated based on the test rate signal S to the formatter 3.

In the formatter 3, reference numeral 31 is a retiming register, which is a pattern data Pda of the pattern generator 2.
Timing generator 1's pattern clock PCK
Based on the above, the retiming is performed and the result is taken into the formatter 3. Numeral 32 is a formatter encoding circuit, which is based on the pattern data Pda fetched by the retiming register 31 and the data (D1, D0) of the format register 33, and which is a format matrix. To 34.

The format matrix 34 includes data for the formatter encoding circuit 32 and a timing generator.
Reading clock LCK and tray output
The RS flip-flop 35 is set / reset based on the ring clock TCK. That is, the RS flip-flop 35 outputs from the Q terminal a digital pulse waveform that is formatted based on the output of the format matrix 34.

FIG. 6 is a time chart for explaining the operation of the conventional waveform generator, in which (A) is a test rate signal S,
(B) is the pattern data Pad, (C) is the pattern clock PCK, (D) is the pattern data Pad * retimed by the retiming register 31, and (E) is the format encoder. The output of the read circuit 32, (F) is the reading clock LCK, and (G) is the trailing clock T.
CK, (H) to (J) are outputs of the RS flip-flop 35, and have NRZ (Non Return to Zero) waveform and RZ (Retur).
n ZERO) waveform and RO (Return to One) waveform are shown. Incidentally, FIG. 7 shows a truth table of the format register 33, and FIG. 8 shows a truth table of the operating state of the present waveform generator.

(1) The pattern generator 2 outputs the pattern data Pad to the retiming register 31 based on the test rate signal S of the timing generator 1. (2) The retiming register 31 uses the pattern data Pad.
Timing generator 1's pattern clock PCK
Re-timed by the format encoding circuit 3
Output to 2.

(3) The format encoding circuit 32 outputs the encoded data to the format matrix 34 based on the data of the retiming register 31 and the format register 33. Format matrix 3
4 is based on the data of the format encoding circuit 32 and the reading clock LCK and the trailing clock TCK of the timing generator 1, and the following (4)
The RS flip-flop 35 is controlled by the processes (9) to (9).

(4), (5) RS flip-flop 35 to N
When the RZ waveform is output, that is, when the data of the format register 33 is (0, 0), when the pattern data Pda is "1", the RS flip-flop 35 rereads.
It is set at the rising of the reading clock LCK, and is reset by the rising of the reading clock LCK when the pattern data Pda is "0".

(6), (7) RS flip-flop 35 to R
When the Z waveform is output, that is, when the data of the format register 33 is (0, 1), the pattern data P
When da is "1", the RS flip-flop 35 is set by the rising of the reading clock LCK,
It is reset by the rising of the trailing clock TCK. Also, when the pattern data Pda is "0",
The RS flip-flop 35 has a reading clock L.
It is reset by the rising edge of CK.

(8), (9) RS flip-flop 35 to R
When the O waveform is output, that is, when the data of the format register 33 is (1, 0), the pattern data P
When ad is "1", the RS flip-flop 35 is
It is reset by the rising of the rig clock TCK,
It is set at the rising edge of the reading clock LCK. When the pattern data Pad is "1", R
The S flip-flop 35 has a reading clock LC.
Set by rising K.

[0011]

In such a conventional waveform generator, the unvalidated time (U and V are omitted in the figure) each time the output of the format encoding circuit is switched.
Therefore, the waveform setting cannot be arbitrarily performed because the timing signal must be generated while avoiding this time. Further, if the output of the format encoding circuit becomes invalid when the reading clock or the trailing clock is at high level, an erroneous set or reset pulse may be generated, which may cause a malfunction.

The present invention has been made in view of the above circumstances, and a storage circuit for storing the data encoded by the format encoding circuit in advance is provided to cut off the output of the format encoding circuit. The purpose of the invention is to provide a waveform generator capable of eliminating an erroneous operation and arbitrarily setting a waveform by preventing an invalid time from being generated each time it is changed.

[0013]

SUMMARY OF THE INVENTION In order to achieve such an object, the present invention provides a pattern data and a format data.
RS based on the data encoded by the format encoding circuit based on the data and the reading clock / trailing clock output by the timing generator.
A waveform generator that sets / resets a flip-flop and obtains an arbitrary digital pulse waveform, based on a pattern clock output from the timing generator by the data encoded by the format encoding circuit. The timing generator and
It is characterized in that it is provided with a memory circuit for reading out based on a reading clock and a trailing clock.

[0014]

The data encoded by the format encoding circuit based on the pattern data and the format data is stored in the storage circuit, and the reading clock of the timing generator is output from this data. And the trailing clock, the NRZ, RZ, and RO waveforms are extracted in an arbitrary form.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the waveform generator of the present invention. In the figure, components having the same functions as those in FIG. Hereinafter, the same applies in the drawings. 4 is a FiFo (first-in first-out) part,
The data input from the formatter encoding circuit 32 is taken out in the order of input and output to the format matrix 35.

The FiFo unit 4 is provided with two (2 bits × n words) FiFo 4A and 4B. One FiFo 4A is for reading and the other FiFo 4A.
4B is used for trailing.

The FiFo4A has a data Da at the Di1 terminal.
(In this case, the pattern data Pda) is input, and the pattern data Pda (hereinafter referred to as data Dc) inverted by the inverter 32 1 of the format encoder 32 is input to the Di2 terminal. Has been done. This data Da, c is written by the pattern clock PCK of the timing generator 1 input to the input clock terminal and the inverted reading clock L input to the output clock terminal.
It is read from the output terminals Do1 and Do2 by CK (hereinafter, an inverted signal is indicated by ⋄ and is indicated by LCK⋄).

On the other hand, FiFo4B is ANDed to the Di1 terminal.
The data Db of the gate 322 is input, and the AN is connected to the Di2 terminal.
The data Dd of the D gate 323 is input.

The AND gate 322 receives the pattern data Pad inverted by the inverter 321 at one input terminal and the format register 33 at the other input terminal.
Data D1 has been input. AND gate 323
The pattern data Pad is input to one input terminal and the data of the format register 33 is input to the other input terminal.
Input D0.

These data Db, d input to the FIFO4B are written by the pattern clock PCK of the timing generator 1 input to the input clock terminal, and the trailing input to the output clock terminal. It is read from the output terminals Do1 and Do2 by the clock TCK⋄.

In the format matrix 34, 3
41 is an AND gate having one input terminal to which the data Da * of the output terminal Do1 of the FiFo4A is input, and the other input terminal to which the reading clock LCK output from the timing generator 1 is input. ing. 342 is an AND gate to which the data Db * of the output terminal Do1 of the FiFo4B is input to one input terminal, and the trailing clock TC output from the timing generator 1 to the other input terminal.
K has been entered. Reference numeral 343 is an OR gate having AND gates 341 and 342 connected to its input terminals, and its output signal is connected to the set terminal of the RS flip-flop 35.

Reference numeral 344 is an AND gate having one input terminal to which the data Dc * of the output terminal Do2 of the FiFo4A is input, and the other input terminal to the trailing clock TCK output from the timing generator 1. Has been entered.
345 is the output terminal Do2 of FiFo4B at one input terminal
Of the data Dd * is input to the other input terminal of which the trailing clock TCK output from the timing generator 1 is input. 346 is an OR gate in which AND gates 344 and 345 are connected to the input terminals.
The output signal is connected to the reset terminal of the RS flip-flop 35.

FIG. 2 is a block diagram showing a structure in which the FiFo unit, which is a main part of the present invention, is extracted and shown. The FiFo will be described as a representative of the reading FiFo 4A. In the figure, 41 is a register part, which is a format
Data Da is input from the input circuit 32 to the input terminal Di1.

In the register unit 41, 411-414
Is an AND gate, the data Da is input to one input terminal, and the inverted output of the demultiplexer 43 output based on the 2-bit read counter 42 is input to the other input terminal. .. For example, the demultiplexer 43
When the read count is "0", only the output terminal S0 outputs a low level signal, and the output terminals S1 to S3 output a high level signal.

Reference numerals 415 to 418 are AND gates to which the output signals of the D-type flip-flops 419 to 4112 are input to one input terminal, and the AND gate 41 to the other input terminal.
Like 1 to 414, the output signal of the demultiplexer 43 is input.

Reference numerals 4113 to 4116 are OR gates, and the output signals of the AND gates 411 to 414 are input to one input terminal, and the AND gate 4 is input to the other input terminal.
The output signals of 15 to 418 are connected. The output signals of the OR gates 4113-4116 are input to the D terminals of the D-type flip-flops 419-4112, and the D-type flip-flops 419-41 based on the pattern clock signal PCK input to the clock terminals. 4112.

Reference numeral 4117 is a data selector which selects the outputs of the D-type flip-flops 419 to 4112 based on the data output from the 2-bit read counter 44 and outputs the data Da * from the output terminal Do1. To do. Read counter 44
Is the reading clock L input to the clock terminal
The signal counted up by CK⋅ is output to the data selector 4117.

Reference numeral 45 is a register portion provided at the input terminal Di2.

FIG. 3 is a time chart for explaining the operation of the FiFo section, in which (A) is a pattern clock PC.
K and (B) are data Dam (m =
1 to n) and (C) are count values of the read counter 42,
(D) to (G) are D-type flip-flops 419 to 4112.
Q output, (H) is the inverted signal of the reading clock LCK, (I) is the count value of the read counter 44,
(J) is an output signal Dam * output from the output terminal Do1.

(1) The D-type flip-flop 419 writes the data Da1 by the input of the pattern clock PCK. At this time, the read counter 42 is also incremented to "1" by this pattern clock PCK and designates the D-type flip-flop 4110 to write the next data Da2. (2) On the other hand, since the read counter 44 is "0", the data Da1 of the D-type flip-flop 419 is directly output from the output terminal of the data selector 4117 to the AND gate 341.

(3) When the next data Da2 is input from the Di1 terminal and the pattern clock PCK is input to each lock terminal, the D-type flip-flop 4110 writes the data Da2. (4) Thereafter, the D-type flip-flop 4 is processed by the same process.
Data Da3 and Da4 are written in 111 and 4112.

(5) The reading of the data Da2 to Da4 is performed based on the reading clock LCK. The reading clock LCK is applied to the clock terminal of the read counter 44.
When ⋄ is input, the read counter 44 is incremented to "1" and the data Da2 stored in the D-type flip-flop 4110 is output from the output terminal D01 of the data selector 4117 to the AND gate 341. To do. (6) Hereinafter, the same process is performed for the data Da3 and Da4.

FIG. 4 is a time chart for explaining the operation of the waveform generator of the present invention, in which (A) is a pattern clock P.
CK, (B) is the pattern data Pda, (C) is FiFo
Data Dam input to the input terminal Di1 of 4A, (D) is data Dbm input to the input terminal Di1 of FiFo4B,
(E) is the data input to the input terminal Di2 of FiFo4A
Data Dcm, (F) is the data Ddm input to the input terminal Di2 of the FiFo4B, and (G) is the output terminal Do1 of the FiFo4A.
From the output terminal D01 of the FiFo4B is data Dbm *, and (I) is F.
Data output from the output terminal D02 of iFo4B Ddm *
, (J) is the reading clock LCK, (K) is the trailing clock TCK, and (L) is the output of the RS flip-flop 35. Incidentally, here, when the data of the format register 33 is (0, 1), that is, RZ
A case of obtaining a waveform will be described.

(1) The data Da to Dd based on the pattern data Pad are input to the pattern clock PCK to be F.
Written to the iFo 4A, 4B. (2) Data Da to D written in FiFo4A and 4B
d is because the read counter 44 is "0",
The data is output as it is from the output terminal Do1,02 as Da * to Dd *.

(3) After this, the reading clock LCK
Is output from the timing generator 1 to the FiFo4A and the format matrix 34. At this time, FiFo
4A is a high level signal from the output terminal Do1 (hereinafter referred to as data
Data Da *) is output to the AND gate 341. AND
The gate 341 is the data Da * and the data from FiFo4A.
A high level signal is output to the OR gate 342 based on the Ding clock LCK (see FIG. 1). The RS flip-flop 35 is set based on the signal of the OR gate 342, and the Q output becomes high level. At this time, both the AND gates 344,6 and the OR gate 345 on the reset side are low level signals.

(4) The FiFo4A continues to read the read counter 44 when the reading clock LCK falls.
Is incremented to "1" to select the next data (data of the D flip-flop 4110). But F
The iFo4A becomes invalid because the next data has not been input yet. (5) When the next pattern clock PCK is input, Fi
The following data Da2 to Dd2 are written in Fo4A and 4B. At this time, since the read counter has already become "1", the data Da2 * and Dc2 * are directly output from the output terminals Do1 and D02. At this time, FiFo4
The read counter of B remains "0" and Db * and Dd * are read.

(6) Next, the trailing clock TCK is output from the timing generator 1 to the FiFo4B and the format matrix 34. By inputting the trailing clock TCK, the AND gate 346 becomes Fi
Data Dd * from Fo4B and trailing clock TC
Based on K, a high level signal is output to the OR gate 345. The RS flip-flop 35 is an OR gate 34.
It is reset based on the high level signal output by 5, and the Q output is inverted to the low level signal.

(7) When the trailing clock falls, the FiFo4B increments the read counter to "1" and selects the next data. However, FiFo
In 4B, the next data has not been input yet,
Become invalid. (8) The reading clock LCK is output from the timing generator 1 to the FiFo4A and the format matrix 34 again. However, the RS flip-flop does not change because the data Da2 * of FiFo4A is a low level signal. The FiFo 4A selects the next data (data of the D-type flip-flop 4111) at the falling edge of the reading clock LCK. However, FiFo4A becomes invalid because the next data has not been input yet. (9) After that, the processes of (1) to (7) are repeated. still,
If data is stored up to the D-type flip-flops (four stages in this case) at the final stage before the trailing clock is input, a malfunction occurs, so the number of D-type flip-flops should be increased. It is better to configure it. By doing so, the settable range can be expanded to several rates.

[0039]

As described above in detail, the waveform generating apparatus of the present invention includes the encoding code of the format encoding circuit previously stored by the FiFo for reading and the FiFo for trailing. RS data based on the reading clock / trailing clock.
The output is made to a flip-flop. For this reason, the format encoding circuit has been
Since the unvalidated time that has been generated each time the data is switched does not occur, malfunction can be prevented and the waveform can be arbitrarily set.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a waveform generator of the present invention.

FIG. 2 is a configuration block diagram showing an extracted FiFo unit, which is a main part of the present invention.

FIG. 3 is a time chart for explaining the operation of the FiFo unit.

FIG. 4 is a time chart explaining the operation of the waveform generator of the present invention.

FIG. 5 is a configuration block diagram of a conventional waveform generator.

FIG. 6 is a time chart for explaining the operation of the conventional waveform generator.

7 is a diagram showing a truth table of the format register 33. FIG.

FIG. 8 is a diagram showing a truth table of operating states of the waveform generator.

[Explanation of symbols]

 32 Format Encode Circuit 33 Format Register 34 Format Matrix 4 FiFo Section 4A, 4B FiFo

Claims (1)

[Claims] 1. A data encoded by a format encoding circuit based on pattern data and format data.
A waveform generator for setting and resetting an RS flip-flop based on a reading clock and a trailing clock output from a timing generator to obtain an arbitrary digital pulse waveform. A storage circuit for storing the data encoded by the read circuit based on the pattern clock output from the timing generator and for reading based on the reading clock and the trailing clock of the timing generator. A waveform generator characterized by being provided with.