JPH048704Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a vertical synchronization separation circuit used in television receivers, video tape recorders, etc.

(B) Prior Art As is well known, various vertical synchronization separation circuits have been proposed in the past, one of which is disclosed in Japanese Patent Application Laid-Open No. 57-50176 filed by the present applicant. . That is, in this conventional example, the charging sensitivity of the charging/discharging circuit that integrates the composite synchronizing signal is increased during the vertical synchronizing pulse period, thereby making it possible to reliably separate the vertical synchronizing signal.

According to the above conventional circuit, the pulse width of the vertical synchronization pulse V is selected to be approximately 0.5H (H: horizontal scanning period) in the composite synchronization signal of a normal television broadcast signal as shown in FIG. 2a. Therefore, a large integrated output voltage can be obtained for this vertical synchronization signal section.
However, in a composite synchronization signal obtained by playing back a video tape recorded to prevent dubbing, the pulse width of the vertical synchronization pulse V is about 1/3 of that in the case shown in Fig. 2a (Fig. 2c), and vertical sync pulse only
It is 0.5H wide (Fig. 2b), so
There is a problem in that a large integrated voltage cannot be obtained for these vertical synchronization pulse portions, and therefore, the vertical synchronization signals cannot be reliably separated.

To solve this problem, it is necessary to increase the charging sensitivity of the integrating charge/discharge circuit to the extent that a sufficiently large integrated output can be obtained even for the signals shown in Figure 2 b and c. However, with such a method, the sensitivity would be too high and would result in malfunctions due to noise.

(c) Problems to be solved by the invention In consideration of the above-mentioned circumstances, the invention provides a vertical synchronization signal for both normal television broadcast signals and playback signals of videotapes recorded with anti-dubbing. The objective is to be able to reliably and accurately separate the signals and to prevent malfunctions caused by noise.

(d) Means for solving the problem In order to solve the above problem, the present invention provides switching in response to a switching pulse that starts a little before the leading edge of the vertical synchronizing signal period and ends during the vertical synchronizing signal period. The switching separation sensitivity control circuit increases the charging current of the integrating capacitor of the composite synchronizing signal and reduces the discharging current during the period of the switching pulse.

(e) Effect By configuring as described above, the integrated output voltage obtained from the integrating capacitor rises significantly at the leading edge of the vertical synchronization signal section, and then slowly decreases for a while, so that the vertical synchronization A large integrated output voltage is obtained at least at the leading edge of the signal section, and therefore, by comparing this output voltage with a constant voltage, a vertically separated output pulse can be obtained.

(f) Embodiment Figure 1 shows an embodiment of the present invention, in which 1 is an input terminal for a television video signal or a reproduced video signal from a VTR (video tape recorder), etc., and 2 is an input terminal for each video signal. It is a synchronous separation circuit that is
This synchronization separation circuit outputs a composite synchronization signal of positive polarity as shown in Figure 3 (a) (for television video signals) or Figure 4 (a) (for VTR playback video signals), and each of these signals is used for charging and discharging. It is applied to the base of the switching transistor Tr1 (switching means). Therefore, the above transistor
Tr ₁ is turned on during each pulse period of the horizontal synchronizing pulse H and vertical synchronizing pulse V in each of the composite synchronizing signals I, and the integrating capacitor C is charged, and the capacitor C is discharged during the other periods.

On the other hand, since a sensitivity switching pulse (this pulse will be explained in detail later) is applied to terminal 3 at a timing as shown in FIG. 3D or FIG. During this pulse period, one constant current transistor Tr4 (second charging circuit) constituting the sensitivity control circuit is turned on, and the other constant current transistor Tr5 (second discharge circuit) is turned off.

Therefore, the first one in the composite synchronization signal
~For two vertical synchronization pulses, the integration capacitor C is charged via the constant current transistor Tr2 (first charging circuit), which forms the main charging path, and the constant current transistor _Tr4 of the sensitivity control circuit. Since this is carried out, a large charge flow will flow. In addition, during the period between the above-mentioned one to two vertical synchronization pulses, the discharge of the integrating capacitor C is caused by the constant current transistor Tr3 (first discharge circuit) forming the main discharge path.
This is done only through Therefore, in the case of the composite synchronization signal shown in Figure 3A, after the arrival of the first vertical synchronization pulse in this signal, the integrated output voltage at point A has a sufficiently large value that exceeds the level V _s described later, as shown in Figure 3B. become. Further, in the case of the composite synchronizing signal shown in FIG. 4A, the integrated output voltage at point A exceeds the above level _Vs after the arrival of the second vertical synchronizing pulse in this signal, as shown in FIG. 4B.

Note that, outside the pulse period of the switching pulse 2, the constant current transistor Tr ₄ of the sensitivity control circuit is off and Tr ₅ is on, so that the integration capacitor C is charged only through the constant current transistor Tr ₂ . , discharge is performed via constant current transistors Tr ₃ and Tr ₅ . Therefore, the integrated output voltage at point A at this time becomes sufficiently small.

Then, the integrated output voltage ro is input to a comparator composed of differential pair transistors Tr ₆ and Tr ₇ ,
It is compared with the constant voltage V _s obtained at point B. Therefore,
Output transistor connected after this comparator
The emitter of Tr ₈ , that is, the output terminal 4 has the terminals shown in Figures 3 and 4.
In each case in the figure, a negative polarity vertically separated output pulse C is obtained as shown.

Here, the vertical separation output pulse c is as follows:
Since it is sufficient that the pulse width be located within the vertical synchronization signal period of the composite synchronization signal and have a pulse width of about 0.6H or more, the sensitivity switching pulse 2 is selected as described above so as to obtain such an output pulse. That is, when the vertical pulse generating circuit provided at the subsequent stage of the vertical separation circuit of this embodiment is constituted by a normal pulse oscillation circuit, the sensitivity switching pulse 2 is generated by the oscillation output pulse or the vertical blanking obtained from the vertical output stage. The switching pulse can be created using a monostable multivibrator or the like based on the pulse, and the pulse width of the switching pulse obtained in this case becomes constant.

Further, if the vertical pulse generation circuit is configured in a countdown type by frequency division of horizontal pulses, the sensitivity switching pulse can be directly taken out from the countdown circuit. That is, in this case, for example, the aforementioned sensitivity switching is used to generate a pulse that starts when the countdown circuit counts the 262nd horizontal pulse and ends when the countdown circuit obtains the aforementioned vertical separation output pulse and is reset. It may be a pulse. That is, in Figs. 3 and 4, pulse d indicates the sensitivity switching pulse when configured in this way, and pulse d indicates the timing of the 2f _H pulse (f _H : horizontal frequency) immediately after the vertical separation output pulse d. This shows the reset pulse generated at Therefore, in this case, the pulse width of the sensitivity switching pulse 2 is different between FIG. 3 and FIG. 4 as shown in the figure.

(g) Effects of the invention According to the invention, it is possible to increase the integrated output voltage for the vertical synchronization signal portion of the composite synchronization signal, thereby preventing dubbing recording in which the pulse width of the vertical synchronization pulse is narrowed. The vertical synchronization signal can be reliably separated even from a reproduced signal of a video tape or the like which has been subjected to the above processing. Moreover, this is achieved by increasing the charging current of the integrating capacitor and reducing the discharging current, so it is not as noise sensitive as the above-mentioned method of sufficiently increasing only the charging sensitivity of the capacitor. There is no possibility of malfunction.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a diagram showing the signal waveform of a composite synchronization signal input to this embodiment, and Figs. 3 and 4 are diagrams showing two different embodiments of the above embodiment. FIG. 3 is a signal waveform diagram showing each operation mode. 2...Synchronization separation circuit, Tr ₄ , Tr ₅ ... Constant current transistor constituting the separation sensitivity switching circuit, Tr ₆ ,
Tr ₇ ...Transistor composing the comparator, d...
Sensitivity switching pulse.

Claims (1)

[Claims for Utility Model Registration] An integrating capacitor that is charged and discharged in response to a composite synchronization signal, a charging circuit connected in series to the integrating capacitor, and a discharging circuit connected in parallel to the integrating capacitor. and switching means arranged in series between the charging circuit and the integrating capacitor and switching between charging and discharging of the integrating capacitor in response to a composite synchronization signal, and switching means for switching the charging and discharging of the integrating capacitor to a constant voltage. a comparator that compares and separates the vertical synchronizing signal; a second charging circuit provided in parallel with the charging circuit; and a second discharging circuit provided in parallel with the discharging circuit; The second charging circuit is operated and the second discharging circuit is stopped when a switching pulse is applied that starts slightly before the front end and ends during the vertical synchronization signal period, and the second charging circuit is activated when the switching pulse is not applied. A vertical synchronization separation circuit comprising: a separation sensitivity control circuit that stops the second discharge circuit and operates the second discharge circuit.