JPH0474605A - Punching method - Google Patents
Punching methodInfo
- Publication number
- JPH0474605A JPH0474605A JP18723190A JP18723190A JPH0474605A JP H0474605 A JPH0474605 A JP H0474605A JP 18723190 A JP18723190 A JP 18723190A JP 18723190 A JP18723190 A JP 18723190A JP H0474605 A JPH0474605 A JP H0474605A
- Authority
- JP
- Japan
- Prior art keywords
- marking
- wafer
- line
- mold
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004080 punching Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000003754 machining Methods 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 20
- 238000005520 cutting process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Processing Of Stones Or Stones Resemblance Materials (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は打ち抜き加工方法に係り、特に半導体ウェハ等
、もろく、靭性の少ない平板を所定形状、例えば円形に
打ち抜くための加工方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a punching method, and particularly to a processing method for punching a brittle, low-toughness flat plate such as a semiconductor wafer into a predetermined shape, for example, a circle. .
半導体ウェハ等の切断加工は円形以外の不定形ウェハを
円形ウェハに加工する前工程として行われる。Cutting of semiconductor wafers and the like is performed as a pre-process for processing irregularly shaped wafers other than circular ones into circular wafers.
従来、不定形ウェハを切断加工する方法としてスクライ
バ−(ケガキ針)を用いて該ウェハに所定のケガキ線加
工を行い、人手で半導体ウェハのケガキ線の両側をつか
み注意深く割っていた。Conventionally, as a method for cutting irregularly shaped wafers, a scriber (scriber) is used to create a predetermined scribe line on the wafer, and then the semiconductor wafer is manually grasped on both sides of the scribe line and carefully split.
上記のように不定形半導体ウェハの切断加工は従来、人
手を用いて人為的に行っていたがこのような人為的作業
では加工作業に熟練を要し、個人差のある作業である、
人手作業のため、作業に時間を要する、また半導体ウェ
ハの切断加工近傍に割れが発生する、手に怪我をする危
険がある等の問題を生じた。As mentioned above, the cutting of irregularly shaped semiconductor wafers has traditionally been done manually, but such manual work requires skill and varies from person to person.
Since the process is done manually, it takes time, and there are problems such as cracks occurring near the cutting process of the semiconductor wafer and the risk of injury to the hands.
本発明は上記問題を解決したものであり、個人差のない
、能率を向上させた加工法を提供することを目的とする
。The present invention solves the above problems, and aims to provide a processing method that is free from individual differences and has improved efficiency.
上記課題は本発明によればもろく、靭性の少ない平板状
の物質を所望形状に打ち抜き加工する際に、
前記所望形状のケガキ線加工を前記平板状物質に施し、
前記所望形状を有し且つ該所望形状よりわずかに小さい
凸状型と前記所望形状を有し且つ該所望形状よりわずか
に大きい凹状型との一対の型を用いて前記平板状の物質
を打ち抜くことを特徴とする打ち抜き加工方法によって
解決される。According to the present invention, when punching a brittle and low-toughness flat material into a desired shape, the above-mentioned problem is solved by performing marking line processing on the flat material in the desired shape,
Punching the flat material using a pair of dies: a convex die having the desired shape and slightly smaller than the desired shape, and a concave die having the desired shape and slightly larger than the desired shape. This problem is solved by a punching method characterized by:
本発明ではもろく、靭性の少ない平板状物質が半導体ウ
ェハ例えばGaAs等が好ましく用いられる。In the present invention, a semiconductor wafer such as GaAs is preferably used as a brittle and flat plate-like material having low toughness.
また上記わずかな距離が1〜2 mmであることがケガ
キ線の加工誤差を吸収でき半導体ウェハに無理な力がか
からないとの理由で有効である。Further, it is effective that the above-mentioned slight distance is 1 to 2 mm because processing errors of the marking lines can be absorbed and no undue force is applied to the semiconductor wafer.
本発明によれば半導体ウェハ等の粗円形等の打ち抜き加
工が機械的にしかも安全確実になされ生産性向上にも寄
与しろる。本発明では粗円形のみを実施例に示したが方
形、台形等積々の形状の打ち抜き加工が可能である。According to the present invention, rough circular punching of semiconductor wafers, etc. can be performed mechanically, safely and reliably, and it can also contribute to improved productivity. In the present invention, only a rough circular shape is shown in the embodiment, but it is possible to punch out a variety of shapes such as a rectangular shape and a trapezoid shape.
以下本発明の実施例を図面にもとすいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図及び第2図は本発明の方法を実施するための概略
図及び第1図の部分拡大断面図(B−B面)である。ま
た第3図は本発明の詳細な説明するための斜視図である
。1 and 2 are schematic diagrams for carrying out the method of the present invention and a partially enlarged cross-sectional view (plane BB) of FIG. 1. Further, FIG. 3 is a perspective view for explaining the present invention in detail.
第2図、第3図に示すように直径約50証の略円形のケ
ガキ線3を約0.1肚の深さに入れた直径100 mm
以下(例えば70mm)厚さ0.5〜1m[Il程度の
GaAs等の半導体ウェハ1を支持台2に載置し、真空
吸着により固定する。As shown in Figures 2 and 3, a roughly circular marking line 3 with a diameter of approximately 50 cm is placed at a depth of approximately 0.1 degrees, with a diameter of 100 mm.
A semiconductor wafer 1 of GaAs or the like having a thickness of about 0.5 to 1 m (about 70 mm) is placed on a support base 2 and fixed by vacuum suction.
支持台2は第1図及び第3図でよくわかるように円形上
型5に対する下型の役割を有する。As can be clearly seen in FIGS. 1 and 3, the support base 2 serves as a lower mold for a circular upper mold 5.
下型2の外形は目的の打ち抜き用ケガキ線にはゾ沿った
形状とし、ケガキ線の内側約1〜2mになるようにする
。The outer shape of the lower die 2 is shaped to follow the intended marking line for punching, and is approximately 1 to 2 m inside the marking line.
そのように半導体ウェハ1、支持台2を配置し、第1図
に示した打ち抜き加工装置で加工する。第1図″に示し
た打ち抜き加工装置の上型5は、粗円形打ち抜き加工の
場合第3図に示すようにドーナツ状をしており、支持台
2、ケガキ線3が入った半導体ウェハ1、及び該上型5
のそれぞれの位置関係が第2図によく示されている。Semiconductor wafer 1 and support stand 2 are arranged in this manner and processed using the punching apparatus shown in FIG. The upper die 5 of the punching device shown in FIG. 1'' has a donut shape as shown in FIG. and the upper mold 5
The respective positional relationships are clearly shown in FIG.
本実施例の場合ケガキ線3から下型の支持台2の外径2
a及び上型5の内径5a迄の距離をそれぞれ1〜2mに
する。このような配置からモータ4等により、駆動凹状
上型5をゆっくり下降させ、半導体ウェハに接触すると
該ウエノ1は所望のケガキ線3形状通り切断され粗円形
ウェハを得る。In this example, from the marking line 3 to the outer diameter 2 of the lower die support stand 2
The distances between a and the inner diameter 5a of the upper die 5 are each 1 to 2 m. From this arrangement, the drive concave upper die 5 is slowly lowered by the motor 4 or the like, and when it comes into contact with the semiconductor wafer, the wafer 1 is cut along the desired scribe line 3 shape to obtain a roughly circular wafer.
以上説明した様に本発明によれば、半導体ウェハ等の切
断加工が、機械によって行え、作業時間が短縮できると
共に、ウェハの割れも減少することが期待できる。As explained above, according to the present invention, cutting of semiconductor wafers, etc. can be performed by a machine, and it is expected that working time can be shortened and cracking of wafers can be reduced.
また、ケガキ線を入れる作業も機械化することにより、
この工程をすべて自動化することができるようになり省
力化に多大の効果がある。In addition, by mechanizing the work of marking lines,
This process can now be completely automated, resulting in significant labor savings.
第1図は本発明の方法を実施するための概略図であり、
第2図は第1図の部分拡大断面図(B−B面)であり、
第3図は本発明の詳細な説明するための斜視図である。
1・・・半導体GaAsウェハ、
2・・・支持台(下型:凸状)、
3・・・ケガキ線、 4・・・モータ、5・・・
上型
(凹状)FIG. 1 is a schematic diagram for carrying out the method of the present invention, FIG. 2 is a partially enlarged sectional view (B-B plane) of FIG. 1, and FIG. 3 is a detailed explanation of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor GaAs wafer, 2... Support stand (lower mold: convex shape), 3... Marking line, 4... Motor, 5...
Upper mold (concave)
Claims (1)
ち抜き加工する際に、 前記所望形状のケガキ線加工を前記平板状物質に施し、
前記所望形状を有し且つ該所望形状よりわずかに小さい
凸状型と前記所望形状を有し且つ該所望形状よりわずか
に大きい凹状型との一対の型を用いて前記平板状の物質
を打ち抜くことを特徴とする打ち抜き加工方法。 2、前記平板状の物質を凸状型に固定することを特徴と
する請求項1記載の方法。 3、前記もろく、靭性の少ない平板状物質が半導体ウェ
ハであることを特徴とする請求項1記載の方法。 4、前記わずかな距離が1〜2mmであることを特徴と
する請求項1記載の方法。[Claims] 1. When punching a brittle, low-toughness flat material into a desired shape, marking the desired shape on the flat material;
Punching the flat material using a pair of dies: a convex die having the desired shape and slightly smaller than the desired shape, and a concave die having the desired shape and slightly larger than the desired shape. A punching method characterized by: 2. The method according to claim 1, characterized in that the flat material is fixed in a convex shape. 3. The method of claim 1, wherein the brittle, low-toughness planar material is a semiconductor wafer. 4. A method according to claim 1, characterized in that said slight distance is 1-2 mm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18723190A JPH0474605A (en) | 1990-07-17 | 1990-07-17 | Punching method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18723190A JPH0474605A (en) | 1990-07-17 | 1990-07-17 | Punching method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0474605A true JPH0474605A (en) | 1992-03-10 |
Family
ID=16202355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18723190A Pending JPH0474605A (en) | 1990-07-17 | 1990-07-17 | Punching method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0474605A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994005476A1 (en) * | 1992-08-31 | 1994-03-17 | New Man International Co., Ltd. | Stone cutting method and device |
JP2011096925A (en) * | 2009-10-30 | 2011-05-12 | Lintec Corp | Removing device and removing method of convex portion in semiconductor wafer |
JP2011096924A (en) * | 2009-10-30 | 2011-05-12 | Lintec Corp | Device and method for removing projection of semiconductor wafer |
JP2015159317A (en) * | 2015-04-20 | 2015-09-03 | パナソニックIpマネジメント株式会社 | Method for cutting semiconductor substrate, method for cutting solar battery, and solar battery |
CN105437388A (en) * | 2014-08-08 | 2016-03-30 | 江俊昇 | Method and device thereof for punch forming of fragile board |
-
1990
- 1990-07-17 JP JP18723190A patent/JPH0474605A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994005476A1 (en) * | 1992-08-31 | 1994-03-17 | New Man International Co., Ltd. | Stone cutting method and device |
JP2011096925A (en) * | 2009-10-30 | 2011-05-12 | Lintec Corp | Removing device and removing method of convex portion in semiconductor wafer |
JP2011096924A (en) * | 2009-10-30 | 2011-05-12 | Lintec Corp | Device and method for removing projection of semiconductor wafer |
CN105437388A (en) * | 2014-08-08 | 2016-03-30 | 江俊昇 | Method and device thereof for punch forming of fragile board |
JP2015159317A (en) * | 2015-04-20 | 2015-09-03 | パナソニックIpマネジメント株式会社 | Method for cutting semiconductor substrate, method for cutting solar battery, and solar battery |
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