JPH0465549B2 - - Google Patents
Info
- Publication number
- JPH0465549B2 JPH0465549B2 JP54037426A JP3742679A JPH0465549B2 JP H0465549 B2 JPH0465549 B2 JP H0465549B2 JP 54037426 A JP54037426 A JP 54037426A JP 3742679 A JP3742679 A JP 3742679A JP H0465549 B2 JPH0465549 B2 JP H0465549B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- drain
- source
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000004335 scaling law Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置に関し、特に短いチヤネ
ル長を有する構造において、パンチスルー耐圧を
高め、所望のしきい値電圧を持ち、ホツトエレク
トロン発生を阻止し得るように構造を工夫したも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure having a short channel length, which has a structure that increases punch-through withstand voltage, has a desired threshold voltage, and can prevent the generation of hot electrons. It was devised.
大規模集積回路、特に大容量メモリにはチヤネ
ル長1μｍ前後のMOS FETが使用される。この
ような短チヤネルMOS FETを従来の長チヤネ
ルMOS FETと同一の構造で、たゞ“スケーリ
ング”の原理で縮小して作ろうとすると種々の問
題に当面する。即ち、この縮少によりソース、ド
レイン拡散深さxjは浅くなるが、余り浅くすると
拡散抵抗が高くなり、高速動作に不利になる。抵
抗を小にするためxjを深くすると空乏層によるチ
ヤネルモジユレーシヨンが起り、正常なオンオフ
動作が不可能になる。この矛循を避けるためソー
ス、ドレインを第１図に示すように深い部分と浅
い部分とで構成することが考えられているが、面
積および工程数が増える。またチヤネル長が小に
なる程低電圧でパンチスルーが生じるが、このパ
ンチスルー耐圧を高めるため基板の不純物濃度を
高くすると接合容量が増大して高速動作に不利と
なり、接合耐圧が低下し、バツクゲート効果が大
きくなつて不利である。かゝる不利を避けるため
ソース，ドレイン間に高濃度および低濃度二層の
チヤネルを形成させる二重チヤネルドープ構造が
提案されているが、これも接合耐圧が低下し、ま
たチヤネルからゲートに電子が飛込みこれがゲー
ト絶縁膜にトラツプされてしきい値電圧Vthを変
化させるホツトエレクトロン効果が無視できなく
なる欠点がある。 MOS FETs with a channel length of around 1 μm are used for large-scale integrated circuits, especially large-capacity memories. If one tries to make such a short channel MOS FET with the same structure as a conventional long channel MOS FET, but only by scaling it down based on the principle of "scaling", various problems arise. That is, this reduction makes the source and drain diffusion depth x j shallower, but if it is made too shallow, the diffusion resistance increases, which is disadvantageous for high-speed operation. If x j is made deep to reduce resistance, channel modulation occurs due to the depletion layer, making normal on/off operation impossible. In order to avoid this contradiction, it has been considered to configure the source and drain into a deep part and a shallow part as shown in FIG. 1, but this increases the area and number of steps. In addition, punch-through occurs at low voltages as the channel length becomes smaller, but if the impurity concentration of the substrate is increased to increase the punch-through voltage, the junction capacitance increases, which is disadvantageous for high-speed operation, lowers the junction voltage, and reduces the back gate voltage. This is disadvantageous because the effect becomes larger. In order to avoid such disadvantages, a double channel doped structure has been proposed in which a high-concentration and low-concentration double-layer channel is formed between the source and drain, but this also reduces the junction breakdown voltage and also causes electrons to flow from the channel to the gate. The disadvantage is that the hot electron effect, which jumps in and becomes trapped in the gate insulating film and changes the threshold voltage Vth, cannot be ignored.
本発明はかゝる種々の欠点を全て除去して長チ
ヤネルFETと同様な安定な動作が期待でき、勿
論短チヤネルFETに期待される高密度集積化可
能、動作速度大などの利点を持ち、製造も容易な
短チヤネルMOS FET構造を提供しようとする
ものである。 The present invention eliminates all of these various drawbacks and can be expected to operate as stable as a long channel FET, and of course has the advantages expected of a short channel FET, such as high density integration and high operating speed. The aim is to provide a short channel MOS FET structure that is easy to manufacture.
本発明では、チヤネルドープ領域を設けるが、
これは高濃度ソース、ドレイン拡散領域とは接触
せず、その間にπ（またはP-）またはυ（または
N-）型のドリフト領域を設ける。チヤネルドー
プ領域は二層とし、基板表面側はVthを所望値に
する濃度とし、基板内部側はパンチスルーを抑え
るに充分な高濃度とする。これらによりシヨート
チヤネル効果（Vth変動）、パンチスルー、ソー
ス、ドレイン接合耐圧問題を改善し得る。また本
発明ではゲート絶縁膜をソース、ドレイン側端部
で厚く、中央部で薄くし、この薄い部分の下に上
記のチヤネルドープ領域を形成しまた厚い部分の
下を上記πまたはυ層とする。これによりホツト
エレクトロン効果を抑止でき、ｇｍが大になり、
また製造に際してアライメントをとり易くなる、
次に実施例を参照しながら本発明を詳細に説明す
る。 In the present invention, a channel doped region is provided;
It has no contact with the heavily doped source, drain diffusion regions, and has no contact between π (or P - ) or υ (or
N - ) type drift region is provided. The channel doped region has two layers, the surface side of the substrate has a concentration that makes Vth a desired value, and the inside side of the substrate has a concentration high enough to suppress punch-through. These can improve the short channel effect (Vth fluctuation), punch-through, and source/drain junction breakdown voltage problems. Further, in the present invention, the gate insulating film is made thick at the end portions on the source and drain sides and thinned at the central portion, and the above-mentioned channel doped region is formed under this thin portion, and the above-mentioned π or υ layer is formed under the thick portion. . This suppresses the hot electron effect, increases gm,
It also makes it easier to align during manufacturing.
Next, the present invention will be explained in detail with reference to Examples.
第２図に本発明の種々の実施例を示す。図示の
如く本発明ではＰ（Ｎでもよい）型シリコン基板
Subのチヤネル部中央にチヤネルドープ領域１０
を設け、該領域１０とソースＳ、ドレインＤ各領
域との間１２，１４は低濃度領域とする。ゲート
絶縁膜１６はソース、ドレイン側端部１６ａ，１
６ｂを厚く、中央部１６ｃを薄くし、この薄い部
分１６ｃをチヤネルドープ領域にまた厚い部分１
６ａ，１６ｂを低濃度領域１２，１４に対向させ
る。チヤネルドープ領域は上下二層に分れてお
り、基板表面側１０ａはVthを考慮して決定した
不純物濃度を有する層、基板内部側１０ｂはパン
チスルー耐圧を考慮して決定した高濃度層であ
る。第２図ａはデプレーシヨン型であり、層１
２，１４，１０ａともソース、ドレイン領域と同
じＮ型である。第２図ｂ，ｃ，ｄはエンハンスメ
ント型であり、層１２，１４はｂ，ｄではP-型、
ｃではN-型、層１０ａはｂではＮ型、ｃ，ｄで
はＰ型である。基板内部側の層１０ｂはａ〜ｄと
もP+型であり基板Subと同じ導電型である。 FIG. 2 shows various embodiments of the invention. As shown in the figure, in the present invention, a P (or N) type silicon substrate
Channel doped region 10 in the center of the channel part of Sub
The regions 12 and 14 between the region 10 and the source S and drain D regions are low concentration regions. The gate insulating film 16 has source and drain side ends 16a, 1
6b is made thicker and the central part 16c is made thinner, and this thinner part 16c is made thicker in the channel doped region as well as thicker part 1.
6a and 16b are opposed to the low concentration regions 12 and 14. The channel doped region is divided into upper and lower layers, the substrate surface side 10a is a layer having an impurity concentration determined by considering Vth, and the substrate inner side 10b is a high concentration layer determined by considering punch-through breakdown voltage. . Figure 2a shows the depletion type, with layer 1
2, 14, and 10a are all N type like the source and drain regions. Figure 2 b, c and d are of the enhancement type, and the layers 12 and 14 are of the P - type in b and d;
layer 10a is N - type in layer b, and P-type in layer c and d. The layers 10b on the inside of the substrate are all P + type, and have the same conductivity type as the substrate Sub.
このような構造にすると次のような種々の利点
が得られる。即ち、ゲート電極Ｇおよびその下部
のゲート酸化膜１６とソース、ドレイン領域Ｓ，
Ｄの一部は不純物拡散またはイオン注入の関係で
一部が重なつているから、スケーリング則により
ゲート絶縁膜厚を減少して行くとこの重なり部分
に強い電界が生じ、絶縁破壊または前述のホツト
エレクトロン効果などを生じる。これに対しゲー
ト絶縁膜のソース、ドレイン側端部１６ａ，１６
ｂを厚くするとゲートとソース、ドレイン間耐圧
は向上し、またホツトエレクトロンが生じにくゝ
なる。また厚いゲート絶縁膜１６ａ，１６ｂの下
部基板をP-またはN-の低濃度層にすると電界集
中が緩和され、ソース、ドレインからの空乏層が
充分拡がるのでドレイン側でのインパクトアイオ
ニゼーシヨンによるサブスレシヨルド電流を軽減
することが可能である。またチヤネル部は相対的
に濃度が高い部分１０ａにより確実に確保される
ので、ソース、ドレイン空乏層の延びによる実効
チヤネル長の減少、所謂短チヤネル効果を抑制す
ることができる。またゲート絶縁膜の端部１６
ａ，１６ｂを厚くすると該端部での耐圧問題に悩
まされることなく中央部のゲート絶縁膜を薄くす
ることができるので、ｇｍが向上する。チヤネル
ドープ領域１０のP+型深部１０ｂはドレイン空
乏層がソース領域へ延びてパンチスルーを生じる
のを確実に阻止する。なおパンチスルーは基板表
面ではなく基板深部で生じるから、パンチスルー
を防止する高濃度層１０ｂは基板深部に形成する
のみで充分である。若しこれを基板表面部まで達
すようにする、つまり部分１０ａ，１０ｂを同じ
高濃度層にするとチヤネル形成に支障があり、ま
たしきい値電圧Vthを変化させる欠点がある。基
板表面側の部分１０ａはその不純物濃度を所望
Vthに応じて決定し、このように機能を分割する
ことで本発明では両側部分１２，１４の選択とも
相俟つて第２図ａのようなデプレーシヨン型もま
た同図ｂ〜ｄのようなエンハンスメント型も実現
可能である。次に本発明FETの製造方法を説明
する。 Such a structure provides the following various advantages. That is, the gate electrode G and the gate oxide film 16 under it, the source and drain regions S,
A portion of D overlaps due to impurity diffusion or ion implantation, so as the gate insulating film thickness is reduced according to the scaling law, a strong electric field is generated in this overlapped area, resulting in dielectric breakdown or the aforementioned hot spots. Generates electron effects, etc. On the other hand, the source and drain side ends 16a and 16 of the gate insulating film
When b becomes thicker, the breakdown voltage between the gate, source, and drain improves, and hot electrons are less likely to be generated. Furthermore, if the lower substrate of the thick gate insulating films 16a and 16b is made of a low concentration layer of P - or N - , the electric field concentration will be alleviated, and the depletion layer from the source and drain will expand sufficiently, resulting in impact ionization on the drain side. It is possible to reduce subthreshold current. Furthermore, since the channel portion is reliably secured by the relatively high concentration portion 10a, it is possible to suppress a reduction in the effective channel length due to the extension of the source and drain depletion layers, ie, the so-called short channel effect. Also, the end portion 16 of the gate insulating film
By increasing the thickness of a and 16b, the gate insulating film in the central portion can be made thinner without suffering from the breakdown voltage problem at the ends, thereby improving gm. The P + type deep portion 10b of the channel doped region 10 reliably prevents the drain depletion layer from extending into the source region and causing punch-through. Note that since punch-through occurs not on the surface of the substrate but in the deep part of the substrate, it is sufficient to form the high concentration layer 10b that prevents punch-through in the deep part of the substrate. If this layer were to reach the surface of the substrate, that is, if the portions 10a and 10b were made of the same high concentration layer, channel formation would be hindered, and the threshold voltage Vth would change. The portion 10a on the substrate surface side has a desired impurity concentration.
By determining the function according to Vth and dividing the function in this way, in conjunction with the selection of both side portions 12 and 14, the depression type shown in FIG. type is also possible. Next, a method for manufacturing the FET of the present invention will be explained.
第３図ａに示すように先ずＰ型シリコン基板
Subにフイールド酸化膜１８を形成し、次いで素
子形成領域に浅くＮ型不純物をイオン注入して
P-型またはN-型層２０を作り、かつ基板表面に
は酸化膜２２を形成する。次にホトプロセスより
酸化膜２２の中央のゲート形成部分に穴をあけ
る。第３図ｂの２４はこのホトプロセスで用いた
レジスト膜、２６は上記の穴である。穴２６は酸
化膜２２を完全に貫通するものではなく、下部々
分を残した凹部であつてもよい。かゝる状態で基
板と同じ導電型の不純物を高濃度にイオン注入
し、P+層１０ｂを作る。このP+層１０ｂは層２
０より深く形成する。次いで同じまたは反対導電
型の不純物を浅くかつ低濃度にイオン注入し、第
３図ｃに示すように層１０ｂ上の基板部分をＰま
たはＮ型にする。次いで熱酸化してゲート絶縁膜
の薄い部分１６ｃを作る。先に形成した酸化膜２
２はゲート絶縁膜の厚い部分１６ａ，１６ｂにな
るものであるが上記熱酸化等に際し付随的に酸化
が再び行なわれて厚くなるので、同図ａの段階で
付ける酸化膜２２の厚みはこれを考慮して最終段
階で所望厚みになるように選定する。然るのち全
面に多結晶ポリシリコン層１７を被着する。次い
で該ポリシリコン層１７をゲート絶縁膜１６の薄
い部分１６ｃ上から厚い部分２２上の一部に亘る
大きさに残るよう選択的に除去したのち該残され
たポリシリコン層をマスクとして厚い酸化膜２２
部分に第３図ｅのようにソース、ドレイン窓をあ
ける。そして基板とは反対のＮ型不純物を高濃度
に拡散して前記ポリシリコン層１７に導電性を付
与すると共にソース、ドレイン領域Ｓ，Ｄを作
る。このソース、ドレイン領域の深さxjは層２０
をやゝ突き出る程度とし、チヤネルドープ領域１
０よりは浅くし、領域１０がパンチスルーに対す
る有効な障壁となるようにする。以後は周知の手
段によつてソースおよびドレイン各電極（図示せ
ず）を取付ければ所望のFETが出来上る。 As shown in Figure 3a, first, a P-type silicon substrate is
A field oxide film 18 is formed on the Sub, and then N-type impurity ions are implanted shallowly into the element formation region.
A P - type or N - type layer 20 is formed, and an oxide film 22 is formed on the substrate surface. Next, a hole is made in the central gate forming portion of the oxide film 22 by photoprocessing. In FIG. 3b, 24 is the resist film used in this photoprocess, and 26 is the hole described above. The hole 26 does not need to completely penetrate the oxide film 22, but may be a recess with a lower portion left. In such a state, impurities of the same conductivity type as the substrate are ion-implanted at a high concentration to form the P + layer 10b. This P + layer 10b is layer 2
Form deeper than 0. Next, impurities of the same or opposite conductivity type are ion-implanted shallowly and at a low concentration to make the substrate portion on layer 10b P or N type, as shown in FIG. 3c. Next, thermal oxidation is performed to form a thin portion 16c of the gate insulating film. Oxide film 2 formed earlier
2 are the thick parts 16a and 16b of the gate insulating film, but during the above-mentioned thermal oxidation, etc., oxidation is performed again and the thickness becomes thicker, so the thickness of the oxide film 22 applied at the stage a in the figure should be Take this into account and select the desired thickness at the final stage. Thereafter, a polycrystalline silicon layer 17 is deposited over the entire surface. Next, the polysilicon layer 17 is selectively removed so as to remain in a size ranging from the thin part 16c to the thick part 22 of the gate insulating film 16, and then a thick oxide film is formed using the remaining polysilicon layer as a mask. 22
Open source and drain windows in the portion as shown in Figure 3e. Then, an N-type impurity opposite to that of the substrate is diffused at a high concentration to impart conductivity to the polysilicon layer 17 and to form source and drain regions S and D. The depth x j of this source and drain region is layer 20
The channel doped region 1 is made so that it protrudes slightly.
It should be shallower than 0 so that region 10 provides an effective barrier to punch-through. Thereafter, source and drain electrodes (not shown) are attached by known means to complete the desired FET.
このような構造を有する本発明による半導体装
置はゲート絶縁膜の厚さをその中央部とソース、
ドレイン領域近傍とで異ならしめることにより、
後の工程の位置合せが容易である。即ち、単にイ
オン注入してチヤネルドープ領域１０を形成した
だけでは、イオン注入部分は目視不可能であるか
ら目印がなくなり、ソース、ドレイン窓開きの際
のマスク合せが厄介である。この点ゲート酸化膜
に図示の如く段差を付けておく本発明方法はこの
段差がマスク合せの目印となり、好都合である。
これは製造工程に起因する実効チヤネル長のバラ
つきを減少させる効果をも伴なう。 In the semiconductor device according to the present invention having such a structure, the thickness of the gate insulating film is the same as that of the center part, the source part, and the gate insulating film.
By making it different from the vicinity of the drain region,
Positioning in subsequent steps is easy. That is, if the channel doped region 10 is simply formed by ion implantation, the ion implanted portion is not visible and there is no mark, making it difficult to align the masks when opening the source and drain windows. In this respect, the method of the present invention in which a step is formed on the gate oxide film as shown in the figure is advantageous because the step serves as a mark for mask alignment.
This also has the effect of reducing variations in effective channel length due to the manufacturing process.
以上詳細に説明したように本発明によれば、パ
ンチスルー耐圧、ゲートとソース、ドレイン間耐
圧、基板とソース、ドレイン領域の耐圧が高ま
り、しきい値電圧の変動およびパンチスルーを防
止でき、ノーマリオン，ノーマリオフの両方が可
能であり、製造も容易である等種々の長所を持つ
短チヤネルMOS FETが得られる。 As described in detail above, according to the present invention, the punch-through withstand voltage, the gate-to-source, drain-to-drain withstand voltage, and the substrate-to-source, drain region withstand voltage are increased, threshold voltage fluctuations and punch-through can be prevented, and no A short channel MOS FET can be obtained that has various advantages such as being capable of both mullion and normally-off operation and being easy to manufacture.
第１図は従来のMOS FETの一例を示す断面
図、第２図ａ〜ｄは本発明の実施例を示す断面
図、第３図ａ〜ｅは本発明に係るFETの製造工
程を示す断面図である。
図面で１０はチヤネルドープ層、Ｓ，Ｄはソー
ス、ドレイン領域、１２，１４はチヤネルドープ
層とソースドレイン領域との間の基板表面部、１
６はゲート絶縁膜、１７はポリシリコンゲート電
極である。
FIG. 1 is a sectional view showing an example of a conventional MOS FET, FIGS. 2 a to d are sectional views showing an embodiment of the present invention, and FIGS. 3 a to e are sectional views showing the manufacturing process of the FET according to the present invention. It is a diagram. In the drawing, 10 is a channel doped layer, S and D are source and drain regions, 12 and 14 are substrate surface parts between the channel doped layer and the source and drain regions, and 1
6 is a gate insulating film, and 17 is a polysilicon gate electrode.
Claims (1)
れるソース領域とドレイン領域と、 表面が該半導体基板表面と同じで、かつ該ソー
ス領域と該ドレイン領域との間の中央に形成さ
れ、トランジスタのしきい値電圧を所望値にする
ように不純物が添加されてなる第１層とパンチス
ルーを防止するように不純物が添加されてなる第
２層とが順に表面から縦方向に二層隣接してなる
チヤネルドープ領域と、 表面が該半導体基板表面と同じで、かつ該チヤ
ネルドープ領域と該ソース領域との両方に隣接し
て間に形成される第１低濃度領域と、 表面が該半導体基板表面と同じで、かつ該チヤ
ネルドープ領域と該ドレイン領域との両方に隣接
して間に形成される第２低濃度領域と を有し、 該第１低濃度領域、該第２低濃度領域の各々よ
りも前記チヤネルドープ領域の第１層の方が深く
形成されてなることを特徴とする半導体装置。[Scope of Claims] 1. A source region and a drain region formed by adding conductive impurities to a semiconductor substrate, and a region whose surface is the same as the surface of the semiconductor substrate and at the center between the source region and the drain region. A first layer doped with an impurity to set the threshold voltage of the transistor to a desired value and a second layer doped with an impurity to prevent punch-through are formed in order from the surface in the vertical direction. a first low concentration region having a surface that is the same as the surface of the semiconductor substrate and adjacent to and between both the channel doped region and the source region; a second low concentration region having a surface the same as the surface of the semiconductor substrate and adjacent to and between both the channel doped region and the drain region, the first low concentration region, the first low concentration region; 2. A semiconductor device, wherein the first layer of the channel doped region is formed deeper than each of the two low concentration regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3742679A JPS55130171A (en) | 1979-03-29 | 1979-03-29 | Mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3742679A JPS55130171A (en) | 1979-03-29 | 1979-03-29 | Mos field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55130171A JPS55130171A (en) | 1980-10-08 |
| JPH0465549B2 true JPH0465549B2 (en) | 1992-10-20 |
Family
ID=12497181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3742679A Granted JPS55130171A (en) | 1979-03-29 | 1979-03-29 | Mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55130171A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58139471A (en) * | 1982-02-15 | 1983-08-18 | Fujitsu Ltd | Mis field effect transistor |
| DE3739501A1 (en) * | 1986-11-26 | 1988-06-01 | Hewlett Packard Co | MOS transistor |
| US4906588A (en) * | 1988-06-23 | 1990-03-06 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
| JP2746482B2 (en) * | 1991-02-14 | 1998-05-06 | 三菱電機株式会社 | Field effect transistor and method for manufacturing the same |
| US5894158A (en) * | 1991-09-30 | 1999-04-13 | Stmicroelectronics, Inc. | Having halo regions integrated circuit device structure |
| JP2001352057A (en) | 2000-06-09 | 2001-12-21 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| US7485514B2 (en) * | 2006-01-05 | 2009-02-03 | Winslow Thomas A | Method for fabricating a MESFET |
| CN101299439B (en) | 2008-06-24 | 2011-06-22 | 广州南科集成电子有限公司 | High pressure resistant constant-current source device and production method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5144880A (en) * | 1974-10-16 | 1976-04-16 | Suwa Seikosha Kk | |
| JPS51114074A (en) * | 1975-03-31 | 1976-10-07 | Sony Corp | Insulation gate type field effect transistor |
| JPS5227280A (en) * | 1975-08-25 | 1977-03-01 | Sony Corp | Method to form pinholes |
| JPS5291381A (en) * | 1976-01-26 | 1977-08-01 | Nec Corp | Field effect type semiconductor device |
| JPS52107777A (en) * | 1976-03-08 | 1977-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Production of semiconductor unit |
| JPS5321582A (en) * | 1976-08-11 | 1978-02-28 | Mitsubishi Electric Corp | Mos type semiconductor device |
-
1979
- 1979-03-29 JP JP3742679A patent/JPS55130171A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5144880A (en) * | 1974-10-16 | 1976-04-16 | Suwa Seikosha Kk | |
| JPS51114074A (en) * | 1975-03-31 | 1976-10-07 | Sony Corp | Insulation gate type field effect transistor |
| JPS5227280A (en) * | 1975-08-25 | 1977-03-01 | Sony Corp | Method to form pinholes |
| JPS5291381A (en) * | 1976-01-26 | 1977-08-01 | Nec Corp | Field effect type semiconductor device |
| JPS52107777A (en) * | 1976-03-08 | 1977-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Production of semiconductor unit |
| JPS5321582A (en) * | 1976-08-11 | 1978-02-28 | Mitsubishi Electric Corp | Mos type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55130171A (en) | 1980-10-08 |
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