JPH0458061B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a communication control device that transfers data between a line control section provided for a line and a main storage section using direct memory access (DMA). For details, see DMA of data by line control unit.
This relates to control when a bus error occurs during transfer.

[Prior art]

The first diagram shows an example of the configuration of a conventional communication control device,
1 is a central control unit that manages the main control of the entire communication control device, 2 is a main storage unit in which programs and transmitted/received data are stored, and 3-i (i=1,...n) is a
A line control unit with a built-in DMA function, 4 a device bus consisting of an address bus and a data bus, 5 a device bus competition circuit, 6-0 and 6-i (i=1,...n)
are device bus request signals, 7-0 and 7-i (i=1,
. . . n) indicates a signal for device bus usage right assignment. In this example, the line control unit 3-i follows the CCITT Recommendation do.

In FIG. 1, when receiving data from the line, the line control unit 3-i assembles the serially received data into bytes, and each time it receives one byte from the line,
It outputs a device bus request signal 6-i to issue a device bus request to the device bus contention circuit 5. When there is a device bus request from the line controller 3-i, the device bus contention circuit 5 sends a device bus request signal 6-i to the central controller 1.
When the device bus request is made by 0 and the device bus usage right is obtained from the central control unit 1 by the device bus usage right assignment signal 7-0, the device bus is sent to the line control unit 3-i that had requested the usage of the device bus. A usage right assignment signal 7-i is returned. The line control unit 3-i, which has obtained the right to use the device bus from the device bus contention circuit 5, transfers the 1-byte data received from the line to the main storage unit 2 via DMA.
Forward. In this way, the line control unit 3-i
Each time it receives one byte from the line, it DMA transfers the received data to the main memory unit 2, and when it finishes receiving one frame from the line, it sends a frame to the line notifying that the frame has been successfully received, and the central control unit 1 The normal reception of the frame is also notified by an interrupt or the like. On the other hand, when transmitting data to the rotation, the line control unit 3-i sequentially transmits the start flag attached to the beginning of the transmission frame, the address field, and the control field, and then, triggered by an internally generated transmission data request, It acquires the right to use the device bus in the same manner as above, and receives the transmission data from the main memory section 2 in units of 1 byte by DMA transfer.
Subsequently, the line control unit 3-i converts the transmission data received from the main storage unit 2 into serial data and sends it to the line. In this way, the line control unit 3-i sends the transmission data to the line one after another, and when the last byte of the transmission data is sent, the frame check sequence unit (FCS) and the termination flag are sequentially transmitted to complete the frame transmission. .

Conventional communication control equipment has the above configuration, so there is no communication between the line control section and the main memory section.
If a bus error such as a memory read error or bus parity error occurs during DMA transfer, erroneous data may be sent to the line, or data received from the line may remain erroneous and be processed by the central control unit. It had the disadvantage of being rejected. For this reason,
It is necessary to detect the above bus error during DMA transfer and take measures against the bus error.

Conventionally, this type of bus error countermeasure has been provided with a means for detecting a bus error and a means for notifying the central control unit of the detected bus error.
There is a method in which a central control unit that receives a bus error notification controls a line control unit (for example, controls to stop operation) by command control via a device bus. However, with this method, when transmitting data to the line, if a bus error occurs while DMA transfers the last 1 byte of data of the transmission frame from the main memory to the line control unit, the central control unit that received the bus error notification Since there is a possibility that frame transmission including erroneous data may be completed in the line controller until the unit command-controls the line controller, there is a drawback that erroneous data transmission cannot be prevented. Also, when receiving data from the line,
If a bus error occurs during DMA transfer of the last byte of data of a received frame from the line control unit to the main memory unit, the central control unit that received the bus error notification will control the line control unit with commands. Since there is a possibility that the line control unit sends a frame to the line to notify of normal frame reception, there is a drawback that erroneous notification to the line cannot be prevented.

[Purpose of the invention]

An object of the present invention is to prevent the line control unit from transmitting a frame containing erroneous data or transmitting a frame notifying normal frame reception when a bus error occurs during the above-mentioned DMA transfer. The purpose is to prevent it.

[Summary of the invention]

In order to achieve the above object, the present invention provides a bus error detection means between a line control unit and a main storage unit, and when a bus error is detected, notifies the central control unit of the bus error and simultaneously controls the line during DMA transfer. It is designed to reset the section.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts. 8-1 and 8
-2 is a bus error detection circuit provided on the main storage side and line control side of the device bus 4, respectively; 9 is a bus error signal detected by the bus error detection circuits 8-1 and 8-2; and 10 is a bus error detection circuit. Bus error notification signal to notify central control unit 1, 11-i
(i=1, ..., n) is a line control reset signal for stopping the operation of the line control unit 3-i and disconnecting communication with the line, 12-1 and 12-2 are OR gates, 13-i (i=1, . . . , n) indicates an AND gate. In FIG. 2, line control unit 3-i
The operation when a bus error does not occur during DMA transfer between the main storage unit 2 and the main storage unit 2 is the same as that shown in FIG. 1, so a description thereof will be omitted. The case where a bus error occurs will be explained below.

When receiving data from the line, line control unit 3
The received data is DMA-transferred from -i to the main storage unit 2 in 1-byte units via the device bus 4. At this time,
The bus error detection circuit 8-2 on the line corresponding section side generates a parity bit, adds it to 1 byte of received data, and transfers it on the device bus 4.
Detects a validity error. When an error occurs during transfer of the device bus 4 and a validity error is detected in the bus error detection circuit 8-1, a bus error signal 9 is output, and at the same time, a signal is sent to the line control unit 3-i. , the line control unit reset signal 11-i, which is an AND logic of the bus error signal 9 and the device bus usage right assignment signal 7-i, is applied to the line control unit 3 during DMA transfer.
-i only is reset. In addition, the central control unit 1
is notified of the bus error by the bus error notification signal 10. As a result, the central control unit 1
For example, the failure processing program is read out from the main storage unit 2 and the diagnostic processing is started. in this way,
If a bus error occurs during DMA transfer, it is possible to prevent erroneous transmission of a confirmation frame that is sent by the line control unit 3-i to notify the line of normal frame reception before the DMA transfer is completed.

Next, when receiving data on the line, the line control section 3-i performs DMA transfer of the transmission data from the main storage section 2 in units of bytes. At this time, the bus error detection circuit 8-1 on the main memory side detects a memory read error due to ECC, etc. for the data (transmission data) from the main memory 2, and if there is no error, a new validation bit is detected. is generated and sent to the line control unit side via the device bus 4. This device bus 4
A parity error is detected for the above transmission data in the bus error detection circuit 8-2 on the line corresponding section side. When a memory read error is detected in the bus error detection circuit 8-1 or a parity error is detected in the bus error detection circuit 8-2, DMA transfer is performed in the same manner as when receiving data from a line. Only the line control section 3-i inside is reset, and the central control section 1 is notified of the bus error. The subsequent processing by the central control unit 1 that receives the notification of the bus error is the same as in the case of data reception. In this way, if a bus error occurs during DMA transfer of transmission data from the main storage section 2 to the line control section 3-i, the line control section 3-i is reset before receiving the transmission data.
This can prevent incorrect data from being sent to the line.

〔Effect of the invention〕

As explained above, according to the present invention, when a bus error occurs during DMA transfer between the line control unit and the main storage unit, the central control unit is notified of the bus error occurrence at the same time as the bus error occurs, and the corresponding Since the line control unit is reset, when receiving data from the line, it has the advantage of preventing the erroneous transmission of a frame for confirming frame reception to the line when a bus error occurs, and when transmitting data to the line, This has the advantage of preventing erroneous data transmission when a bus error occurs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a conventional communication control device, and FIG. 2 is a diagram showing an embodiment of the present invention. 1...Central control unit, 2...Main storage unit, 3-i...
...Line control unit, 4...Device bus, 5...Device bus contention circuit, 8-1, 8-2...Bus error detection circuit, 9...Bus error signal, 10...Bus error notification signal, 11- i... Line control unit reset signal.

Claims (1)

[Scope of Claims] 1. A central control unit, a main memory unit, and a line control unit provided corresponding to a line, and data transfer between the line control unit and the main memory unit is performed by direct memory access ( In a communication control device using DMA), there is a
A first means for detecting a bus error during DMA transfer is provided, and a second means is provided for notifying the central control section of the occurrence of a bus error and resetting the corresponding line control section when a bus error is detected by the means. A communication control device characterized by: 2. The first means has a function of detecting a memory read error when reading transmission data from the main storage unit to the line, and the second means has a function of detecting an error in the central control unit when the memory read error is detected. 2. The communication control device according to claim 1, wherein the communication control device notifies the user and resets the corresponding line control section.