JPH0448652A - Semiconductor device of silicon planar type - Google Patents

Abstract

PURPOSE:To acquire a silicon planar type semiconductor device having a structure whose depletion layer easily grows uniformly and resists external effect by forming the device of a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, an insulating film, a conductive ring, a first main electrode and a second main electrode. CONSTITUTION:When a reverse voltage is applied to a main junction 4 between main electrodes 8, 9, a depletion layer grows from the main junction 4 and a guard ring 5 and a channel stopper 6 work to hold a reverse voltage of a main junction flat part 4a. In the process, a conductive ring 12 positions on an n<->-silicon layer 2 as a first semiconductor layer through an insulating film 7. Furthermore, since each conductive ring 12 is spaced regularly to a p-region 3, it does not have a detrimental effect on operation of the guard ring 5 and a channel stopper 6. When irregular electric charge exists inside an insulating film 7 below an insulating film-silicon interface and the conductive ring 12, electric charge easily moves inside the conductive ring 12 to cancel effect of irregular electric potential as electric potential of each conductive ring 12 is fixed; therefore the conductive ring 12 resists irregular charge. A depletion layer easily grows uniformly in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a silicon planar semiconductor device, and particularly to a structure around a main junction for maintaining its breakdown voltage ability.

[Conventional technology]

FIG. 2 shows a cross-sectional view of the vicinity of the main junction, which has been used to maintain the withstand voltage of the main junction in a conventional planar semiconductor device.

In this figure, 1 is an n+ substrate, on which an n- silicon layer 2 is formed. By diffusing p-type impurities into the surface of this n9932 layer 2 by planar technology, a p region 3 is formed, and the boundary between the p region 3 and the n-silicon layer 2 becomes a main junction 4. A required number of guard rings 5 are formed on the outer periphery by diffusing p-type impurities. Furthermore, a channel stopper 6 is formed by diffusing n-type impurities into the outer periphery of the guard ring 5. One wafer is divided into each element outside this channel stopper 6. p region 3° guard ring 5. An insulating film 7 is formed on the surface of the n9932 layer 2 between each channel stopper 6 . Further, a main electrode 8 is formed on the surface of the p region 3, a main electrode 9 is formed on the back surface of the n+ substrate 1, and a guard ring electrode 10 is formed on the surface of each guard ring 5.
A channel stopper electrode 11 is formed so as to extend from the surface of the channel collar 6 to the insulator 7.

In such a configuration, between the main electrode 8 and the main electrode 9,
The main electrode 8 applies a negative voltage and the main electrode 9 applies a positive voltage. Since this voltage is a reverse voltage with respect to the main junction 4, as the voltage becomes stronger, a depletion layer extends from the main junction 4 to the n-silicon layer 2 with a lower concentration. At this time, the electric field at the main junction corner portion 4b is generally stronger than the electric field at the main junction flat portion 4a. Therefore, when obtaining a high reverse voltage (100 to 200 V or more), without the guard ring 5, breakdown will occur at the main junction corner 4b before the reverse voltage determined at the main junction flat part 4a.
It happens in Therefore, the main joint 4 is the main joint corner portion 4b.
the first guard ring 5a so that the depletion layer reaches the first guard ring 5a before breaking down.
If a is attached, the depletion layer will now extend from the first guard ring 5a, and the electric field at the main junction corner 4b will be relaxed. Next, we must consider the electric field at the corner of this first guard ring 5a, but by attaching a plurality of guard rings 5, the electric field at the corner is relaxed, and the main junction 4 is connected to the flat part of the main junction. 4a shows the reverse voltage determined in FIG.

Also, from the outermost circumferential guard ring 5b to the channel stopper 6
The design is such that the depletion layer does not extend until then, but if the depletion layer extends too much for some reason, the depletion layer will reach the edge of the device without the channel stopper 6, causing a drop in breakdown voltage. Since the channel stopper 6 is generally at the same potential as the n+ substrate 1 on the back side, it suppresses the extension of the depletion layer and prevents the depletion layer from forming at the edge 1 of the device.
I'm trying to keep it from growing.

Guard ring electrode 10. The channel stopper electrode 11 is
It is attached to help each work.

With such a structure, the withstand voltage holding ability of planar bonding has been significantly improved.

However, guard ring 5. Even if the channel stopper 6 is formed, the silicon-insulating film interface and the insulating film 7
There is generally a positive charge inside. If this charge is non-uniform, this charge will cause non-uniform elongation of the depletion layer (in general, the charge makes the depletion layer easier to elongate)
. Therefore, since the extended portion of the depletion layer is closest to the channel stopper 6, the electric field is stronger than in other locations, making it easier to blow up and down.

Furthermore, if electric charges, moisture, etc. adhere from the outside to a part of the periphery of the main junction on the surface, non-uniformity will occur in the elongation of the depletion layer underneath. Further, if the depletion layer adheres to the entire surface (particularly moisture is considered), the depletion layer tends to extend over the entire surface, making it easier to break down the corner portion of the outermost circumferential guard ring 5b. Alternatively, if the depletion layer is severely elongated, the depletion layer may reach the channel stopper 6, and the electric field at this portion may become stronger, leading to breakdown.

[Problem to be solved by the invention]

As described above, in the conventional planar junction, the depletion layer from the main junction around the junction becomes uneven or extends too much, which causes problems such as a decrease in breakdown voltage.

The invention of Party B was made in order to solve the above-mentioned problems, and its purpose is to provide a silicon planar semiconductor device having a structure in which the depletion layer can easily grow uniformly and is less susceptible to external influences. shall be.

[Means to solve the problem]

The silicon planar semiconductor device according to the present invention has a first
a first semiconductor layer of a conductivity type; a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer; and a second semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer outside the second semiconductor layer. a conductive ring formed in the insulating film so as to surround the second semiconductor layer, a first main electrode formed on the surface of the second semiconductor layer, and a first semiconductor layer. A second main electrode is formed on the back surface.

[Effect]

In this invention, charge movement occurs within the conductive ring so as to eliminate non-uniformity of charge at the insulating film-silicon interface and within the insulating film. Further, this conductive ring functions as a shield against electric charges and the like that adhere to the external surface.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of the vicinity of a main junction of an embodiment of a silicon planar semiconductor device of the present invention. In this diagram,
The same reference numerals as in FIG. 2 indicate the same parts, and 12 is a conductive ring.

That is, in the silicon planar semiconductor device of the present invention, as shown in FIG. 1, in addition to the conventional structure, a conductive ring 12 is provided as a second semiconductor layer within the insulating film 7 from the main junction 4 to the periphery of the element. In each insulating film 7, conductive leans 12 are formed at equal intervals from the p region 3.

Next, the operation of the planar type joining according to the present invention will be explained.

In such a configuration, when a reverse voltage is applied to the main junction 4 between the main electrodes 8 and 9, as described above, the main junction 4
The guard ring 5° channel stopper 6 acts so that the depletion layer is depressed and the reverse voltage of the main junction flat portion 4a is maintained. At this time, the conductive rings 12 are located on the n-silicon layer 2 as the first semiconductor layer with the m-layer 7 in between, and each conductive ring 12 is equally spaced with respect to the p region 3. Guard ring 5. It does not adversely affect the function of the channel stopper 6.

Next, consider the case where non-uniform charges exist at the insulating film-silicon interface or within the insulating film 7 below the conductive ring 12.

In this case, since each conductive ring 12 has a constant potential, charge movement occurs within the conductive ring 12 to cancel out the non-uniform potential, making it less susceptible to the effects of non-uniform charge.
This makes it easier for the depletion layer to grow uniformly.

Furthermore, if charges or moisture adhere to the inside of the insulating film 7 above the conductive ring 12 or to the external surface, each conductive ring 12 exhibits a shielding effect, making it less susceptible to external influences. Furthermore, since the conductive rings 12 are arranged at regular intervals with respect to the p-region 3, the depletion layer can easily grow uniformly even without uneven charges, externally attached charges, or moisture.

In addition, in the embodiment shown in FIG. 1, the guard ring 5. Channel stopper 6 and guard ring electrode 10. Although an example is shown in which the channel stopper electrode 11 is provided, the conductive ring 12 of the present invention functions to maintain the withstand voltage of the main junction 4 even without these.

Further, in the above embodiment, a push type junction of the n-silicon layer 2 was described, but it goes without saying that the present invention can also be applied to a planar type junction of the p-silicon layer.

〔Effect of the invention〕

As explained above, the present invention includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer, and a second semiconductor layer of the second conductivity type. an insulating film formed on the surface of the first semiconductor layer on the outside; a conductive ring formed in the insulating film so as to surround the second semiconductor layer; and a first conductive ring formed on the surface of the second semiconductor layer. , and a second main electrode formed on the back surface of the first semiconductor layer. Therefore, when a reverse voltage is applied to the main junction, the depletion layer can easily grow uniformly, and it can be protected from external influences. This has the effect of making it possible to obtain a planar type joint that is less susceptible to susceptibility.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the vicinity of the main junction of an embodiment of the silicon planar semiconductor device of the present invention, and FIG. 2 is a cross-sectional view of the vicinity of the main junction of a conventional planar semiconductor device. In the figure, 1 is an n+ substrate, 2 is an n- silicon layer, 3 is a p region, 4 is a main junction, 5 is a guard ring, 6 is a channel stopper, 7 is an insulating film, 8 and 9 are main electrodes, and 10 is a guard A ring electrode, 11 is a channel stopper electrode, and 12 is a conductive ring. Note that the same reference numerals in each figure refer to the same or corresponding parts. Agent Masuo Oiwa (around 2 others) Voluntary to write procedural amendments) July 9, 1991 3, Relationship to the case of the person making the amendments Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name Title (601) Mitsubishi Electric Corporation Representative Moriya Shiki 5, Detailed explanation of the invention column 6 of the specification subject to amendment, page 9 between lines 4 and 5 of the specification of the contents of the amendment as follows: Insert a descriptive text. [Furthermore, in the embodiment shown in FIG.
2 is the insulation W787 between the main junction 4 and the channel stopper 6
Although an example has been shown in which the conductive rings 12 are present within the insulating film 7, the withstand voltage of the main junction 4 is maintained regardless of the number and position of the conductive rings 12. However, in order to more fully demonstrate the ability of the main junction 4 to maintain the withstand voltage, it is desirable to form all of the main junctions within the insulating film 7. J or above

Claims (1)

[Claims] a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer; and the first semiconductor layer outside the second semiconductor layer. an insulating film formed on the surface, a conductive ring formed in the insulating film so as to surround the second semiconductor layer, and a first main electrode formed on the surface of the second semiconductor layer; A silicon planar semiconductor device comprising a second main electrode formed on the back surface of the first semiconductor layer.