JPH0440537A - Data management system - Google Patents

Abstract

PURPOSE:To simplify the data management by detecting whether an address to a common memory from an information processor is a processing address set in advance or not, switching successively the head address of each store area of the common memory, whenever a prescribed address is detected and adding it to the address from the information processor, and reading out successively data of the common memory by its result. CONSTITUTION:When a CPU 1 reads out and processes successively receiving data stored in common memories 3 - 5 in order of its address, whether a read-in address from the CPU 1 coincides with a specific address or not is detected by an address comparing circuit 22, and when the coincidence is detected by the address comparing circuit 22, the head address of each of the common memories 3 - 5 from a head address holding circuit 24 is switched successively and added to the read-in address from the CPU 1, and the receiving data stored in the common memories 3 - 5 are read in successively by its addition result. In such a way, the data management can be simplified.

Description

TECHNICAL FIELD The present invention relates to a data management system, and more particularly to a data management system for received data written to a common memory from an external device.

BACKGROUND ART Conventionally, in this type of data management system, as shown in FIG. The received data written in the common memories 3 to 5 through the data bus 121 is sequentially read and processed through the data bus 121.

In other words, the CPU allocates areas for storing received data on the common memories 3 to 5 divided by "one data capacity (block data)" x [number of retained data (number of blocks)] from the first address of the received data storage, and stores the next data. In addition to managing the starting address of the area where the data is stored, the data received from the external device 6 stored in the common memories 3 to 5 are sequentially read and processed.

In such a conventional data management system, areas for storing received data are secured on the common memory 3 to 5 in the amount equal to "capacity of one data" x "number of data stored" from the first address of storing the received data. When accessing an area where received data is stored, it must always manage the address of the currently accessed data, that is, whether the currently accessed area is in common memory 3 to 5 with the The drawback is that data management becomes complicated.

Aspects of the Invention The present invention has been made to eliminate the drawbacks of the conventional methods as described in item 1 above, and its 1 purpose is to provide a data management system that can simplify data management.

Structure of the Invention A data management system according to the present invention includes a common memory provided in common to external devices and consisting of a plurality of storage areas each storing received data from the external device, and an information processing device stored in the common memory. When reading and processing the received data sequentially in address order, a detection means detects whether the address from the information processing device to the common memory is a preset predetermined address; addition means for sequentially switching the start address of each of the plurality of storage areas and adding it to the address from the information processing device each time the information processing device accesses the common memory; The received data stored in the common memory is sequentially read out based on the addition result.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, when a CPU 1 sequentially reads received data from an external device 6 stored in common memories 3 to 5, it sends a read address to a switching circuit 2 via an address bus 100.

The switching circuit 2 generates addresses for the common memories 3 to 5 based on the addresses from the CPU 1, and sends them to the common memories 3 to 5 via the address bus 102.

That is, the switching circuit 2 determines which of the common memories 3-5 is to be accessed, generates an address based on the result, and sends the address to the common memories 3-5.

The common memories 3 to 5 store received data from the external device 6 inputted via the data bus III, and the received data is read out according to the address from the switching circuit 2 and sent to the CPU 1 via the data bus 101. It is sent to 141.

Here, the common memories 3 to 5 have the same capacity, r100OJ to rlFr"FJ, r2000, respectively.
J~r2PPFJ, r3000J~r3FFP
The address of J is EjJj.

FIG. 2 is a block diagram showing the configuration of the switching circuit 2 of FIG. 1. In the figure, address latch circuit 2 of switching circuit 2
1 holds the read address from the CPUI and outputs the read address to the address comparison circuit 22.

The address comparison circuit 22 compares the read address held in the address latch circuit 2 with a preset specific address (in this embodiment, rOFPPJ indicating the final address of the capacity of the common memories 3 to 5), and latches the address. If the read address from the circuit 21 matches the specific address, that fact is notified to the head address addition circuit 23, and if they do not match, the read address is sent to the address adder 25.

When the start address addition circuit 23 receives the notification from the address comparison circuit 22, it adds the start address (rlooOJ) of each of the common memories 3 to 5 held in the start address holding circuit 24.
, r2000J, r3000j) at the next timing is output to the head address holding circuit 24.

The start address holding circuit 24 stores the start addresses (N, G(IOJ, r200(IJ) of each of the common memories 3 to 5).
.

r3000J) is held and the start address addition circuit 2
The start address to be output to the address adder 25 is switched at the next timing according to the signal from the address adder 3.

The address adder 25 adds the read address from the address comparison circuit 22 and the start address from the start address holding circuit 24, and outputs the addition result to the common memories 3 to 5 via the address bus 102.

FIG. 3 is a diagram showing the format of the received data stored in the common memories 3 to 5 of FIG. 1. In the figure, the received data consists of a data presence flag 31 indicating that data is stored, received data 32, and end notification data 33 indicating the end of the stored data.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

When the CPUI reads received data stored in the common memories 3 to 5 from the external device 6, a read address is output from the CPUI to the switching circuit 2.

In the switching circuit 2, an address read from the CPUI is held in an address latch circuit 21, and an address comparison circuit 22 detects whether it matches a specific address.

At this time, if the address comparison circuit 22 does not detect a match with the specific address, the address adder 25
] The start address from the start address holding circuit 24 is added to the read address from the start address holding circuit 24 and output to the common memories 3 to 5 via the address bus 102.

For example, if the read address from the CPUI is r0003J, which indicates the third byte, the first address holding circuit 2
If the starting address from 4 is r 2000J,
Address adder 25 reads address r from CPUI.
0003J and the start address r 2000J from the start address holding circuit 24 are added, and the address r 200SJ of the common memory 4 is output via the address bus 102.

As a result, the received data stored at address r2003J of the common memory 4 is transferred to the CPU via the data bus 101.
sent to.

Furthermore, the received data is sequentially read from the common memory 4 in address order according to the read address from the CPUI, and when the read address from the CPUI reaches roFPFJ, a match is detected by the address comparison circuit 22, and this fact is sent to the start address addition circuit 23. will be notified.

The start address addition circuit 23 outputs a signal to the start address holding circuit 24 based on this notification, and changes the start address output from the start address holding circuit 24 to the address adder 25 from r 2000J to r 3000J at the next timing.
Switch to.

At the next timing, the read address from CPU1 is O.
By I・“1 is specified r When it becomes 0OOOJ, the address adder 25 reads the read address r 0 from the CPUI.
OOOJ and the start address “3000J” from the start address holding circuit 24 are added, and the address r 3000J of the common memory 5 is outputted via the address bus 102.

As a result, the received data stored at address r3000J of the common memory 5 is transferred to the CPU via the data bus lOI.
sent to.

Therefore, the received data to be read by the CPUI is stored in the common memory 3~
Address r O that indicates how many bytes of the common memory 3 to 5, that is, the capacity of the common memory 3 to 5, without managing in which memory the data is stored in the common memory 3 to 5.
Since it is only necessary to access the received data using OOOJ~'F Pj, it becomes easy to manage the received data stored in the common memories 3 to 5.

In this way, when the CPUI sequentially reads and processes the received data stored in the common memories 3 to 5 in address order,
The address comparison circuit 22 detects whether or not the address read from the CPUI matches a specific address, and each time the address comparison circuit 22 detects a match, the start address holding circuit 24 transfers the data to the beginning of each of the common memories 3 to 5. By sequentially switching the address and adding it to the read address from the CPUI, and using the addition result to sequentially read the received data stored in the common memories 3 to 5, the CPU
I does not manage which memory among the common memories 3 to 5 the received data is stored in, and the received data is stored in the common memories 3 to 5.
Address r OOOOJ~rOPFl” indicating the capacity of 5
Since the received data can be managed with J, data management can be done in-house.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when an information processing device sequentially reads and processes received data stored in a common memory in address order, an address from the information processing device to the common memory is set in advance. Detect whether it is a specified address or not,
Each time a predetermined address is detected, the start address of each storage area of the common memory is sequentially switched and added to the address from the information processing device, and the received data stored in the common memory is sequentially read out based on the addition result. This has the effect of simplifying data management.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the switching circuit in FIG. 1, and FIG.
The figure does not show the format of the received data stored in the common memory of FIG. 1, and FIG. 4 is a block diagram showing a conventional example. Explanation of symbols of main parts] 1 1 ... CPU 2 ... Switching circuits 3 to 5 ... Common memory 22 ... Address comparison circuit 24 ... ...Start address holding circuit 25...
・Address adder

Claims (1)

[Claims] (1) A common memory provided in common to external devices and consisting of a plurality of storage areas each storing received data from the external device, and an information processing device sequentially storing the received data stored in the common memory in address order. a detection means for detecting whether or not an address from the information processing device to the common memory is a predetermined address when reading and processing; addition means for sequentially switching the start address of each storage area and adding it to the address from the information processing device; and when the information processing device accesses the common memory, the addition result of the addition means is added to the common memory. A data management system characterized in that the stored received data is sequentially read out.