JPH04373160A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit having a clock distribution circuit wherein skew management of clock signal between a plurality of clock signal processing circuit parts in an inner circuit part is easy, the inner circuit can be driven even when the circuit scale is large, and high frequency clock signal can be transmitted to the inner circuit parts. CONSTITUTION:A first stage driver circuit 3, second stage driver circuits 7, 8 and third stage driver circuits 13-16 are connected in a tree structure. The lengths of a plurality of wirings connecting the first stage and the second stage driver circuits are made equal. The lengths of wirings connecting the second stage and the third stage driver circuits are made equal. Output terminals of four driver circuits 13-16 of the third stage are mutually connected, and one output is led out. Hence a clock distribution circuit can be constituted which can manage easily clock skew, drive a large scale circuit, and transmit high frequency clock.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit for semiconductor integrated circuits.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional clock distribution circuit mounted on an LSI. As shown in the figure,
A clock signal input terminal 1 is connected to an input terminal of an input buffer circuit 2. Further, the output terminal of the input buffer circuit 2 is connected to one end of the wiring 4, and the other end of the wiring 4 is connected to the input terminal of the driver circuit 3. Further, the output terminal of the driver circuit 3 is connected to one end of a wiring 17, and the other end of the wiring 17 is connected to an internal circuit (not shown) corresponding to an internal circuit section of the LSI, which will be described later.

FIG. 4 shows the conventional clock distribution circuit of FIG.
FIG. 3 is a diagram showing a layout when mounted on an SI chip. As shown in the figure, in the LSI chip 23, P
The clock signal input PAD 18 corresponding to the clock signal input terminal 1 in FIG. There is. Further, the output part of the input buffer circuit section 2a is connected to the input of the driver circuit section 3a corresponding to the driver circuit 3 in the I/O buffer area 20 via the aluminum wiring 4a corresponding to the wiring 4 in FIG. 3 in the wiring area 21. connected to the section. Furthermore, the output section of the driver circuit section 3a is connected to the internal circuit section 22 via an aluminum wiring 170 corresponding to the wiring 17 in FIG. 3 within the wiring region 21.

Next, the operations shown in FIGS. 3 and 4 will be explained. First, in FIG. 3, a clock signal applied from a clock input terminal 1 is output from an input buffer circuit 2 and input to a driver circuit 3 via a wiring 4. The clock input signal driven by the driver circuit 3 is sent from its output to an internal circuit (not shown) via a wiring 17 (internal circuit section 2 in FIG.
2) is given.

Similarly, in FIG. 4, the clock signal applied to the clock signal input PAD 18 is given to the input of the input buffer circuit section 2a, and the output of the input buffer circuit section 2a is sent to the driver circuit section 3a via the aluminum wiring 4a. is input. The clock signal driven by the driver circuit section 3a is supplied to the internal circuit section 22 via the aluminum wiring 170. Furthermore, the aluminum wiring 170 is connected to a plurality of circuit sections within the internal circuit section 22 that process clock signals.

[0006]

Since the conventional clock distribution circuit was constructed as described above, it had the following problems. ■． In the layout on the LSI shown in FIG. 4, aluminum wiring 1 connecting the driver circuit section 3a and the internal circuit section 22
A plurality of circuits that process clock signals depending on the wiring lengths of a plurality of wirings that are further connected to 70 and connect the driver circuit section 3a and a plurality of circuit sections that process clock signals in the internal circuit section 22, respectively. The clock skew differs between sections (for example, the skew of the clock signal differs between a circuit section far from and a circuit section close to the section to which the driver circuit section 3a of the internal circuit section 22 is connected). Have difficulty. ■． As shown in FIG. 3, the number of stages of the driver circuit is one stage, which is only the driver circuit 3. Therefore, when the circuit scale of the internal circuit section 22 becomes large, the driving ability of the driver circuit 3 will not be insufficient. be. ■． Due to the lack of driving capability of the driver circuit 3, the waveform of the signal applied to the input of the driver circuit 3 is rounded at the output of the driver circuit 3, making it impossible for the driver circuit 3 to drive a high-frequency clock signal.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit having a clock distribution circuit as described below. ■． It is easy to manage clock signal skew between a plurality of circuit units that process clock signal input within the internal circuit unit. ■． Even when the circuit scale of the internal circuit section becomes large, it can be driven. ■． A high frequency clock signal can be transmitted to the internal circuit section.

[0008]

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention has a plurality of driver circuits configured in a multi-stage tree structure, and has the same wiring length between each driver circuit between adjacent stages. , the output terminals of the final stage driver circuits are connected to each other to derive one output.

[0009]

[Operation] In the semiconductor integrated circuit according to the present invention, the wiring length between adjacent stages of a plurality of driver circuits configured in a multi-stage tree structure is made the same, and the output terminals of the final stage driver circuit are Connect 1
Since two outputs are derived, the skew of the signal input to the first-stage driver circuit at the output of the final-stage driver circuit can be made the same, and the driving capability of one final output can be increased. can.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a clock distribution circuit implemented on an LSI according to an embodiment of the present invention. As shown in the figure, a clock signal input terminal 1 is connected to an input terminal of an input buffer circuit 2. Further, the output terminal of the input buffer circuit 2 is connected to one end of the wiring 4, and the other end of the wiring 4 is connected to the input terminal of the driver circuit 3. Further, the output terminal of the driver circuit 3 is connected to one end of the wiring 5 and the wiring 6, the other end of the wiring 5 is connected to the input terminal of the driver circuit 7, and the other end of the wiring 6 is connected to the input terminal of the driver circuit 8. each connected. Further, the output terminal of the driver circuit 7 is connected to one end of the wirings 9 and 10, the output terminal of the driver circuit 8 is connected to one end of the wirings 11 and 12, respectively, and the other ends of the wirings 9 to 12 are connected to the driver circuits. It is connected to input terminals 13 to 16. Furthermore, the output terminals of the driver circuits 13 to 16 are commonly connected to one end of a wiring 17, and the other end of the wiring 17 is connected to an internal circuit (not shown) corresponding to an internal circuit section of the LSI, which will be described later. It is connected.

FIG. 2 is a diagram showing a layout when the clock distribution circuit of FIG. 1 is mounted on an LSI chip. As shown in the figure, in the LSI chip 23, the PAD
The clock signal input PAD 18 corresponding to the clock signal input terminal 1 in FIG. 1 in the area 19 is connected to the I/O buffer area 20.
Input buffer circuit section 2a corresponding to input buffer 2 in
electrically connected to the input section of the Further, the output part of the input buffer circuit section 2a is connected to the wiring 4 in FIG. 1 within the wiring area 21.
The driver circuit portion 3 corresponding to the first stage driver circuit 3 located at the chip corner portion of the LSI chip 23 in the I/O buffer area 20 is connected via the aluminum wiring 4a corresponding to the
It is connected to the input section of a.

Further, the output section of the driver circuit section 3a is connected to the driver circuit section 3a in the I/O buffer area 20 via the aluminum wirings 5a and 6a corresponding to the wirings 5 and 6 in FIG. 1 in the wiring area 21, respectively. Driver circuit sections 7a and 8a corresponding to second-stage driver circuits 7 and 8 respectively located at chip corner sections adjacent to and equidistant from the chip corner section of the LSI 21 located therein;
is connected to the input section of the

Furthermore, the output section of the driver circuit section 7a is connected to the position of the driver circuit section 7a within the I/O buffer area 20 via aluminum wirings 9a and 10b corresponding to the wirings 9 and 10 in FIG. 1 within the wiring area 21. driver circuits corresponding to the third-stage driver circuits 13 and 14 located at the left and right center portions and the top and bottom center portions of the LSI chip 23 adjacent to and equidistant from the chip corner portion of the LSI chip 23; It is connected to the input sections of sections 13a and 14a. Similarly, the output section of the driver circuit section 8a is connected to the I/O buffer area 20 via aluminum wirings 11a and 11b corresponding to the wirings 11 and 12 in FIG. 1 in the wiring area 21.
A third-stage driver circuit is located at the left and right center portions and the top and bottom center portions of the LSI chip 23, which are adjacent to the chip corner portion of the LSI chip 23 where the driver circuit section 8a is located, and which are equidistant from the chip corner portion. 15,
It is connected to the input section of the driver circuit section 15a, 16a corresponding to the driver circuit section 16.

Furthermore, the third stage driver circuit section 13a~
The output portions of the aluminum wires 16a are connected to the input portions of the internal circuit portion 22 via aluminum wires 171 to 174 in the wiring region 21, respectively, in a symmetrical manner when viewed from the internal circuit portion 22. Note that the aluminum wirings 171 to 174 are connected within the internal circuit section 22, and the wiring 17a corresponding to the wiring 17 in FIG. 1 is connected within the internal circuit section 22.
It is connected to each circuit section in 2 that processes a clock signal. At this time, the wiring 17a is connected, for example, in a loop shape within the internal circuit section 22 so as to be as equidistant as possible from each circuit section that processes clock signals within the internal circuit section 22.

Next, the operations shown in FIGS. 1 and 2 will be explained. First, in FIG. 1, a clock signal applied from clock input terminal 1 is output from input buffer circuit 2, and
It is driven by two first-stage driver circuits 3, two second-stage driver circuits 7 and 8, and four third-stage driver circuits 13 to 16. In addition, the third stage driver circuits 13 to 1
The output terminals 6 are connected to each other and supplied to an internal circuit (corresponding to the internal circuit section 22 in FIG. 2), not shown, via a wiring 17.

Similarly, in FIG. 2, the clock signal applied to the clock signal input PAD 18 is output from the input buffer circuit section 2a, and is first sent to the first stage driver circuit section 3.
input to a. Next, the output of the driver circuit section 3a is
The signal is input to second-stage driver circuit sections 7a and 8a that are equidistant from this driver circuit section 3a. Further, the output of the driver circuit section 7a is inputted to the third stage driver circuit sections 13a and 14a which are equidistant from this driver circuit section 7a, and the output of the driver circuit section 8a is inputted at an equal distance from this driver circuit section 8a. The third stage driver circuit section 15a located in
, 16a. In addition, the driver circuit section 13a~
The outputs of 16a are input to the internal circuit section 22 via aluminum wirings 171 to 174, respectively.

The aluminum wires 171 to 174 are connected within the internal circuit section 22, and a common wire corresponding to the wire 17 in FIG. 1 is connected to each circuit section within the internal circuit section 22 that processes clock signals. . At this time, the common wiring is arranged so that it is as equidistant as possible from each circuit section that processes clock signals within the internal circuit section 22, for example.
connected in a loop inside.

As explained above, according to the present invention,
In FIG. 1, the first stage driver circuit 3, the second stage driver circuits 7 and 8, and the third stage driver circuits 13 to 16
is configured in a tree structure, and the four driver circuits 1 in the third stage are arranged in a tree structure.
Since the 3 to 16 output terminals are connected to each other to derive one output, the driving ability of the entire circuit is increased and a high frequency clock can also be driven. Note that by making the transistor sizes of the third-stage driver circuits 13 to 16 variable at this time, it is possible to realize a clock distribution circuit having a driving ability compatible with any circuit scale.

In addition, in FIG. 2, the wiring lengths of the aluminum wirings 5a and 6a between the first-stage driver circuit section 3a and the second-stage driver circuit sections 7a and 8a are the same, respectively.
The wiring lengths of the aluminum wirings 9a to 12a between the driver circuit sections 7a and 8a of the third stage and the driver circuit sections 13a to 16a of the third stage are made to be the same, respectively. Since the layout on the LSI chip 23 is configured so that the outputs of the 16a are symmetrically input into the internal circuit section 21, there are Clock signal skew management becomes easier.

Note that in this embodiment, the driver circuit is
Stage driver circuit 3 and second stage driver circuits 7 and 8
Although a three-stage tree structure is used, including driver circuits 13 to 16 in the third stage, a structure other than three stages may be used.

Although FIG. 2 is shown as an example of the layout of the driver circuits on the LSI chip 23, this layout is particularly limited as long as the wiring length between each driver circuit in adjacent stages can be made the same. There's no need.

[0022]

As described above, according to the present invention, there is provided a plurality of driver circuits configured in a multi-stage tree structure,
In addition to making the wiring length between each driver circuit in adjacent stages the same, the output terminals of the final stage driver circuits are connected to derive one output, so that the final stage of the signal input to the first stage driver circuit Since the skews in the outputs of the driver circuits can be made the same and the driving ability of one final output can be increased, there is an effect that even high-frequency signals can be transmitted.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a clock distribution circuit in which driver circuits are arranged in a tree structure, showing one embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout when the circuit of FIG. 1 is mounted on an LSI chip.

FIG. 3 is a diagram showing a conventional clock distribution circuit.

FIG. 4 is a diagram showing an example of a layout when the circuit of FIG. 3 is mounted on an LSI chip.

[Explanation of symbols]

3, 7, 8, 13~16 Driver circuit 5, 6, 9~
12 Wiring

Claims (1)

[Claims] Claim 1: A driver circuit comprising a plurality of driver circuits configured in a multi-stage tree structure, with the wiring length between each driver circuit in adjacent stages being the same, and output terminals of the final stage driver circuits being connected to each other. A semiconductor integrated circuit characterized in that it derives two outputs.