JPH043536A - Ultrahigh speed multiplex and demultiplex system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding an ultra-high-speed multiplexing and demultiplexing circuit system for multiplexing and demultiplexing multi-channel signals at ultra-high speed, even if there is an unimplemented low-speed multiplexer on the transmitting side, the receiving The purpose of this is to enable frame synchronization on the side and channel matching with the transmitting side, by multiplexing the transmitted data and inserting frame synchronization information and channel identification numbers to create low-speed data. In addition to multiplexing the low-speed data of channels to generate and transmit ultra-high-speed data, the receiving side separates the ultra-high-speed data into low-speed data of multiple channels so that the channel identification number of the reference channel becomes the predetermined channel identification number. In an ultra-high-speed multiplexing/demultiplexing circuit system that rearranges the order of low-speed data and then separates the low-speed data of each channel into the original data, a 110 alternation pattern is used when the low-speed multiplexing section of the reference channel is not implemented. Generated frame synchronization information and
It is configured by inserting a channel identification number and sending it out, and when a low-speed multiplexing unit for channels other than the reference channel is not installed, a 110 alternating pattern is generated and sent out.

[Industrial Application Field] The present invention relates to a transmission device that multiplexes and demultiplexes multi-channel signals, and particularly an ultra-high-speed multiplexing and demultiplexing circuit system when it is necessary to multiplex and demultiplex multi-channel signals at ultra-high speed. It is related to.

In the case of digital signal transmission of multi-channel video signals without band compression, it is necessary to multiplex and demultiplex multi-channel signals at extremely high speed.

In such a case, the signal created by multiplexing in a low-speed multiplexer provided for each channel on the transmitting side is further multiplexed in an ultra-high-speed multiplexer and transmitted as serial data. The system configuration is such that the signal is separated into signals for each channel by an ultra-high-speed separation section, and then further separated by a low-speed separation section provided for each channel.

In this case, even if there is an unimplemented low-speed multiplexer on the transmitting side, it is possible to synchronize the frame on the receiving side and match the channel with the transmitting side, and it is possible to ensure the mark rate on the transmission path. It is desired that the channels on the transmitting side and the receiving side can be matched in a short time.

[Conventional technology]

FIG. 4 is a functional block diagram showing a conventional ultra-high speed multiplexing/demultiplexing circuit system. In the figure, 1 is a low-speed multiplexing unit for each channel CHI to CHn that multiplexes transmission data, and 2 is a low-speed multiplexing unit for each channel CHI to CHn from each low-speed multiplexing unit 1 to generate ultra-high-speed data consisting of serial data. These parts form the transmitting part. In addition, 3 is an ultra-high-speed separation unit that separates ultra-high-speed data into CHI to CHn, and 4 is CH1 to CHn separated by the ultra-high-speed separation unit 3.
This is a low-speed separation unit that separates low-speed data of CHn into original data.

On the transmitting side, the low-speed multiplexing unit 1 of CHI to CHn,
It has a synchronous multiplexer (MUX) 12 and multiplexes a plurality of transmission data to generate low-speed data for each channel.

There is also a synchronous frame insertion unit that inserts a frame pattern, and a CH-I that adds a channel identification number CH-ID.
It has a control data insertion section 11 consisting of a D addition section and a BSI data insertion section that inserts BSI data having a predetermined pattern, and its output data is inserted into low-speed data in a synchronous multiplexing section 12.

The ultra-high-speed multiplexer 2 is an n:1 parallel/serial converter (
P/S) 21, which converts the data of CH1 to CHn into serial data, multiplexes it into ultra-high speed data without compression, and sends it out to the transmission line.

On the receiving side, the ultra high-speed separator 3 converts the transmitted serial data into parallel data using a 1:n serial/
A parallel conversion unit (S/P) 31 and a shift matrix unit (S/P) for changing channels of separated parallel data.
SI FT MTX) 32, and a shift matrix control section (MTX CONT) 33 that controls channel replacement in the shift matrix section 32.

The serial/parallel converter 31 converts ultra-high-speed data into CH
Separate into low-speed data of I to CHn. At this time, the synchronization frame detection unit 34 detects a frame pattern from the CHI low-speed data, thereby establishing synchronization of the received signals. In addition, the CH-ID comparator 35 detects the channel identification number CH-ID from the CHI low-speed data, and
Compare the CH-I D generated in all occurrences 36, and if the comparison result does not match, the shift matrix control section 33
D Discrepancy information Discrepancy information. As a result, the shift matrix control section 33 controls the shift matrix section 32, whereby the channels in the shift matrix section 32 are replaced.

The low-speed separator 4 has a synchronization separator (DMUX) 41, separates the low-speed data of each channel, and reproduces the original data.

Conventionally, in devices that multiplex and demultiplex signals at ultra-high speeds, processing such as insertion and detection of BSI data and frame patterns is carried out on the ultra-high-speed side in order not to increase the transmission speed in the ultra-high-speed section. Because it was difficult to do
On the transmitting side, a low-speed multiplexer for each channel inserts a frame pattern, adds a CH-ID, and inserts BSI data, and then parallel/serial conversion is performed in an ultra-high-speed multiplexer. ing.

On the receiving side, the ultra-high-speed separator 3 detects the frame pattern inserted in the received data after serial/parallel conversion, establishes frame synchronization, and then sends the CH-ID comparator 35 In CHI
CH-I D and CH-I detected from the received data
Compare with D.

Since the CH-ID of the data output from the serial/parallel converter 31 does not necessarily match the CH-ID of the channel in which each low-speed separator 4 is installed, the channels on the transmitting side and the channel on the receiving side are made to match. There is a need. Therefore, if the CH-ID comparison result is a mismatch, the CH-ID comparison section 35 sends CH-ID mismatch information to the shift matrix control section 33, and outputs the output of the shift matrix section 32 to the current channel. Shift one channel from to the next channel. From now on, such operations will be performed with CH-
Repeat until the IDs match.

FIG. 5 is a diagram conceptually showing a channel shift operation.

In the figure, (1) to (n) represent channels of received data, and [1], [2], [3], . . . , [n] represent channels of the low-speed separation unit 4. Therefore, the example in FIG. 5 shows a state in which data sent from CH2 on the transmitting side appears on CHI on the receiving side.

In this state, the CH-ID comparison section 35 shifts the output of the shift matrix section 32 by one channel by the above-described operation, but it is assumed that the shift order at this time is fixed in the direction of the arrow in the figure. Therefore, in the example of FIG. 5, since the number of channels is n, it is necessary to repeat n-1 shifts until the transmitting side channel and the receiving side channel match.

After the CH-IDs match in this way, normal multiplexing and demultiplexing can be performed between the transmitting side and the receiving side.

[Problems to be Solved by the Invention] In the conventional ultra-high-speed multiplexing/demultiplexing circuit system shown in FIG. Since it is not possible to add IDs, etc., frame synchronization cannot be achieved on the receiving side, and at the same time, the rate at which "1°゛0"' changes appear in data on the transmission path, that is, the mark rate, decreases. , there is a problem in that it becomes difficult to recover the clock on the receiving side.

Also, on the receiving side, after frame synchronization is established,
If the CH-ID of the reference channel CHI and the CHiD detected from the received data do not match, the shift matrix section 32 shifts the comparison target channel by one channel and then changes the CH-ID again. Since the comparison is performed and such operations are repeated until they match, there is a problem in that it takes time to match the transmitting side channel and the receiving side channel.

The present invention aims to solve the problems of the prior art, and when transmitting multiple channels of low-speed data by ultra-high-speed multiplexing on the transmitting side and separating it into the original low-speed data on the receiving side, Even if there is an unimplemented low-speed multiplexer on the transmitting side, it is possible to synchronize the frame on the receiving side and match the channel with the transmitting side, and it is possible to ensure the mark rate on the transmission path. Furthermore, it is an object of the present invention to provide an ultra-high-speed multiplexing/demultiplexing circuit system that can match channels on the transmitting side and the receiving side in a short time.

[Means for Solving the Problems] As shown in the principle configuration of FIG. In an ultra-high-speed multiplexing/demultiplexing circuit system having a high-speed demultiplexing section 3 and a low-speed demultiplexing section 4 for multiple channels in the receiving section, a mounting state detection section 22 and a control data reinsertion section 23 are combined into an ultra-high-speed multiplexing section 2. The mounting state detection section 22 is provided in the low-speed data input section of the reference channel of the
and a 110 alternating pattern generating section 25 are provided at the low-speed data input section of channels other than the reference channel of the ultra-high-speed multiplexing section 2.

Here, the low-speed multiplexing unit 1 for multiple channels multiplexes transmission data, inserts frame synchronization information and a channel identification number into it, and generates low-speed data. Further, the ultra-high-speed multiplexer 2 multiplexes the low-speed data of the low-speed multiplexer 1 of a plurality of channels to generate ultra-high-speed data. The ultra-high-speed separation section 3 separates the ultra-high-speed data from the ultra-high-speed multiplexing section 2 into low-speed data of multiple channels, and also separates the separated low-speed data so that the channel identification number of the reference channel becomes a predetermined channel identification number. Reorder and output. Furthermore, the low-speed separator 4 separates the low-speed data of each channel output from the ultra-high-speed separator 3 into original data.

Further, the mounting state detecting section 22 detects whether the low-speed multiplexing section 1 is mounted in the transmitting section. The control data re-insertion unit 23 performs 11 when the low-speed multiplexing unit 1 is not installed.
It generates a 0 alternation pattern and inserts frame synchronization information and channel identification number into it,
The 110 alternating pattern generating section 25 generates a 110 alternating pattern when the low-speed multiplexing section 1 is not installed.

Further, the present invention detects the difference between the channel identification number of the received data of the reference channel and the predetermined channel identification number in the ultra-high-speed demultiplexing section 3 in the above-mentioned ultra-high-speed multiplexing/demultiplexing circuit system, and performs demultiplexing in accordance with this difference. The order of the low-speed data is rearranged and output.

[Effect]

On the transmitting side, by providing a control data insertion section 11 in the low-speed multiplexing section 1 of each channel, synchronous multiplexing is performed after inserting a synchronization frame, CH-ID, and BSI data into the transmission data, and ultra-high-speed multiplexing is performed. The data is sent to the converting section 2.

For the CHI input of the ultra-high-speed multiplexing unit 2, the mounting state detection unit 22 detects whether or not the low-speed multiplexing unit 1 is mounted, and if it is not installed, the selector 2
4 selects the output of the control data reinsertion section 23. The control data reinsertion unit 23 inserts the synchronization frame, CHID, and BSI data into the 110 alternating pattern and sends it to the parallel/serial conversion unit 21, thereby performing ultra high-speed multiplexing. If the low-speed multiplexer 1 is installed, the selector 24 selects the output of the low-speed multiplexer 1.

For the input of each CH other than CHI, the mounting state detection section 22 detects whether or not the low-speed multiplexing section 1 is mounted. If it is not mounted, the selection section 24 selects the 110 alternating The output of the pattern generator 25 is selected. 11
The 0 alternation pattern generation section 25 generates a pattern in which "1" and "0°" are randomly alternated, and sends it to the parallel/serial conversion section 21, thereby performing ultra high-speed multiplexing. If the low-speed multiplexer 1 is installed,
The selector 24 selects the output of the low-speed multiplexer 1.

On the receiving side, the serial/parallel converter 31 separates the data into data for each channel in the ultra-high-speed separator 3 . The separated data passes through the shift matrix unit 32, and the connection of the corresponding channel to the low-speed separation unit 4 is switched.

At the CHI output of the shift matrix section 32, a synchronization frame detection section 34 detects the frame inserted on the transmitting side to establish frame synchronization.

After establishing frame synchronization on CHI, CH-I
The CH-ID of the own channel from the D generation section 36 is compared with the CH-ID detected from the received data in the CH-ID comparison section 35. If the comparison result is a non-coincidence, information to that effect is sent to the shift matrix control section 33. As a result, the shift matrix control section 33 controls the shift matrix section 32 to perform channel switching.

At this time, the CM-ID comparison section 35 calculates the difference between the CH-ID on the transmitting side and a predetermined CH-ID on the receiving side, and notifies the shift matrix control section 33 of the difference. The shift matrix control section 33 controls the switching of channels in the shift matrix section 32 according to this difference.
Channel replacement takes place in a short time.

Therefore, according to the present invention, even if the low-speed multiplexing section of any channel is unimplemented, in CHI, the synchronization frame, C
By inserting H-ID and 110 alternating patterns, and inserting 110 patterns in other channels, the mark rate on the transmission path is ensured, and the C on the receiving side is
By detecting the synchronization frame and CH-ID at HI, it becomes possible to perform frame synchronization, compare CH-IDs, and swap channels.
Ultra-high speed data separation can be performed correctly.

In addition, if the CH-ID comparison result does not match, the CH-ID
- Since channel switching can be controlled according to the difference in ID, it is possible to match the channel on the transmitting side and the channel on the receiving side in a short time.

〔Example〕

FIG. 2 shows one embodiment of the present invention.
The same parts as in the figure are indicated by the same numbers, and 22 is an implementation state detection unit that detects whether or not the low-speed multiplexer 1 is installed, and 23 is a unit that detects the reinsertion of a synchronization frame and the channel identification number CH-ID. Re-attachment and reinsertion of BSI data,
and 110, a control data reinsertion section that generates an alternating pattern; 24, a selection section that selects the output of the low-speed multiplexing section 1 and the output of the control data reinsertion section 23; and 25, a "1"
” and “0” at random.

In FIG. 2, a 16-channel multiplexing/demultiplexing device is connected to a low-speed multiplexer l of CHI to CH16 and a low-speed demultiplexer 4'. The low-speed multiplexer 1 installed in each channel has a control data inserter 11, and a synchronization frame is provided in each channel.

Synchronous multiplexing is performed by inserting CH-ID and BSI data. In this embodiment, it is assumed that the low-speed multiplexer 1 and the low-speed demultiplexer 4 corresponding to CHI and CH2, which are shown surrounded by chain lines in FIG. 2, are not installed.

CHI mounting state detection unit 22 in ultra-high-speed multiplexing unit 2
When it is detected that the low-speed multiplexing unit 1 is not installed, the control data reinsertion unit 23 inserts the 110 alternation pattern and at the same time inserts the synchronization frame and CH-
Add ID. Furthermore, when the non-mounted state detecting section 22 of CH,2 to CH16 detects that the low-speed multiplexing section 1 is not mounted, a 110 alternating pattern is inserted. In this embodiment, only CH2 has the low-speed multiplexer l not implemented, so
Insert I10 alternating pattern only in CH2.

With the above operation, regardless of the implementation state of the low-speed multiplexer 1, the time slot corresponding to the CHI of the serial data sent from the ultra-high-speed multiplexer 2 to the transmission path has a synchronization frame and a CH-ID. is added.

On the receiving side, the ultra-high-speed demultiplexer 3 separates the data from the ultra-high-speed multiplexer 2 into each channel.

The separated data is transferred to CHI of the shift matrix section 32.
After the frame pattern is detected by the synchronization frame detection unit 34 mounted on the output and synchronization is established, the CH-I
By detecting D, the sending/borrowing channel and the receiving side channel are matched.

FIG. 3 is a flowchart showing the procedure for matching the channels on the transmitting side and the receiving side.
T7 represents each operation step.

First, a synchronization frame is detected in the synchronization frame detection section 34 mounted on the CHI of the shift matrix section 32 (STI). In the configuration of this embodiment, CHI and CH2
The low-speed multiplexing section is not yet implemented.

If the 110 alternating pattern sent from CH2 on the transmitting side appears in the CHI output of the shift matrix section 32, it means that CH2 on the transmitting side and CHI on the receiving side are connected. In this state, the synchronization frame detection unit 34 cannot detect a synchronization frame even after a predetermined synchronization pull-in time has elapsed (Sr1).

The synchronous frame detection section 34 transmits the synchronous frame detection information to the shift matrix control section 33.

The shift matrix control unit 33 that received this information,
The shift matrix section 32 is instructed to shift its output by one channel (Sr5). As a result, the data transmitted from CH3 on the transmitting side appears at the CHI output of the shift matrix section 32. After completing channel switching, STI and Sr1 operations are performed again.

After establishing the synchronization frame, try to detect the CH-ID.
T3), CH- added to the received data of this channel
CH-ID
This is performed in the comparing section 35 (Sr1). At this time, what is being compared is the CH-ID of CH3, so C
It does not match the CH-ID of HI.

Next, the CH-ID comparison unit 34 calculates the comparison result, that is, the difference between the detected CH-ID of CH3 and the CH-ID of CHI, and instructs the shift matrix control unit 33 to shift by two channels. (Sr6). The shift matrix control section 33 causes the shift matrix section 32 to shift its output by two channels according to the transmitted CH-ID comparison result. (Sr7).

Thereafter, by following the steps (STI) to (Sr1), frame synchronization is established, and the matching of the transmitting side channel and the receiving side channel is completed to perform normal multiplexing and demultiplexing.

〔Effect of the invention〕

As explained above, according to the present invention, when transmitting ultra-high-speed multiplexing of low-speed data from multiple low-speed multiplexers on the transmitting side and separating it into the original low-speed data on the receiving side, it is possible to Even if there is a low-speed multiplexer of
Since this is added, on the receiving side, it is possible to ensure a mark rate, achieve frame synchronization, and match the channel with the transmitting side. Furthermore, since the 110 alternating pattern is inserted for channels other than CHI, it is possible to ensure the mark rate on the transmission path.

Also, after establishing frame synchronization, CHI and CH of received data
Since the -IDs are compared and the channel is switched using the difference, the channels on the transmitting side and the receiving side can be matched in a short time.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a flowchart showing the procedure for matching channels on the transmitting side and the receiving side. 4
The figure is a functional block diagram showing a conventional ultra-high-speed multiplexing/demultiplexing circuit system, and FIG. 5 is a diagram conceptually showing a channel shift operation. 1 is a low-speed multiplexing unit, 2 is an ultra-high-speed multiplexing unit, 3 is an ultra-high-speed demultiplexing unit, 4 is a low-speed demultiplexing unit, 11 is a control data insertion unit, 1
2 is a synchronous multiplexing section, 22 is a mounting state detection section, 23 is a control data reinsertion section, and 25 is a 110 alternating pattern generation section.

Claims (2)

[Claims] (1) A low-speed multiplexing unit (1) for multiple channels that multiplexes transmission data and generates low-speed data by inserting frame synchronization information and a channel identification number therein; The transmission section includes an ultra-high-speed multiplexing section (2) that multiplexes and generates ultra-high-speed data, and separates the ultra-high-speed data into multiple channels of low-speed data, and the channel identification number of the reference channel is set to a predetermined channel identification number. an ultra-high-speed separation unit (3) that rearranges and outputs the separated low-speed data so that it becomes a number; and a multi-channel low-speed separation unit that separates the output low-speed data of each channel into the original data. In an ultra high-speed multiplexing/demultiplexing circuit system having a receiver section (4), a mounting state detecting section (22) detecting whether or not the low-speed multiplexing section (1) is mounted, and a low-speed multiplexing section (1) 1 when not implemented
A control data reinsertion unit (23) that generates a /0 alternating pattern and inserts frame synchronization information and a channel identification number into the low-speed data input of the reference channel of the ultra-high-speed multiplexing unit (2). and a 1/0 alternating pattern generating section (25) that generates a 1/0 alternating pattern when the low-speed multiplexing section (1) is not mounted. Multiplexing section (2)
An ultra-high-speed multiplexing/demultiplexing circuit system characterized by being provided at the low-speed data input section of channels other than the reference channel. (2) The ultra-high-speed separation unit (3) detects the difference between the channel identification number of the received data of the reference channel and the predetermined channel identification number, and rearranges the order of the separated low-speed data in accordance with the difference. 2. The ultrahigh-speed multiplexing/demultiplexing circuit system according to claim 1, wherein the ultrahigh-speed multiplexing/demultiplexing circuit system performs multiplexing and output.