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JPH0429353A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0429353A
JPH0429353A JP13512390A JP13512390A JPH0429353A JP H0429353 A JPH0429353 A JP H0429353A JP 13512390 A JP13512390 A JP 13512390A JP 13512390 A JP13512390 A JP 13512390A JP H0429353 A JPH0429353 A JP H0429353A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor
substrate
section
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13512390A
Other languages
Japanese (ja)
Inventor
Mitsuo Matsunami
松浪 光雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP13512390A priority Critical patent/JPH0429353A/en
Publication of JPH0429353A publication Critical patent/JPH0429353A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To achieve monolithic integration by forming an insulating film partially on the bonding face of at least one of semiconductor substrates attached directly to partially interpose the insulating film therebetween. CONSTITUTION:When semiconductor substrates 1 are attached, a directly attached section and a section with an insulating film 2 interposed therebetween are formed. With the substrates thus laminated, vertical devices are formed in the section without the insulating film 2 and devices subjected to dielectric insulation are formed in the section with the insulating film 2, making a semiconductor device having devices of different characteristics in one semiconductor substrate. Thereby, even if the semiconductor device requires vertical power MOSFET's, such as photo MOS relays, and high-voltage-output-type solar cells consisting of a plurality of solar cells subjected to dielectric isolation and connected in series, the vertical power MOSFET's can be formed in the section without the insulating film 2 of the substrate and the high-voltage-output-type solar cells can be formed in the section with the insulating film 2.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、特性が異なる半導体単結晶基板の表良に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to the surface quality of semiconductor single crystal substrates having different characteristics.

〈従来の技術〉 複数の半導体単結晶基板表面を接着した単一の積層構造
基板の特性を利用する半導体装置は、1970年代から
提案されていたが、技術上の問題などから実用化されて
いない。しかし、近年の半導体製造技術や、精密加工技
術や測定技術等の半導体製造の周辺技術などが急速に進
歩して、上記で説明した半導体装置が徐々に実用化にむ
かっている。
<Conventional technology> Semiconductor devices that utilize the characteristics of a single laminated structure substrate made by bonding the surfaces of multiple semiconductor single crystal substrates have been proposed since the 1970s, but have not been put to practical use due to technical problems. . However, in recent years, semiconductor manufacturing technology and peripheral technologies for semiconductor manufacturing, such as precision processing technology and measurement technology, have rapidly advanced, and the semiconductor devices described above are gradually coming into practical use.

以上の半導体装置には、半導体基板の接着界面に酸化膜
、窒化膜等の絶縁膜を形成した誘電体分離方式を主とし
た半導体装置と、半導体基板のみを積層して、その基板
の接着面で不純物濃度を急激に変化させることができる
などの特徴を利用した高耐圧デバイス等の半導体装置と
があった。
The above-mentioned semiconductor devices include semiconductor devices mainly using a dielectric isolation method in which an insulating film such as an oxide film or nitride film is formed on the bonding interface of the semiconductor substrate, and a semiconductor device in which only the semiconductor substrate is stacked and the bonding surface of the substrate is stacked. There have been semiconductor devices such as high-voltage devices that take advantage of features such as the ability to rapidly change impurity concentrations.

〈発明が解決しようとする課題〉 以上で説明した従来の半導体基板を接着した基板による
半導体装置は、その基板によ多形成できるデバイスの種
類が限定されるので、用途と応用範囲が限定され、その
半導体装置の機能的効果を広くできないという問題があ
また。例えば、従来の技術では半導体基板の接合面を利
用したパワーMO5FETを作製した基板に、誘電体分
離を利用した方が有利な直列接続の高電圧出力型太陽電
池や、高速スイッチングデバイスが作製できないので、
別の基板を用いることになった。
<Problems to be Solved by the Invention> The conventional semiconductor device described above using a substrate bonded with semiconductor substrates is limited in the types of devices that can be formed on the substrate, and therefore has a limited use and range of application. Another problem is that the functional effects of the semiconductor device cannot be widely extended. For example, with conventional technology, it is not possible to fabricate series-connected high-voltage output solar cells or high-speed switching devices, which are more advantageous by using dielectric isolation, on a substrate on which a power MO5FET using the junction surface of a semiconductor substrate is fabricated. ,
I decided to use a different board.

本発明は、従来の半導体基板を接着した基板の半導体装
置がもつ課題を解消し、半導体基板を接着した基板によ
る応用範囲が広く、かつ、機能的及び経済的効果の大き
い半導体装置を提供することを目的としている。
An object of the present invention is to solve the problems of the conventional semiconductor device using a substrate to which a semiconductor substrate is bonded, and to provide a semiconductor device that has a wide range of applications and has great functional and economical effects using a substrate to which a semiconductor substrate is bonded. It is an object.

〈課題を解決するための手段〉 本発明は、半導体基板を接着するとき、半導体基板が直
接接着する部分と、絶縁膜を介する部分にするものであ
る。
<Means for Solving the Problems> In the present invention, when bonding semiconductor substrates, the semiconductor substrates are bonded directly to a portion and to a portion via an insulating film.

以上で説明し九構成の積層型の基板を用いることで、絶
縁膜が介在しない部分に縦型デバイスを形成し、絶縁膜
が介在している部分に誘電膜分離(又は、絶縁膜外@>
のデバイスを形成することで、1枚の半導体基板上に特
性の異なるデバイスを形成した半導体装置にしている。
By using the laminated substrate with the nine configurations described above, a vertical device is formed in the part where there is no insulating film, and a dielectric film separation (or outside the insulating film) is made in the part where the insulating film is interposed.
By forming these devices, a semiconductor device is obtained in which devices with different characteristics are formed on one semiconductor substrate.

く作 用〉 以上で説明した、本発明の積層型の半導体基板を用いる
ことで、ホトMOSリレーのような、縦型パワーMO5
FETと絶縁膜分離した複数の太陽電池を直列接続した
高電圧出力型太陽電池とを必要とする半導体装置でも、
その基板の絶縁膜を介在させない部分に縦型パワーMO
3FETを形成し、絶縁膜を介在させた部分に高電圧出
力型太陽電池を形成して、作製できる。従1て、ホトM
OSリレーのように特性の異なるデバイスをもつ各種の
半導体装置を容易に構成できる。
Function> By using the laminated semiconductor substrate of the present invention as explained above, vertical power MO5 such as a photoMOS relay can be realized.
Even in semiconductor devices that require FETs and high-voltage output solar cells that are made by connecting multiple solar cells separated by insulating films in series,
A vertical power MO is installed on the part of the substrate that does not include an insulating film.
It can be manufactured by forming a 3FET and forming a high voltage output type solar cell in a portion with an insulating film interposed therebetween. First, photo M
Various semiconductor devices having devices with different characteristics such as OS relays can be easily configured.

〈実施例〉 以下、本発明の実施例を、その一部拡大した断面図面を
参照して説明する。
<Example> Hereinafter, an example of the present invention will be described with reference to partially enlarged cross-sectional drawings.

本発明の実施例では、接着が絶縁膜を介在させた部分と
、介在させない部分からなる2枚のSi半導体単結晶基
板からなるホ)MO3!Jレーについて説明する。
In the embodiment of the present invention, the adhesion consists of two Si semiconductor single crystal substrates, one with an insulating film interposed and the other without an insulating film. e) MO3! Let me explain about J-Lee.

従来は、ホトMOSリレーの、縦型パワーMO5FET
と、誘電膜分離の高電圧出力型太陽電池とは別々に作製
した半導体基板に作製した後、パ・ケジングで結合して
いたので、作製時間が長くなシ、小型化と低価格化に限
界があった。
Conventionally, vertical power MO5FET of photoMOS relay
In addition, dielectric film-separated high-voltage output solar cells were fabricated on separate semiconductor substrates and then combined through packaging, which took a long time to fabricate and limited miniaturization and cost reduction. was there.

本発明の実施例は、先ず第2図に示したようにn”(1
00)Si半導体基板1の表面の所定の部分を、ホトエ
ッチによるホトレジスト膜の形成とRI E (Rea
ctive Ion Et/ching )等で浅い段
差を形成し、熱酸化又は低温CVD等で5i02の絶縁
膜2が形成される。
Embodiments of the present invention are first implemented as shown in FIG.
00) Formation of a photoresist film by photoetching and RIE (Rea) on a predetermined portion of the surface of the Si semiconductor substrate 1
A shallow step is formed using active ion etching (active ion etching) or the like, and an insulating film 2 of 5i02 is formed using thermal oxidation or low-temperature CVD.

次にう・ピングやポリ・シング等の機械的な方法や、前
記のRIE技術によシ段差部の凸部になった5i03膜
の除去によシ、第8図に示したように、シリコン半導体
1の露出表面と絶縁膜2の表面とを平坦にした基板1に
した。
Next, as shown in FIG. 8, the 5i03 film, which has become a convex part of the step part, can be removed by mechanical methods such as ping or polishing, or by the RIE technique described above. The exposed surface of the semiconductor 1 and the surface of the insulating film 2 are made flat in the substrate 1.

以上のように形成した半導体基板1と、比抵抗が50〜
55Ω1程度のn−(100)Si半導体基板8とをH
,0,、又は、H2O2との混合液性した基板1と3は
接着する面に微細な異物も付着しないようにし、かつ、
接着する基板1と2との結晶方位をよく一致させ第4図
で示したように密若させた状態で800℃〜1800℃
の加熱を行ないSi半導体基板lとSi半導体基板3を
直接強固に接着させた。
The semiconductor substrate 1 formed as described above has a specific resistance of 50 to
H
, 0, or mixed liquid with H2O2, the substrates 1 and 3 should be made so that even minute foreign matter does not adhere to the surfaces to be bonded, and
The substrates 1 and 2 to be bonded are heated at 800°C to 1800°C in a state where the crystal orientations of the substrates 1 and 2 are well matched and the substrates are densely stacked as shown in Fig. 4.
Heating was performed to directly and firmly bond the Si semiconductor substrate 1 and the Si semiconductor substrate 3.

以上の実施例ではSi半導体基板8の接着面は半導体の
表面のみにしたが、この表面にも、基板1で説明した絶
縁膜を形成することができる。
In the above embodiments, the bonding surface of the Si semiconductor substrate 8 is only the semiconductor surface, but the insulating film described in connection with the substrate 1 can also be formed on this surface.

一般にSi半導体基板は一定以上の厚さをもつので、S
i半導体基板3を、ポリッシングやラフ力 ピング等のメyニカルな方法、又はKOHやNaOH等
を用いた化学的な方法による加工で、80μm程度の平
坦な層にした上、熱酸化、プラズマcVD(Chmic
al  Vapour  Deposition)等に
よυSiO□、Ni3N、等の絶縁膜4を形成する。絶
縁膜4の所定の位置にホトエツチングで開ロバターンを
形成した膜4をマスクにして、KOH。
In general, Si semiconductor substrates have a thickness above a certain level, so S
i The semiconductor substrate 3 is processed into a flat layer of approximately 80 μm by mechanical methods such as polishing and rough force pinning, or chemical methods using KOH, NaOH, etc., and then thermal oxidation and plasma CVD. (Chmic
An insulating film 4 of υSiO□, Ni3N, etc. is formed by Al Vapor Deposition) or the like. Using the film 4 with an open pattern formed by photoetching at a predetermined position of the insulating film 4 as a mask, KOH is applied.

NaOH等のアルカリエッチャントによるエフ千ングで
、第5図のようにSi半導体基板8に溝を形成すること
で、絶縁膜2の上に所定の形状のSi半導体単結晶のア
イランド(島)を作製した。
By forming grooves in the Si semiconductor substrate 8 as shown in FIG. 5 by etching with an alkaline etchant such as NaOH, an island of Si semiconductor single crystal of a predetermined shape is created on the insulating film 2. did.

続いて、絶縁膜4をエツチングで除去し、再び熱酸化、
低温CVD等によりSi半半導体3面所定の条件でのS
iH.の熱分解、SiCノ.の水素還元によシSi多結
晶膜6を堆積した状態を示したのが第6図である。更に
、ポリシング,ラフピング等の機械的な方法と、H F
 、H N O s等による化学的方法により、前記の
溝のなかに充填された部分以外のSi多結晶膜6及び絶
縁膜5を除去して平坦化した後、熱酸化等によ,9Si
Ozの絶縁膜7を形成したのが第7図である。
Subsequently, the insulating film 4 is removed by etching, and thermal oxidation is performed again.
S is deposited on three Si semi-semiconductor surfaces under specified conditions by low-temperature CVD, etc.
iH. Thermal decomposition of SiC no. FIG. 6 shows a state in which a Si polycrystalline film 6 is deposited by hydrogen reduction. Furthermore, mechanical methods such as polishing and roughing, and H F
, HNOs, etc., to remove and planarize the Si polycrystalline film 6 and the insulating film 5 other than the portions filled in the grooves, and then remove 9Si by thermal oxidation or the like.
FIG. 7 shows the insulating film 7 of Oz formed.

以上で形成したSi半導体基板に、集積回路の製造技術
であるホトエツチング技術6選択エフチングによ,9S
i02膜7に所定のパターンの開口部を形成し、その開
口部形成に用いたホトレジスト及び5io2膜7をマス
クにして、Si半半導体基板圧イオン注入法によシホウ
素元素を所定の条件による打込みと、活性化処理にょシ
縦型MO5 FETのチャンネル部を形成するためのp
−5iウニ/L/8.高耐圧化のp−5iガードリ上記
の活性化処理は1100’C程度の酸素中の長時間熱処
理であ夛、前記開口部にも数千λの5i02膜が形成さ
れる。再度、これらの5i02膜に前記の開口部形成の
方法によシ縦型MO8FETチャンネルを形成し、ソー
スコンタクト領域及び太陽電池素子のn−5i拡散層を
形成する領域に開口部を設けるようパターン化した5i
Oa膜9にした。
The Si semiconductor substrate formed above is etched by 6-select etching, which is a photo-etching technique used to manufacture integrated circuits.
Openings with a predetermined pattern are formed in the i02 film 7, and using the photoresist used to form the openings and the 5io2 film 7 as a mask, a Si boron element is implanted under predetermined conditions by the Si semi-semiconductor substrate pressure ion implantation method. and p for forming the channel part of the vertical MO5 FET during the activation process.
-5i sea urchin/L/8. P-5i Gardry for High Withstand Voltage The above activation process is a long-time heat treatment in oxygen at about 1100'C, and a 5i02 film of several thousand λ is also formed in the opening. Vertical MO8FET channels were again formed in these 5i02 films by the method for forming openings described above, and patterned to provide openings in the source contact region and the region where the n-5i diffusion layer of the solar cell element was to be formed. 5i
Oa film 9 was used.

続いて、縦型MO5Tのゲート部に、約1000λの熱
酸化5iOz膜と、SiH4の熱分解によるポリSi膜
を積層して形成し、不要な部分をホトエツチング技術,
イオンエツチング等の選択エツチングによって、除去し
て5i02 ゲート絶縁膜lOと縦型MO8 FETの
ポリSi膜ゲート電極11を形成した。
Next, a thermally oxidized 5iOz film with a thickness of approximately 1000λ and a poly-Si film produced by thermal decomposition of SiH4 were laminated on the gate part of the vertical MO5T, and unnecessary parts were removed using photoetching technology.
It was removed by selective etching such as ion etching to form a 5i02 gate insulating film 1O and a poly-Si film gate electrode 11 of a vertical MO8 FET.

更に続いて、イオン注入法、または、熱拡散法により、
縦型MO3FETのソースコンタクト領域と太陽電池の
受光面になる領域等に浅いn” S i拡散層12.1
2’を形成し、以後の工程に不要になる縦型MO5 F
ETのp−5iウエル上に形成されたn”Si拡散層1
2を作製するためのマスクにした5i02膜と、熱拡散
法や活性化熱処理でn”−5i拡散層12.12’の上
に形成された5i02膜を選択上・チング法により除去
したのが第8図である。
Furthermore, by ion implantation method or thermal diffusion method,
A shallow n” Si diffusion layer 12.1 is formed in the source contact region of the vertical MO3FET and the region that becomes the light-receiving surface of the solar cell.
Vertical MO5 F which forms 2' and becomes unnecessary for subsequent processes.
n”Si diffusion layer 1 formed on the p-5i well of ET
The 5i02 film used as a mask for manufacturing 2 and the 5i02 film formed on the n''-5i diffusion layer 12.12' by the thermal diffusion method or activation heat treatment were selectively removed by the ching method. FIG.

次に、低温CVD法.プラズマCVD法等で5i02な
どの絶縁膜18をSi半導体基板の表面に被覆した上、
前記の選択エツチング法で、縦型MO5 FETのソー
ヌ領域でのn”−5i拡散層12の電極コンタクト部、
p−5i拡散層8の所定の領域、および、p−Siガー
ドリング8′の所定の領域などに開口を形成した上、A
J薄膜をスパッタリング、電子ビーム蒸着等で形成した
Next, low temperature CVD method. After coating the surface of the Si semiconductor substrate with an insulating film 18 such as 5i02 by plasma CVD method or the like,
By the selective etching method described above, the electrode contact portion of the n''-5i diffusion layer 12 in the Saone region of the vertical MO5 FET,
After forming openings in a predetermined region of the p-5i diffusion layer 8 and a predetermined region of the p-Si guard ring 8',
A J thin film was formed by sputtering, electron beam evaporation, etc.

形成したAノ薄膜は、Aノに対するホトエッチ技術1選
択工・チング技術を用いて所定のパターンのAノ配線1
4を形成した。更にAノ配線14を形成した基板の表面
を絶縁膜15で被覆した。この絶縁膜15は、低温CV
D,プラズマCVDによる5i02又はSi3N4で形
成することができる。
The formed A thin film is formed into a predetermined pattern of A wiring 1 using a photoetching technique 1 selective process/etching technique for A.
4 was formed. Further, the surface of the substrate on which the A wiring 14 was formed was covered with an insulating film 15. This insulating film 15 is
D. Can be formed from 5i02 or Si3N4 by plasma CVD.

以上に続いて、前記のAj!配線14の形成と同じ方法
によシ、太陽電池素子の電極接続部の開口形成と所定パ
ターンAノ配線16形成によシ各太陽電池を直接続して
”高電圧出力型太陽電池”の構成にしたのが第1図であ
る。
Following the above, the aforementioned Aj! Using the same method as for forming the wiring 14, each solar cell is directly connected by forming an opening for the electrode connection part of the solar cell element and forming the wiring 16 in a predetermined pattern A to form a "high voltage output solar cell". Figure 1 shows this.

なお、第1図に示したように高い電圧が印加されるAノ
配線16はp−3iガ一ドリング部8の上に配設された
Aノ配線に接続している。
Incidentally, as shown in FIG. 1, the A wiring 16 to which a high voltage is applied is connected to the A wiring arranged above the p-3i gadling portion 8.

以上のような第1図の構成で縦型MO5 FETと高電
圧出力型太陽電池を単一半導体基板上に合理的に形成で
きるので、本実施例で期待したホトMOSリレー(光駆
動型半導体装置)になった。
With the configuration shown in FIG. 1 as described above, a vertical MO5 FET and a high voltage output solar cell can be rationally formed on a single semiconductor substrate. )Became.

なお、以上の本発明の実施例では、本発明の詳細な説明
できるホトMOSリレーの一部のみの構成で示したが、
とのホトMOSリレーのスイッチング動作速度を向上さ
せる周辺回路を太陽電池素子を形成したようなアイラン
ドに形成すればよいことは容易に考えられる。
In addition, in the above embodiments of the present invention, only a part of the photoMOS relay configuration was shown, which can explain the present invention in detail.
It is easily conceivable that a peripheral circuit for improving the switching operation speed of the photoMOS relay may be formed on an island similar to the solar cell element.

又、本実施例では、本発明をホ)MO3!Jし−の高電
圧部と高出力部をもつ光駆動型半導体装置で説明したが
、本発明は、この実施例のホ)MO!リレーに限定され
ず高耐圧、高電力又は高速等のデバイス又は回路を一つ
の基板上に形成するスマートパワーIC等に効果的に利
用できるものである。
In addition, in this example, the present invention is described as e) MO3! Although the description has been made using an optically driven semiconductor device having a high voltage section and a high output section, the present invention is applicable to the MO! The present invention is not limited to relays, but can be effectively used in smart power ICs and the like in which high-voltage, high-power, high-speed devices or circuits are formed on one substrate.

〈発明の効果〉 本発明は、複数の半導体単結晶基板を部分的に絶縁膜を
介在させて接着する構成で、接着する各半導体基板の結
晶性と不純物濃度の均一性が保たれることから、高耐圧
接合や絶縁膜分離された結晶性のよいアイランドに、そ
れぞれ特性の良いデバイスを形成したモノリシウク集積
化ができる。
<Effects of the Invention> The present invention has a configuration in which a plurality of semiconductor single crystal substrates are bonded with an insulating film partially interposed therebetween, and the crystallinity and impurity concentration uniformity of each semiconductor substrate to be bonded is maintained. , monolithic integration is possible in which devices with good characteristics are formed on islands with good crystallinity separated by high-voltage junctions or insulating films.

従って、例えばホトMOSリレーのときも(イ)縦型パ
ワーMO5FETは、従来の厚いエピタキシャル膜をも
つ高価な基板は不要で、しかも質の良いバルク結晶体で
形成でき、良好な素子特性が得られる。10】複数の太
陽電池素子を直列接続した高電圧出力型太陽電池も絶縁
膜で分離された結晶性の良いアイランドに形成できる。
Therefore, for example, in the case of photoMOS relays, (a) vertical power MO5FETs do not require the conventional expensive substrate with a thick epitaxial film, and can be formed from high-quality bulk crystals, resulting in good device characteristics. . 10. A high voltage output type solar cell in which a plurality of solar cell elements are connected in series can also be formed on islands with good crystallinity separated by an insulating film.

(71以上の縦型パワーMO5FET、太陽電池素子及
びその周辺回路の素子も同一基板上に作製するので作製
プロセスを共通に使える。に))各種のデバイスを−チ
・プに集積できて、パフケージングコストの低下と小型
化を図ることができる等の効果がある。
(Since 71 or more vertical power MO5FETs, solar cell elements, and their peripheral circuit elements are also manufactured on the same substrate, the manufacturing process can be shared.) Various devices can be integrated on a chip, and There are effects such as reduction in caging cost and miniaturization.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例の一部を拡大した断面図、
第2図乃至第8図は実施例の製造工程を示す一部拡大断
面図である。 1.8・・・(100)Si半導体基板、2.4.5゜
7、9.18.15・・・絶縁膜、6・・・Si多結晶
膜、8.8’、8”・・・p−5i拡散層、10・・・
ゲート絶縁膜、11・・・ポリシリコン電極、12.1
2’・・・n−3i拡散層、14.16・・・Aノ配線
。 代理人 弁理士 梅 1)  勝C他2名)第2図 第3図 第4図 ! @51!!!! 9フ
FIG. 1 is a partially enlarged sectional view of an embodiment of the present invention;
2 to 8 are partially enlarged sectional views showing the manufacturing process of the embodiment. 1.8... (100) Si semiconductor substrate, 2.4.5°7, 9.18.15... Insulating film, 6... Si polycrystalline film, 8.8', 8"...・p-5i diffusion layer, 10...
Gate insulating film, 11... polysilicon electrode, 12.1
2'...n-3i diffusion layer, 14.16...A wiring. Agent Patent Attorney Ume 1) Katsu C and 2 others) Figure 2 Figure 3 Figure 4! @51! ! ! ! 9f

Claims (1)

【特許請求の範囲】 1、少なくとも2枚の半導体単結晶基板の表面を直接接
着した積層構成の基板に、半導体デバイスが形成された
半導体装置において、前記直接接着した半導体基板の少
くとも一方の半導体基板の接着面に部分的な絶縁膜が形
成され、部分的に絶縁膜を介在させた接着であることを
特徴とする半導体装置。 2、前記積層型半導体基板で形成された半導体装置にお
いて、前記半導体基板中の、前記絶縁膜が介在しない部
分に縦型構成のデバイスが形成され、前記絶縁膜を介在
させた部分に絶縁膜分離したデバイスが形成されている
ことを特徴とする請求項1記載の半導体装置。
[Scope of Claims] 1. In a semiconductor device in which a semiconductor device is formed on a substrate with a laminated structure in which the surfaces of at least two semiconductor single crystal substrates are directly bonded, at least one semiconductor of the directly bonded semiconductor substrates is provided. A semiconductor device characterized in that a partial insulating film is formed on the bonding surface of a substrate, and the bonding is performed with the insulating film partially interposed. 2. In a semiconductor device formed using the laminated semiconductor substrate, a device having a vertical structure is formed in a portion of the semiconductor substrate where the insulating film is not interposed, and an insulating film separation is formed in a portion where the insulating film is interposed. 2. The semiconductor device according to claim 1, wherein a device is formed.
JP13512390A 1990-05-24 1990-05-24 Semiconductor device Pending JPH0429353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13512390A JPH0429353A (en) 1990-05-24 1990-05-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13512390A JPH0429353A (en) 1990-05-24 1990-05-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0429353A true JPH0429353A (en) 1992-01-31

Family

ID=15144363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13512390A Pending JPH0429353A (en) 1990-05-24 1990-05-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0429353A (en)

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US5573972A (en) * 1994-07-29 1996-11-12 Nec Corporation Method for manufacturing a silicon bonded wafer
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US5723895A (en) * 1995-12-14 1998-03-03 Nec Corporation Field effect transistor formed in semiconductor region surrounded by insulating film
US5726089A (en) * 1992-11-25 1998-03-10 Nec Corporation Semiconductor device and method for fabricating the same
US5844294A (en) * 1995-12-28 1998-12-01 Nec Corporation Semiconductor substrate with SOI structure
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor
US5969401A (en) * 1996-12-13 1999-10-19 Nec Corporation Silicon on insulator substrate with improved insulation patterns
US5985681A (en) * 1995-10-13 1999-11-16 Nec Corporation Method of producing bonded substrate with silicon-on-insulator structure
US6096433A (en) * 1997-02-20 2000-08-01 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
JP2005079109A (en) * 2003-08-29 2005-03-24 Sumitomo Mitsubishi Silicon Corp Method for manufacturing lamination soi wafer, lamination soi wafer manufactured by the method
JP2006512754A (en) * 2002-12-24 2006-04-13 コミサリヤ・ア・レネルジ・アトミク Composite substrate manufacturing method and structure thus obtained
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US5726089A (en) * 1992-11-25 1998-03-10 Nec Corporation Semiconductor device and method for fabricating the same
US5872388A (en) * 1992-11-25 1999-02-16 Nec Corporation Semiconductor device and method for fabricating the same
EP0701286A1 (en) 1994-06-16 1996-03-13 Nec Corporation Silicon on insulating substrate and manufacturing method for same
US6004406A (en) * 1994-06-16 1999-12-21 Nec Corporation Silicon on insulating substrate
US5573972A (en) * 1994-07-29 1996-11-12 Nec Corporation Method for manufacturing a silicon bonded wafer
JPH098128A (en) * 1995-06-16 1997-01-10 Nec Corp Soi substrate and its manufacturing method
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
US5985681A (en) * 1995-10-13 1999-11-16 Nec Corporation Method of producing bonded substrate with silicon-on-insulator structure
US5723895A (en) * 1995-12-14 1998-03-03 Nec Corporation Field effect transistor formed in semiconductor region surrounded by insulating film
US5844294A (en) * 1995-12-28 1998-12-01 Nec Corporation Semiconductor substrate with SOI structure
US5969401A (en) * 1996-12-13 1999-10-19 Nec Corporation Silicon on insulator substrate with improved insulation patterns
US6096433A (en) * 1997-02-20 2000-08-01 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
US6346435B1 (en) 1997-02-20 2002-02-12 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor
JP2006512754A (en) * 2002-12-24 2006-04-13 コミサリヤ・ア・レネルジ・アトミク Composite substrate manufacturing method and structure thus obtained
JP2005079109A (en) * 2003-08-29 2005-03-24 Sumitomo Mitsubishi Silicon Corp Method for manufacturing lamination soi wafer, lamination soi wafer manufactured by the method
JP4581349B2 (en) * 2003-08-29 2010-11-17 株式会社Sumco Manufacturing method of bonded SOI wafer
US7781309B2 (en) 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US7855129B2 (en) 2005-12-22 2010-12-21 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
USD941916S1 (en) 2018-06-08 2022-01-25 Ccl Label, Inc. Label sheet layout assembly

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