JPH04273164A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which has reduced an input capacitance by reducing an area of a gate electrode. CONSTITUTION:A gate electrode 1 is formed only on a channel part 4 defined between source regions 2 and drain regions 3 of a plurality of MOSFETs arranged in an array and the gate electrodes 1 are mutually connected with a stripe connecting part 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOS field effect transistor (hereinafter referred to as MOSFET).

0002

2. Description of the Related Art Conventionally, in a semiconductor device in which a plurality of MOSFET elements are arranged in an array, a channel is formed between a source region 12 and a drain region 13, as shown in a plan view in FIG. A gate electrode (usually a gate polycrystalline silicon film) 11 is formed not only on the portion 14 but also on one of the source and drain regions, and the gate electrode has a mesh structure. Also, as another example,
As shown in FIG. 4, the gate electrode 1 other than the channel part 14
A structure in which a cross-shaped cutout 15 is formed in 1 has also been proposed.

0003

[Problem to be solved by the invention] Such a conventional MO
In the SFET, since the gate electrode is formed in areas other than the channel portion 14, the area of the gate electrode as a whole becomes large and unnecessary input capacitance is added. Therefore, there is a problem that the switching speed of the MOSFET is reduced, making it difficult to apply it to high-frequency semiconductor devices. An object of the present invention is to provide a semiconductor device in which the area of a gate electrode is reduced to reduce input capacitance.

0004

[Means for Solving the Problems] A semiconductor device of the present invention includes:
A gate electrode is formed only on the channel portions of a plurality of MOSFETs arranged in an array, and each gate electrode is connected to each other by a strip-like connection portion.

[0005]

According to the present invention, the gate electrode extends substantially only over the channel portion, thereby reducing the area and input capacitance.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view of one embodiment of the present invention. In the figure, a source region 2 and a drain region 3 are arranged in a grid pattern, and a plurality of channel portions 4 are defined in a rectangular frame shape between these regions. The gate electrode 1 is formed of a polycrystalline silicon film, and is patterned into a frame shape so as to extend over the channel section 4, and the gate electrode 1 on each channel section 4 is formed of a polycrystalline silicon film.
are connected in one direction by an integrally formed strip-like connecting portion 5. FIG. 2 is a diagram schematically showing a wider area than in FIG. are connected to aluminum electrodes 6 as shown in FIG.

According to this structure, the gate electrode 1 is formed only on the channel part 4, and the connecting part 5 is formed on the other part.
Since it is only provided in one piece, it is possible to reduce the overall area. As a result, the input capacitance can be reduced, the switching speed of the MOSFET can be increased, and the MOSFET can be applied to high-frequency semiconductor devices. Also, Figure 2
By configuring the gate finger with the aluminum electrode 6 as shown in FIG. 1, the impedance in the gate electrode 1 can be reduced and the switching operation can be performed more advantageously.

[0008]

[Effects of the Invention] As explained above, in the present invention, since the gate electrode extends only substantially over the channel portion,
By reducing the area of the gate electrode and reducing the input capacitance, MOS
This has the effect of increasing the switching speed of the FET.

[Brief explanation of the drawing]

FIG. 1 is a plan view of essential parts of an embodiment of the present invention.

FIG. 2 is a schematic plan view showing a wide range of FIG. 1;

FIG. 3 is a plan view of an example of a conventional gate electrode.

FIG. 4 is a plan view of another example of a conventional gate electrode.

[Explanation of symbols]

1 Gate electrode 2 Source area 3 Drain region 4 Channel part 5 Connection part 6 Aluminum electrode

Claims (1)

[Claims] 1. A semiconductor device including a plurality of MOS field effect transistor elements arranged in an array,
1. A semiconductor device characterized in that a gate electrode is formed only on a channel portion of each MOS type field effect transistor element, and each gate electrode is connected to each other by a strip-like connection portion.