JPH06342813A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide electrode construction for a field effect transistor capable of providing a larger output power even in the case of a small-area semiconductor substrate. CONSTITUTION:Three drain electrodes 60 are connected to a drain drawing-out region 70 provided in the vicinity of the output-side side 12 of a semiconductor substrate 10 on the opposite side to the input-side edge 11. Four source electrode 50 are connected to a rear electrode on the rear of the semiconductor substrate 10 through a via hole 51, and grounded. A first group of electrode fingers 33 are connected to the gate drawing-out region 20 through a first gate bus 35 provided with width smaller than that of the gate drawing-out region 20 on the side opposite to the input-side edge 11 of the gate drawing-out region 20, and a second group 34 of electrode fingers are provided through a second gate bus 36 in an area of the input-side edge 11 on the semiconductor substrate where the gate drawing-out region 20 is not provided. Accordingly, it becomes possible to obtain larger gate electrode width on the semiconductor substrate and raise output power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor for high frequency power amplification having a comb structure.

[0002]

2. Description of the Related Art Since the output power of a GaAs field effect transistor is proportional to its gate width, a gate width of 10 mm or more is usually required to obtain an output power of several watts or more. In order to obtain such a long gate width, a planar structure called a comb structure in which a gate electrode is divided into a plurality of electrode fingers and connected in parallel is used.

FIG. 1 shows an example of a planar structure of a GaAs field effect transistor using a comb structure. Semiconductor substrate 1
A gate lead-out region 20 for inputting a signal is provided in the vicinity of the input side 11 above 0. The gate electrode 30 forming a Schottky junction is provided separately on a plurality of electrode fingers 31 of the same length on an active region 40 formed by ion implantation. The length of the electrode finger 31 is limited to a length that does not affect the high frequency characteristics. Electrode finger 31
Are connected to the gate lead-out region 20 by the gate bus 32 on the gate lead-out region 20 side.

The source electrode 50 and the drain electrode 60 are provided on the active region 40 so as to sandwich the gate electrode finger 31 therebetween. Drain electrode 60 that outputs a signal
Are connected to a drain lead region 70 provided near the output side 12. The source electrode 50 is connected to the back surface of the semiconductor substrate 10 via the via hole 51 and is grounded. In addition, a source lead-out region may be provided on the surface of the semiconductor substrate 10 and may be connected by a multilayer wiring such as an aerial wiring (air bridge).

[0005]

With such a comb structure, it is possible to obtain a certain amount of output power with a small semiconductor substrate area (chip area), but the output power is not sufficient. Therefore, it is difficult to further reduce the manufacturing cost of the field effect transistor, which is almost proportional to the area of the semiconductor substrate. In particular, in the semiconductor device using the GaAs substrate, which has high substrate cost and wafer process cost, in order to reduce the manufacturing cost,
It has been desired to obtain more output power than ever before from a narrower semiconductor substrate.

The present invention has solved the above problems, and an object of the present invention is to provide an electrode structure of a field effect transistor capable of obtaining a larger output power even in a small area of a semiconductor substrate. .

[0007]

In order to solve the above problems, the present invention provides a rectangular semiconductor substrate and a gate electrode, a drain electrode, a source electrode provided on one main surface of the semiconductor substrate, And a field effect transistor including a plurality of lead-out regions respectively connected to the gate electrode and the drain electrode, wherein (a) one of the lead-out regions is near one side of the semiconductor substrate and has a width narrower than the length of the side. (B) the other lead-out region is provided near the other side of the semiconductor substrate facing the one side, and (c) the gate electrode is substantially perpendicular to the one side. A first electrode finger group formed of a plurality of electrode fingers extending in the direction from one of the lead regions to the other side, and the one lead region. A second electrode finger group composed of a plurality of electrode fingers extending from the vicinity of the one side to the other side, and (d) the source electrode and the drain electrode are the gate electrode fingers. The gist is that they are provided adjacent to each other.

It is preferable that the semiconductor substrate is made of a compound semiconductor such as GaAs, and the source electrode is led out through a through hole (via hole).

[0009]

With the above structure, the electrode fingers forming the gate electrode can be arranged in a region near one side of the semiconductor substrate where the lead-out region is not provided. A long gate electrode width can be obtained. Therefore, a field effect transistor having a large output power can be formed on the same semiconductor substrate, the manufacturing cost can be reduced, and the element can be downsized.

In particular, in a field effect transistor using a compound semiconductor such as GaAs which is used at a frequency higher than microwaves, the miniaturization of the element improves the high frequency characteristics and further reduces the manufacturing cost.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A GaAs field effect transistor which is an embodiment of the present invention will be described with reference to FIGS. 2 to 4 which are plan views thereof. 2 to 4, the same or equivalent members as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and duplicate description will be omitted.

The first embodiment is shown in FIG. Semi-insulating Ga
In the vicinity of the input side 11 on the semiconductor substrate 10 made of As, a gate lead-out region 20 made of a metal layer formed by continuous vapor deposition of AuGe / Ni / Au for signal input is provided. The size of the gate lead-out region 20 is the minimum size necessary for wire bonding, and is a width that is less than half the length of the input side 11. Gate electrode 30 made of Ti metal layer formed by vapor deposition
Is composed of a first electrode finger group consisting of two short first electrode fingers 33 and a second electrode finger group consisting of four long second electrode fingers 34. The electrode fingers 33 and 34 having a gate length of 0.8 μm are almost in the signal input / output direction (input side 11
Direction perpendicular to the). The first electrode finger group is provided with the second electrode through the first gate bus 35 provided on the side of the gate lead-out region 20 facing the input side 11 with a width narrower than that of the gate lead-out region 20. The finger group is connected to the gate lead-out region 20 via a second gate bus 36 provided in a region of the input side 11 on the semiconductor substrate 10 where the gate lead-out region 20 is not provided. The first and second gate buses 35,
Reference numeral 36 denotes a Mo / Au metal layer formed by vapor deposition, and the first and second electrode fingers 33 and 34 are arranged on an active region 40 formed by ion implantation of Si.

The source electrode 50 and the drain electrode 60 are provided on the active region 40 so as to sandwich the gate electrode fingers 33 and 34, respectively. 3 drain electrodes 6
0 is a drain lead region 70 provided in the vicinity of the output side 12 on the opposite side of the input side 11 on the semiconductor substrate 10.
It is connected to the. The four source electrodes 50 are connected to the back surface electrodes on the back surface of the semiconductor substrate 10 via the via holes 51 and are grounded. The source electrode 50, the drain electrode 60, and the drain extraction region 70 are made of AuGe /
It is composed of a metal layer formed by continuous vapor deposition of Ni / Au, and is formed simultaneously with the gate lead-out region 20.

According to this first embodiment, the semiconductor substrate 1
Gate lead-out region 20 near input side 11 of 0
Since the portion of the second gate electrode finger, which is longer than the first gate electrode finger, can be arranged in the region where the gate electrode is not provided, a longer gate electrode width can be obtained on the semiconductor substrate 10, and the output power can be increased. Can be increased.

Next, a second embodiment is shown in FIG. As a difference from the first embodiment, the gate extraction region 20 is
The central portion of the input side 11 on the semiconductor substrate 10 is arranged,
A second electrode finger group consisting of long second electrode fingers 34 is divided into regions on both sides of the gate lead-out region 20, and accordingly, the second gate bus 36 is also divided into regions on both sides of the gate lead-out region 20. Is provided. The other structure is similar to that of the first embodiment.

According to the second embodiment, a longer gate electrode width can be obtained as in the first embodiment, and even if the width of the semiconductor substrate 10 is relatively wide, the gate lead-out region 20 can be removed. Since the distance to the second gate electrode finger 34 does not become long, deterioration of high frequency characteristics can be prevented.

Furthermore, a third embodiment is shown in FIG. First
The difference from the above embodiment is that the drain lead-out region 70 provided in the vicinity of the output side 12 is the minimum size required for wire bonding, and is about half the length of the output side 12. Width. Therefore, a part of the first or second gate electrode finger 33 or 34 can be arranged in a region in the vicinity of the output side 12 of the semiconductor substrate 10 where the drain extraction region 70 is not provided. It is possible to obtain a longer gate electrode width on the semiconductor substrate 10 than in the first embodiment, and it is possible to increase the output power. In addition, since the drain lead-out region 70 is provided in the vicinity of the side opposite to the gate lead-out region 20, the gate lead-out region 20 extends to the gate electrode fingers 33, 3.
4 and the distance from the drain electrode 60 to the drain extraction region 70 can be made uniform, so that deterioration of high frequency characteristics can be prevented.

In the above embodiment, the source electrode 50 is used.
Is connected to the back surface electrode of the back surface of the semiconductor substrate 10 via the via hole 51, but a source extraction region may be provided on the front surface of the semiconductor substrate 10 and may be connected via an air bridge or the like. First and second gate bus 3
Although the gate electrode fingers 33 and 34 are connected via 5 and 36, one gate bus may be connected or the gate electrode region 33 may be directly connected to the gate lead-out region 20. The length, width, number, constituent materials and the like of the source electrode, the drain electrode and the gate electrode finger can be appropriately selected.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a field effect transistor using a comb structure according to a conventional technique.

FIG. 2 is a plan view showing the structure of the field effect transistor according to the first embodiment of the present invention.

FIG. 3 is a plan view showing the structure of a field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a plan view showing the structure of a field effect transistor according to a third embodiment of the present invention.

[Explanation of symbols]

 10 semiconductor substrate 11 input side 12 output side 20 gate extraction region 30 gate electrode 33 first electrode finger 34 second electrode finger 35 first gate bus 36 second gate bus 40 active layer 50 source electrode 51 via hole 60 drain electrode 70 drain extraction region

Claims (1)

[Claims] 1. A rectangular semiconductor substrate, a gate electrode, a drain electrode, a source electrode provided on one main surface of the semiconductor substrate, and a plurality of lead regions respectively connected to the gate electrode and the drain electrode. In the field effect transistor including: (a) one of the extraction regions is provided in the vicinity of one side of the semiconductor substrate with a width narrower than the length of the side, and (b) the other extraction region is formed on the one side. And (c) the gate electrode extends in a direction substantially perpendicular to the one side and extends from the one lead region to the other side. A first electrode finger group composed of a plurality of electrode fingers, and a plurality of electrode fingers extending from the vicinity of the one side where the one lead-out region is not provided to the other side. And a second electrode finger group constituted by (d) the source electrode and the drain electrode are provided adjacent to the gate electrode finger, respectively.