JPH04274613A - Chattering elimination circuit - Google Patents

Abstract

PURPOSE:To realize the chattering elimination circuit without dispersion in a delay time by providing an exclusive OR gate, a counter, a FF, a clock generating circuit and a counter initial value input section to the chattering elimination circuit. CONSTITUTION:When an input signal 11 and an inverted output signal 12 are the same, an exclusive OR gate 1 outputs an H level reset signal 13. When the reset signal 13 is logical H, an initial value 'n' is given to a counter 2 by an initial value setting input signal 15. When the input signal 11 changes to logic L and the reset signal 13 goes to L, the count is counted-down by a clock signal 14 from a clock generating circuit 14. When the count changes from 'n' to '0' and the clock signal 14 goes to 'L', a pulse outputted. An FF 3 inverts an output signal 17 by the pulse.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chattering elimination circuit, and more particularly to a chattering elimination circuit used in a digital logic circuit.

0002

[Prior Art] Conventionally, in circuits using relay contacts or switches, chattering caused by opening and closing of the contacts has a negative electrical effect on other circuit parts.
Chattering generated from relay contacts or switches is removed by a chattering circuit, and this conventional chattering removal circuit is shown in FIG.

In FIG. 3, a driver is used for the input gate 21 that is not affected by an integrating circuit made up of a resistor 22 and a capacitor 23. And resistance 22
Chattering contained in the input signal is removed by an integrating circuit including a capacitor 23 and a Schmitt trigger gate 24.

Further, the signal waveforms of each part of the above circuit are as shown in FIG. This shows that chattering occurs when the input signal 31 is turned on and off, and the input gate 2
Although the polarity of the signal 32 outputted from 1 is also reversed, the chattering during on/off remains unchanged. but,
The waveform of the signal 33 output from the integrating circuit including the resistor 22 and the capacitor 23 is integrated to reduce the chattering portion.

[0005] And Schmitt trigger gate 24
The waveform of the output signal 34 is shaped by the threshold values S1 and S2, but a delay time occurs with respect to the input signal.

[0006]

[Problems to be Solved by the Invention] The conventional chattering removal circuit described above uses an analog integration circuit using a resistor and a capacitor, so the integration time is unstable due to variations in the integration constant, and the delay time varies depending on the circuit. Because of this variation, when used in a plurality of parallel digital input circuits, it has the disadvantage of adversely affecting the operation of the digital circuit.

An object of the present invention is to provide a chattering removal circuit with no variation in delay time.

[0008]

[Means for Solving the Problems] A chattering removal circuit according to a first aspect of the invention includes (A) an input signal and an inverted output signal which is an inverted signal of an output signal, and a value of the input signal and an output signal. (B) An exclusive OR gate that outputs a reset signal whose logic value is "high level" when the value of the inverted signal is the same as the value of the inverted signal; (B) When the logic value of the reset signal is "high level," An initial value "n" (n is a positive integer) is given via the initial value input terminal by the initial value setting input signal, and the logic value of the input signal is set to "low level".
and the logic value of the reset signal becomes “low level”.
, the count value is incremented by "-1" at the rising edge of the supplied clock signal for counting, and when the count value becomes "0", the logical value of the clock signal for counting is (C) a flip-flop that inverts the values of the output signal and the inverted output signal at the falling edge of the clock pulse output from the counter;
D) a clock generation circuit that supplies a clock signal with a period t to the counter as the clock signal for counting;
(E) Initial value “” via the initial value input terminal of the counter.
and a counter initial value input section that outputs an initial value setting input signal to the counter in order to provide the counter with an initial value of n''.

[0009] Furthermore, in the chattering removal circuit of the second invention, in the chattering removal circuit of the first invention, the "high level" is a "low level" and the "low level" is a "high level". It is configured as follows.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a chattering removal circuit according to the present invention. Further, FIG. 2 is a diagram showing signal waveforms of various parts in the chattering removal circuit of FIG. 1.

The chattering removal circuit of this embodiment is shown in FIG.
As shown in , when the input signal 11 and the inverted output signal 12 are added and the value of the input signal 11 and the value of the inverted output signal 12 are the same value, a reset signal with a logic value of "high level" is output. When the logic value of the exclusive OR gate 1 and the reset signal 13 is "high level", the input initial value setting input signal 15 sets the initial value "" through the initial value input terminal.
n" (n is a positive integer, here n = 4) is given, and when the logic value of the reset signal 13 is "low level", the count value is determined at the rising edge of the supplied counting clock signal 14. is incremented by “-1”, and the count value becomes “
0", and the logic value of the clock signal 14 becomes "low level", the counter 2 outputs the clock pulse. At the falling edge of the clock pulse output from the counter 2, the output signal 17 and the inverted output signal are output. a flip-flop 3 for inverting the value of 12; a clock generation circuit 4 for supplying a clock signal of period t to the counter 2 as a clock signal 14; , a counter initial value input section 5 that outputs an initial value setting input signal to the counter 2.

Next, the operation will be explained.

In FIG. 1, when the logic value of the input signal 11 applied to the exclusive OR gate 1 is "high level", the value of the inverted output signal 12 is "low level", and the exclusive OR gate 1 When the values of the input signal 11 and the inverted output signal 12 applied to the counter 2 are different, a reset signal 13 having a logic value of "high level" is output to the counter 2.

When the reset signal 13 becomes "high level", the counter 2 receives a counter initial value setting input signal 15 outputted from the counter initial value input section 5 and sets the counter 2 through the "initial value" input terminal. An initial value "4" is given as an initial value. In the case of FIG. 2, the case where the value of n is "4" is explained.

Next, when the logic value of the input signal 11 changes to "low level", the value of the inverted output signal 12 is "low level", so the input signal 11 applied to the exclusive OR gate 1 and The value of the inverted output signal 12 becomes the same value,
Reset signal 1 whose logic value is “low level” to counter 2
3 is output.

On the other hand, from the clock generation circuit 4, the period t
The clock signal 14 is applied to the counter 2 as the clock signal 14 for counting, but when the reset signal 13 is at "low level", the counter 2 receives the signal every rising edge of the clock signal 14 output from the clock generation circuit 4. Then, the count value of the counter 2 is incremented by "-1", and the value of the counter 2 becomes "0".

When the value of the counter 2 becomes "0", the clock signal 14 supplied to the counter 2 becomes
When it becomes “low level”, carrier signal 1 of counter 2
A clock pulse is generated as 6. At the falling edge of the clock pulse output from counter 2, a flip occurs.
The flop 3 inverts the values of the output signal 17 and the inverted output signal 12.

This time, when the logic value of the input signal 11 applied to the exclusive OR gate 1 is at a "low level", the value of the inverted output signal 12 is at a "high level", and the input signal 11 is applied to the exclusive OR gate 1. A reset signal 13 having a logic value of "high level" is output to the counter 2. Therefore, since the reset signal 13 has become "high level", the counter 2 is reset again via the "initial value" input terminal by the counter initial value setting input signal 15 output from the counter initial value input section 5. An initial value "4" is given as the initial value. Next, when the logical value of the input signal 11 changes to "high level", the value of the inverted output signal 12 is "high level", so the input signal 11 and the inverted output signal 12 are added to the exclusive OR gate 1. become the same value, and a reset signal 13 with a logic value of "low level" is output to the counter 2. Therefore, the counter 2 starts counting again every time the clock signal 14 rises.

In this way, each time the input signal is inverted,
Time T to count from initial value “4” to “0” (T=
4t) and the output signal 17 is inverted. That is, an output signal 17 having the same waveform as the input signal 11 and delayed by the time T from the input signal 11 is obtained.

Now, if chattering occurs between point A and point B shown in FIG. 2, the count value is "0".
The reset signal 13 becomes “
Each time, the initial value “4” is added to counter 2.
” is given, the count value does not become “0” while chattering continues, and no clock pulse is generated in carrier signal 16. Therefore, while chattering continues, output signal 17 is inverted. does not occur, and the output signal 17 is output after time T has passed since the chattering has disappeared.
is reversed. That is, the waveform is the same as the input signal 11,
An output signal 17 is obtained that is delayed by the chattering duration and time T from the input signal.

Further, even when chattering occurs between points C and D shown in FIG. 2, the same operation as described above is performed.

[0023] In this way, by performing the above operation, chattering that occurs at the rise and fall of the input signal 11 can be removed.

Note that even if the logical values in the above explanation are switched between "high level" and "low level", a chattering removal circuit that can perform the same operation can be constructed.

Furthermore, in the above explanation, the counter 2 was described as performing a countdown operation based on a clock signal, but it may also be configured to perform a countup operation.

[0026]

As explained above, the chattering removal circuit of the present invention is composed of a digital logic circuit, and the delay time can be reduced by setting the delay time value based on the period of the clock signal and the initial value of the counter. This has the effect of eliminating variations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a chattering removal circuit of the present invention.

FIG. 2 is a diagram showing signal waveforms at various parts in the chattering removal circuit of this embodiment.

FIG. 3 is a block diagram of a conventional chattering removal circuit.

FIG. 4 is a diagram showing signal waveforms at various parts in the chattering removal circuit of FIG. 3;

[Explanation of symbols]

1 Exclusive OR gate 2 Counter 3 Flip-flop 4 Clock generation circuit 5 Counter initial value input section 11 Input signal 12 Inverted output signal 13 Reset signal 14 Clock signal 15 Counter initial value setting input signal 16
Counter carrier signal 17 Output signal 21 Input gate 22 Resistor 23 Capacitor 24 Schmitt trigger gate 31
Input signal 32 Integrating circuit input signal 33 Integrating circuit output signal 34 Output signal

Claims (2)

[Claims] Claim 1: (A) When an input signal and an inverted output signal, which is an inverted signal of an output signal, are added, and the value of the input signal and the value of the inverted output signal are the same value, a logical value is obtained. (B) When the logic value of the reset signal is "high level," the gate is outputted via the initial value input terminal by the input initial value setting input signal. Initial value “n” (n is a positive integer)
is given, and when the logic value of the input signal changes to "low level" and the logic value of the reset signal becomes "low level", the count value changes at the rising edge of the supplied counting clock signal. When the count value reaches "0" and the logical value of the clock signal for counting becomes "low level", a counter outputs a clock pulse; (C) the counter outputs a clock pulse; a flip-flop that inverts the values of the output signal and the inverted output signal at the falling edge of the output clock pulse;
) A clock generation circuit that supplies a clock signal with a period t to the counter as the clock signal for counting, (
E) The initial value “n” is input via the initial value input terminal of the counter.
a counter initial value input section that outputs an initial value setting input signal to the counter in order to provide a chattering removal circuit. 2. The chattering removal circuit according to claim 1, wherein the "high level" is a "low level" and the "low level" is a "high level".