JPH04217370A - Gate electrode of thin film transistor and manufacture thereof - Google Patents
Gate electrode of thin film transistor and manufacture thereofInfo
- Publication number
- JPH04217370A JPH04217370A JP40353790A JP40353790A JPH04217370A JP H04217370 A JPH04217370 A JP H04217370A JP 40353790 A JP40353790 A JP 40353790A JP 40353790 A JP40353790 A JP 40353790A JP H04217370 A JPH04217370 A JP H04217370A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- layer
- film transistor
- thin film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 239000010949 copper Substances 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052802 copper Inorganic materials 0.000 claims abstract description 14
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 11
- 239000011733 molybdenum Substances 0.000 claims abstract description 11
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011651 chromium Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 5
- 238000001039 wet etching Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000009835 boiling Methods 0.000 description 2
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910002651 NO3 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は薄膜トランジスタのゲ−
ト電極およびその製造方法に関する。[Industrial Application Field] The present invention relates to a thin film transistor gate.
The present invention relates to an electrode and a method for manufacturing the same.
【０００２】0002
【従来の技術】薄膜トランジスタをアレイ状に形成した
もの（以下、薄膜トランジスタアレイという。）では、
ゲ−ト電極およびゲ−ト配線の抵抗値を低減するために
ゲ−ト電極およびゲ−ト配線に銅（Ｃｕ ）を用いたも
のがある。通常は、銅層を保護するために、銅層の上下
にタンタル（Ｔａ ）層を形成し、Ｔａ ／Ｃｕ ／Ｔ
ａ の３層構造としている。[Prior Art] In an array of thin film transistors (hereinafter referred to as a thin film transistor array),
Some devices use copper (Cu) for the gate electrode and gate wiring in order to reduce the resistance value of the gate electrode and gate wiring. Usually, tantalum (Ta) layers are formed above and below the copper layer to protect the copper layer, and Ta/Cu/T
It has a three-layer structure.
【０００３】0003
【発明が解決しようとする課題】しかしながら、上記従
来のゲ−ト電極構造では、タンタル層をドライエッチン
グ法を用いてエッチングしなければならず、製造コスト
が高くなるという問題点があった。However, the conventional gate electrode structure described above has the problem that the tantalum layer must be etched using a dry etching method, which increases manufacturing costs.
【０００４】本発明の目的は、ゲ−ト電極を３層構造に
しても安価に製造可能な薄膜トランジスタのゲ−ト電極
およびその製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a gate electrode for a thin film transistor that can be manufactured at low cost even if the gate electrode has a three-layer structure, and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明における薄膜トラ
ンジスタのゲ−ト電極は、銅層上にモリブデン（Ｍｏ）
やクロム（Ｃｒ ）等のウエットエッチングが容易な金
属を主成分とする金属層を形成したものである。[Means for Solving the Problems] The gate electrode of the thin film transistor in the present invention is made of molybdenum (Mo) on a copper layer.
A metal layer whose main component is a metal that can be easily wet-etched, such as chromium (Cr) or the like, is formed.
【０００６】また、上記薄膜トランジスタのゲ−ト電極
の製造方法は、３層構造のゲ−ト電極を形成する際に、
フォトレジスト等のマスク層をマスクとして、銅層およ
び銅層上の金属層を同一のエッチング液を用いてエッチ
ングするものである。[0006] Furthermore, in the method for manufacturing a gate electrode of a thin film transistor, when forming a gate electrode having a three-layer structure,
Using a mask layer such as photoresist as a mask, the copper layer and the metal layer on the copper layer are etched using the same etching solution.
【０００７】[0007]
【実施例】図１〜図３は、薄膜トランジスタアレイのゲ
−ト電極およびゲ−ト配線の製造工程を示した断面図で
ある。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are cross-sectional views showing the manufacturing process of gate electrodes and gate wiring of a thin film transistor array.
【０００８】絶縁基板１１にはガラスが用いられる。第
１金属層１２にはチタン（Ｔｉ ）層が用いられ、その
層厚は５０〜１００ｎｍである。第２金属層１３には銅
（Ｃｕ）層が用いられ、その層厚は２００ｎｍである。
第３金属層１４にはモリブデン（Ｍｏ ）層またはクロ
ム（Ｃｒ ）層が用いられ、その層厚は５０ｎｍである
。Glass is used for the insulating substrate 11. A titanium (Ti) layer is used for the first metal layer 12, and the layer thickness is 50 to 100 nm. A copper (Cu) layer is used for the second metal layer 13, and the layer thickness is 200 nm. A molybdenum (Mo 2 ) layer or a chromium (Cr 2 ) layer is used for the third metal layer 14, and the layer thickness is 50 nm.
【０００９】つぎに、図１〜図３を用いて製造工程の説
明をする。Next, the manufacturing process will be explained using FIGS. 1 to 3.
【００１０】
（Ａ）絶縁基板１１上に、第１金属層１２となるチタン
層をスパッタリング法で形成する。チタン層はガラス基
板１１に対する付着力が強く、膜剥がれが生じ難い。引
き続き第１金属層１２上に、第２金属層１３となる銅層
をスパッタリング法で形成する。引き続き第２金属１３
上に、第３金属層１４となるモリブデン層またはクロム
層をスパッタリング法で形成する。第３金属層１４上に
、ゲ−ト電極およびゲ−ト配線の平面形状を有するマス
ク層１５を、フォトレジストを用いて形成する（図１参
照）。(A) A titanium layer that will become the first metal layer 12 is formed on the insulating substrate 11 by sputtering. The titanium layer has strong adhesion to the glass substrate 11 and is unlikely to peel off. Subsequently, a copper layer that will become the second metal layer 13 is formed on the first metal layer 12 by sputtering. Continue with the second metal 13
A molybdenum layer or a chromium layer, which will become the third metal layer 14, is formed thereon by sputtering. A mask layer 15 having a planar shape of a gate electrode and a gate wiring is formed on the third metal layer 14 using a photoresist (see FIG. 1).
【００１１】
（Ｂ）マスク層１５をマスクとして、第１金属層１２、
第２金属層１３および第３金属層１４をエッチングする
。第３金属層１４および第２金属層１３は同一のウエッ
トエッチング液を用いてウエットエッチングする。エッ
チング液には、硝酸＋酢酸＋硝酸第２セリウムアンモニ
ウム（Ｃｅ （ＮＨ４ ）２ （ＮＯ３ ）６ ）の混
合水溶液を用いる。なお、第３金属層１４としてモリブ
デン層を用いる場合には、必ずしも硝酸を混合する必要
はない。
第３金属層１４および第２金属層１３の側壁をテ−パ−
状に形成するには、エッチング液に含まれる酸化剤（酢
酸、硝酸）の混合割合を適宜選定し、第３金属層１４の
エッチングレ−トを第２金属層１３のエッチングレ−ト
よりも大にすればよい。第３金属層１４および第２金属
層１３をエッチング後、希フッ酸ボイルまたはリン酸水
溶液ボイルにより第１金属層１２をエッチングする。な
お、ＣＦ４ ガス等を用いたドライエッチング法で第１
金属層１２をエッチングしてもよい（図２参照）。(B) Using the mask layer 15 as a mask, the first metal layer 12,
The second metal layer 13 and the third metal layer 14 are etched. The third metal layer 14 and the second metal layer 13 are wet-etched using the same wet etching solution. As the etching solution, a mixed aqueous solution of nitric acid + acetic acid + ceric ammonium nitrate (Ce (NH4) 2 (NO3) 6 ) is used. Note that when a molybdenum layer is used as the third metal layer 14, it is not necessarily necessary to mix nitric acid. The side walls of the third metal layer 14 and the second metal layer 13 are tapered.
In order to form the third metal layer 14, the mixing ratio of the oxidizing agent (acetic acid, nitric acid) contained in the etching solution is appropriately selected so that the etching rate of the third metal layer 14 is higher than that of the second metal layer 13. Just make it bigger. After etching the third metal layer 14 and the second metal layer 13, the first metal layer 12 is etched using dilute hydrofluoric acid boiling or phosphoric acid aqueous solution boiling. Note that the first step is performed using a dry etching method using CF4 gas, etc.
The metal layer 12 may also be etched (see FIG. 2).
【００１２】
（Ｃ）マスク層１５を除去し、テ−パ−形状を有するゲ
−ト電極およびゲ−ト配線が形成される（図３参照）。(C) Mask layer 15 is removed, and a gate electrode and gate wiring having a tapered shape are formed (see FIG. 3).
【００１３】図４は、薄膜トランジスタアレイにおける
薄膜トランジスタの断面図である。FIG. 4 is a cross-sectional view of a thin film transistor in a thin film transistor array.
【００１４】この薄膜トランジスタは、図１〜図３の工
程でゲ−ト電極およびゲ−ト配線を形成した後、ゲ−ト
絶縁層となる窒化シリコン層１５（層厚１００〜１５０
ｎｍ）および酸化シリコン層１６（層厚４００〜５００
ｎｍ）、アモルファスシリコン層１７、ｎ＋ アモルフ
ァスシリコン層１８、ソ−ス電極およびドレイン電極と
なるＩＴＯ（インジウム ティン オキサイド）層
１９を形成することにより作成される。This thin film transistor is manufactured by forming a silicon nitride layer 15 (thickness: 100 to 150 mm) to serve as a gate insulating layer after forming a gate electrode and a gate wiring in the steps shown in FIGS. 1 to 3.
nm) and silicon oxide layer 16 (layer thickness 400-500 nm)
nm), an amorphous silicon layer 17, an n+ amorphous silicon layer 18, and an ITO (indium tin oxide) layer 19 serving as a source electrode and a drain electrode.
【００１５】図５は、薄膜トランジスタアレイにおける
ゲ−ト配線の終端部付近を示した断面図であり、図４に
示した薄膜トランジスタの形成と同時に作成されるもの
である。したがって、窒化シリコン層１５、酸化シリコ
ン層１６およびＩＴＯ層１９は、図４に同一番号を付し
たものと同時に形成されるものである。なお、図５に示
したＩＴＯ層１９は、ゲ−ト配線を外部回路と接続する
ための接続端子となるものである。FIG. 5 is a cross-sectional view showing the vicinity of the terminal end of the gate wiring in the thin film transistor array, which is produced at the same time as the formation of the thin film transistor shown in FIG. Therefore, silicon nitride layer 15, silicon oxide layer 16, and ITO layer 19 are formed at the same time as those labeled with the same numbers in FIG. The ITO layer 19 shown in FIG. 5 serves as a connection terminal for connecting the gate wiring to an external circuit.
【００１６】以上述べた実施例では、第３金属層１４を
形成する金属をモリブデンまたはクロムとしたが、他の
金属を主成分としたものでもよい。ゲ−ト電極に関して
いえば、ウエットエッチングが容易な金属を主成分とす
るものであればよい。特に、第３金属層（銅層）１４と
第２金属層１３とを同一のウエットエッチング液を用い
てエッチングできるものが好ましい。また、ゲ−ト配線
に関していえば、ＩＴＯ層１９等を用いた導電性の接続
層に対して、良好なオ−ミックコンタクトが得られる金
属を主成分とするものであればよい。In the embodiments described above, the metal forming the third metal layer 14 is molybdenum or chromium, but it may be made of other metals as the main component. As for the gate electrode, it may be one whose main component is a metal that can be easily wet-etched. In particular, it is preferable that the third metal layer (copper layer) 14 and the second metal layer 13 can be etched using the same wet etching solution. As for the gate wiring, any material may be used as long as the main component is a metal that can provide good ohmic contact with the conductive connection layer using the ITO layer 19 or the like.
【００１７】[0017]
【発明の効果】本発明では、銅層上にモリブデン（Ｍｏ
）やクロム（Ｃｒ ）等のウエットエッチングが容易
な金属を主成分とする金属層を形成したため、ゲ−ト電
極を３層構造にしても安価に製造可能な薄膜トランジス
タのゲ−ト電極が形成できる。また、適当なエッチング
液を選択することにより、銅層および銅層上の金属層を
同一のエッチング液を用いてエッチングすることができ
る。Effects of the Invention In the present invention, molybdenum (Mo
) and chromium (Cr), which are easy to wet-etch, the gate electrode of a thin film transistor can be formed at low cost even if the gate electrode has a three-layer structure. . Furthermore, by selecting an appropriate etching solution, the copper layer and the metal layer on the copper layer can be etched using the same etching solution.
【図１】本発明に係わる実施例であり、薄膜トランジス
タアレイのゲ−ト電極およびゲ−ト配線の製造工程を示
した断面図である。FIG. 1 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.
【図２】本発明に係わる実施例であり、薄膜トランジス
タアレイのゲ−ト電極およびゲ−ト配線の製造工程を示
した断面図である。FIG. 2 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.
【図３】本発明に係わる実施例であり、薄膜トランジス
タアレイのゲ−ト電極およびゲ−ト配線の製造工程を示
した断面図である。FIG. 3 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.
【図４】本発明に係わる実施例であり、薄膜トランジス
タアレイにおける薄膜トランジスタの断面図である。FIG. 4 is an embodiment of the present invention, and is a cross-sectional view of a thin film transistor in a thin film transistor array.
【図５】本発明に係わる実施例であり、薄膜トランジス
タアレイにおけるゲ−ト配線の終端部付近を示した断面
図である。FIG. 5 is an embodiment of the present invention, and is a cross-sectional view showing the vicinity of the terminal end of a gate wiring in a thin film transistor array.
１１……絶縁基板 １２……第１金属層 １３……第２金属層 １４……第３金属層 11...Insulating substrate 12...first metal layer 13...Second metal layer 14...Third metal layer
Claims (5)
金属層と、上記第１金属層上に上記第１金属層と略同一
形状で形成され、銅（Ｃｕ ）を主成分とする第２金属
層と、上記第２金属層上に上記第２金属層と略同一形状
で形成され、モリブデン（Ｍｏ ）やクロム（Ｃｒ ）
等のウエットエッチングが容易な金属を主成分とする第
３金属層とからなる薄膜トランジスタのゲ−ト電極。Claim 1: A first plate formed on the main surface side of an insulating substrate.
a metal layer, a second metal layer formed on the first metal layer in substantially the same shape as the first metal layer and mainly containing copper (Cu), and a second metal layer on the second metal layer, It is formed in approximately the same shape as the layer, and contains molybdenum (Mo) and chromium (Cr).
A gate electrode of a thin film transistor comprising a third metal layer whose main component is a metal that is easy to wet-etch.
）またはクロム（Ｃｒ ）を主成分とした材料で構成さ
れている請求項１に記載の薄膜トランジスタのゲ−ト電
極。2. The third metal layer is molybdenum (Mo
) or chromium (Cr) as a main component.
積し、上記第１金属層上に銅（Ｃｕ ）を主成分とする
第２金属層を堆積し、上記第１金属層上にモリブデン（
Ｍｏ ）やクロム（Ｃｒ ）等のウエットエッチングが
容易な金属を主成分とする第３金属層を堆積する工程と
、フォトレジスト等のマスク層をマスクとして、上記第
３金属層および上記第２金属層を同一のエッチング液を
用いてエッチングする工程と上記マスク層をマスクとし
て、上記第１金属層をエッチングする工程とからなる薄
膜トランジスタのゲ−ト電極の製造方法。3. Depositing a first metal layer on the main surface side of the insulating substrate, depositing a second metal layer containing copper (Cu) as a main component on the first metal layer, and depositing a second metal layer on the first metal layer. Molybdenum (
A step of depositing a third metal layer mainly composed of a metal that is easy to wet-etch, such as Mo) or chromium (Cr), and a step of depositing the third metal layer and the second metal using a mask layer such as photoresist as a mask. A method for manufacturing a gate electrode of a thin film transistor, comprising the steps of etching the layers using the same etching solution and etching the first metal layer using the mask layer as a mask.
対するエッチングレ−トは、上記第２金属層の上記エッ
チング液に対するエッチングレ−トよりも大である請求
項３に記載の薄膜トランジスタのゲ−ト電極の製造方法
。4. The gate of the thin film transistor according to claim 3, wherein the etching rate of the third metal layer with the etching solution is higher than the etching rate of the second metal layer with the etching solution. A method for manufacturing an electrode.
）またはクロム（Ｃｒ ）を主成分とした材料で構成さ
れている請求項３に記載の薄膜トランジスタのゲ−ト電
極の製造方法。5. The third metal layer is made of molybdenum (Mo
) or chromium (Cr) as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40353790A JPH04217370A (en) | 1990-12-19 | 1990-12-19 | Gate electrode of thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40353790A JPH04217370A (en) | 1990-12-19 | 1990-12-19 | Gate electrode of thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04217370A true JPH04217370A (en) | 1992-08-07 |
Family
ID=18513269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40353790A Withdrawn JPH04217370A (en) | 1990-12-19 | 1990-12-19 | Gate electrode of thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04217370A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044439A (en) * | 1999-07-28 | 2001-02-16 | Nec Corp | Transistor and manufacture thereof |
| KR100303347B1 (en) * | 1998-06-23 | 2001-11-22 | 박종섭 | Manufacturing Method of Thin Film Transistor |
| KR100430950B1 (en) * | 1998-09-01 | 2004-06-16 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and its manufacturing method |
| KR100670982B1 (en) * | 2000-02-10 | 2007-01-17 | 샤프 가부시키가이샤 | Thin film transistor and method for fabricating the same |
| KR20140070344A (en) * | 2012-11-30 | 2014-06-10 | 삼성전자주식회사 | Semiconductor material, transistor including semiconductor material and electronic device including transistor |
| KR20180098647A (en) * | 2016-02-01 | 2018-09-04 | 가부시키가이샤 리코 | Field effect transistor, method of manufacturing the same, display element, display device, and system |
| CN108573980A (en) * | 2017-03-09 | 2018-09-25 | 群创光电股份有限公司 | Conductor structure and panel device |
-
1990
- 1990-12-19 JP JP40353790A patent/JPH04217370A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100303347B1 (en) * | 1998-06-23 | 2001-11-22 | 박종섭 | Manufacturing Method of Thin Film Transistor |
| KR100430950B1 (en) * | 1998-09-01 | 2004-06-16 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and its manufacturing method |
| JP2001044439A (en) * | 1999-07-28 | 2001-02-16 | Nec Corp | Transistor and manufacture thereof |
| KR100670982B1 (en) * | 2000-02-10 | 2007-01-17 | 샤프 가부시키가이샤 | Thin film transistor and method for fabricating the same |
| KR20140070344A (en) * | 2012-11-30 | 2014-06-10 | 삼성전자주식회사 | Semiconductor material, transistor including semiconductor material and electronic device including transistor |
| KR20180098647A (en) * | 2016-02-01 | 2018-09-04 | 가부시키가이샤 리코 | Field effect transistor, method of manufacturing the same, display element, display device, and system |
| CN108496243A (en) * | 2016-02-01 | 2018-09-04 | 株式会社理光 | Field-effect transistor, its manufacturing method, display element, display equipment and system |
| US10748784B2 (en) | 2016-02-01 | 2020-08-18 | Ricoh Company, Ltd. | Field effect transistor, method for manufacturing same, display element, display device, and system |
| CN108573980A (en) * | 2017-03-09 | 2018-09-25 | 群创光电股份有限公司 | Conductor structure and panel device |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980312 |