JPH04207040A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a potential barrier from being lowered by a method wherein an impurity layer to which impurities to be used as acceptors have been added when carriers are composed of electrons or to which impurities to be used as donors have been added when carriers are composed of holes is inserted and formed in a semiconductor layer which is closest to a gate out of a plurality of semiconductor layers. CONSTITUTION:When a voltage is applied to a gate electrode 19, electrons excited from impurity atoms with which an n-type GaAs layer 7 has been doped are accumulated in a quantum well which is formed of an undoped AlGaAs layer 5, the n-type GaAs layer 7 and an undoped AlGaAs layer 9. Then, when a much higher voltage is applied to the gate electrode 9, much more electrons are accumulated in the heterointerface between the n-type GaAs layer 7 and the undoped AlGaAs layer 9, and a pseudo-Fermi level is increased. The potential barrier at the heterointerface between the n-type AlGaAs layer 7 and the undoped AlGaAs layer 9 becomes effectively low and the width W of the undoped AlGaAs layer 9 becomes narrow. However, the width W becomes high and wide thanks to a delta doped layer 13 which has been inserted and formed in the undoped AlGaAs layer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to field effect transistors (FETs), and particularly to MIS type FETs having a superlattice.

(Prior Art) Technology for controlling the potential shape (energy band structure) of compound semiconductors is one of the important semiconductor device technologies for increasing the functionality and performance of devices. Generally, two methods can be considered as methods for controlling the energy band structure. That is, a method using a heterojunction and a method using implantation of impurity atoms.

The former method involves forming a junction using different types of semiconductors. However, in this method, since semiconductors having different lattice constants are generally bonded together, an interface level is generated at the bonding surface, which greatly disturbs the behavior of electrons, making it easy to cause deterioration of the device. As a result, a practical heterojunction is A IGaAS/GaA
s, InGaAs/A I InGaAs/InG
aAsP/InP or some pseudomorphic structures
) are limited to semiconductors.

An example of the latter method is to implant equal numbers of donor and acceptor impurity atoms on both sides of the junction interface. As a result, the doped interface dipole D I D (DopedInterface Di
pole), making it possible to control the effective potential barrier. Another example is Q U I D
(Quantum Interface Induc)
edDipole). This lowers the effective potential barrier by providing an ultra-thin monoatomic layer (δ-doped layer) made of donor atoms on the semiconductor with the smaller energy band gear lump among the semiconductors forming the heterojunction. That is what it is.

In recent years, DMT (Dope-chan) has been used as a semiconductor device manufactured by applying this method of implanting impurity atoms.
nel hetero MISFET5) with a superlattice called
al., ED-3y(2) (1987) 1448] is attracting attention because it is superior to the conventional GaAs MESFET.

A specific MT is a Schottky metal layer (upper layer)
/Undoped AllGaAs layer/n-doped GaAs layer/
An example is an undoped Ai)GaAs layer (lower layer).

NiT has the following characteristics.

First, the upper undoped A, pGaAs layer allows 2
Concentration of deep levels such as the DX center, which causes various types of unstable operation in dimensional electron FETs, is minimized. Furthermore, the breakdown voltage also increases.

Second, at high gate voltages, carriers mainly concentrate in the region of the heterointerface of the undoped A, 11GaAs layer/n-doped GaAs layer. Therefore, it is less susceptible to scattering of ionized impurities, and the screening effect and mobility are improved.

Third, this DMT supports high speed (5Gbit/S
) and low power consumption. Therefore, by using this DMT, DCFL-5 bit shift register, 31 stage DC
FL ring oscillator (4, sp s/ga te)
, laser drivers (100 bit/s), and other devices have been realized.

FIG. 7 is an energy band diagram immediately below the gate of this DMT. Figure 7(a) is OFF, Figure 7(b) is ON
It shows the time. As shown in FIG. 7(b), in the ON state, as the gate voltage V6 increases, CVa-Vc+→V
G2) Undoped ANGaAs layer (upper layer)/n-type GaA
The height of the potential barrier near the heterointerface (channel region) of the s-layer is reduced by being distorted.

Therefore, electrons accumulated at the hetero interface of the undoped AjlGaAs layer (upper layer)/n-type GaAs layer easily overcome this potential barrier and enter the gate.
There has been a problem in that electrical characteristics such as admittance deteriorate.

(Problem to be Solved by the Invention) As mentioned above, in a conventional MIS type FET having a superlattice, when the gate voltage increases, the potential barrier at the heterojunction interface (channel) becomes distorted and becomes lower as a result.
Therefore, there is a problem in that electrons within the channel easily enter the gate, resulting in a decrease in electrical characteristics.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor device that prevents a decrease in the potential barrier at a heterojunction interface due to an increase in gate voltage and has good electrical characteristics. It's about doing.

[Configuration of the Invention (Means for Solving the Problems) In order to achieve the above object, the semiconductor device of the present invention comprises:
In a semiconductor device in which carriers accumulated in a superlattice formed by heterojunctions of a plurality of semiconductor layers are controlled by a voltage applied to a gate, the carriers are transferred to a semiconductor layer closest to the gate among the plurality of semiconductor layers. In particular, this semiconductor device is characterized in that an impurity layer is inserted into which is added an impurity that becomes an acceptor when the carrier is a hole, or an impurity that becomes a donor when the carrier is a hole. a first compound semiconductor layer; a second compound semiconductor layer having a smaller energy bandgap than the first compound semiconductor layer containing an impurity heterojunctioned to the first compound semiconductor layer;
a third compound semiconductor layer having a larger energy bandgap than the second compound conductor layer heterojunctioned to the second compound semiconductor layer; and at least one pole inserted in the third compound semiconductor layer. It is characterized by having a superlattice with a thin impurity layer.

(Function) According to the semiconductor device of the present invention, an extremely thin impurity layer is inserted in the semiconductor layer closest to the gate among the semiconductor layers forming the electron storage layer. The effective potential barrier at the location increases. Therefore, even if the gate voltage becomes high, electrons cannot easily overcome this potential barrier. As a result, it becomes possible to control the movement of electrons in the film thickness direction, and it is possible to prevent electrons from entering the gate, thereby preventing deterioration of the element and deterioration of electrical characteristics.

(Example) Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a sectional view of a MISFET according to a first embodiment of the present invention.

A buffer layer 3 made of undoped GaAs and having a thickness of about 500 nm is provided on a semi-insulating substrate 1 made of GaAs to adjust the crystallinity. This buffer layer 3
On top is undoped Al)GaA with a thickness of about 20 nm.
An s layer 5 is provided. This undoped AlGaAs
On the layer 5 is an n-type GaAs layer 7 with a Si concentration of about 1X1018 cm-3 and a thickness of about 20 nm. Thickness approx. 25nm
undoped AllGaAs layer 9. An n-type GaAs layer 11 having a thickness of about 5 nm is sequentially provided. Furthermore, a δ-doped layer 13 is inserted into the undoped AlGaAs layer 9 and serves as an acceptor. This δ-doped layer 13 is made of carbon atoms, and each atom has 1 to 5×101
Contains ions of about 2 cm-2. Source electrode 15. The drain electrode 17 and the gate electrode 19 are the n-type GaAs layer 11
are arranged in a predetermined relationship above.

FIGS. 5(a) to (c) show the MIS configured in this way.
An energy band diagram of PET is shown.

Figure (a) shows the conduction band E when the gate voltage is zero.
c and the Fermi level EF are shown. A low bandgap n-type GaAs layer 7 is sandwiched between high bandgap undoped AllGaAs layers 5 and 9. For this reason, a quantum well is formed in the GaAs layer 5.

Moreover, undoped Al1GaAs on the n-type GaAs layer 7
Since the δ-doped layer 13 is provided in the layer 9, the δ-doped layer 13 and the undoped Al1GaAs layer 5/
A dipole moment is induced between the n-type GaAs layer 7 and the interface. This induced dipole moment is the n-type G
This leads to an effective increase in the potential barrier at the heterointerface of the aAs layer 7/and-coupled ApGaAs layer 9. That is, the energy Ec at the lower end of the conduction band at the position where the δ-doped layer 13 is inserted increases in a spike-like manner.

Next, as shown in the same figure (b) (hereinafter, Fermi level EP is labor-saving), when a voltage is applied to the gate electrode 19,
As the gate voltage increases, electrons excited from the impurity atoms doped in the n-type GaAs layer 7
It is accumulated in the quantum well formed by the 1GaAs layer 5/n-type ANGaAs layer 7/undoped AIGaAS layer 9.

Next, as shown in the same figure (C), when a higher voltage is applied to one gate electrode, more electrons are generated at the heterointerface of the n-type GaAs layer 7/and-amp AρGaAs layer 9. As it accumulates, the suspected Fermi level increases. When the pseudo-Fermi level increases, the n-type A, 1JGaAS layer 7/
The potential barrier at the hetero interface of the undoped A, 9GaAs layer 9 is effectively lowered. That is, n-type AlGaA
The energy Ec at the lower end of the conduction band of the undoped AlGaAs layer 9 near the hetero interface of the s layer 7/and-doped AlGaAs layer 9 becomes low, and the undoped AlGaAs has an Ec higher than the energy level at which electrons are stored.
The width W of the layer 9 becomes narrower. However, undoped Al
The level of the conduction band EC of the undoped AlGaAs layer 9 of this embodiment due to the δ-doped layer 13 inserted in the 1GaAs layer 9 and the width W of the conduction band Ec of the undoped AlGaAs layer 9 which is higher than the energy level where electrons are stored are as follows. , respectively, are higher and wider than the conventional ones. For this reason,
As shown in FIG. 5(C), even if the voltage level applied to the gate electrode 19 reaches vt2 shown in FIG. The generation of electrons penetrating the transverse n-type GaAs layer 11 can be prevented.

In this way, the MISPET of this example can prevent electrons from entering the gate electrode at high gate voltages, so the safe range of the voltage that can be applied to the gate electrode 19 is widened, and as a result, more electrons can be transferred to the n-type GaAs layer. Since it is accumulated at the hetero interface of the 7/and-p Aj7 GaAs layer 9, electrical characteristics such as drain current are improved.

Note that the mouth-shaped GaAs layer 7/undoped A according to this embodiment
, the effective increase in the potential barrier at the hetero interface of the QGaAs layer 9 is approximately 50 to 150 mV when the δBe 1 layer 13 is inserted into the undoped AlGaAs layer 9, which is approximately 5 to 19 nm away from the hetero interface. It is. Also,
When a logic circuit such as a DCFL circuit is constructed using the MISFET of this embodiment, the noise margin becomes large, so that the reliability of the circuit can be improved.

FIG. 2 shows a sectional view of a MISFET according to a second embodiment of the invention. Note that parts corresponding to the embodiment in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

This old 5FET differs from the previously described embodiment in that the second δBe1 layer 21 is inserted into the undoped AlGaAs layer 9. FIGS. 6(a) to 6(C) show energy band diagrams of the old 5FET configured in this manner. FIG. 5A shows the conduction band Ec and the Fermi level EF when no voltage is applied to the gate electrode 19. The undoped AlGaAs layer 9 corresponds to the position where the δ Be 1 layer 13.21 is inserted.
A spike-like increase in level is seen in the conduction band. Next, when a voltage is applied to the gate electrode 19, the same figure (b)
As shown in FIG.
Electrons are accumulated at the heterointerface of the GaAs layer 9. As in the previous embodiment, even if the gate voltage exceeds V12,
As shown in the figure (c), since the effective potential barrier at the hetero interface between the n-type GaAs layer 7 and the undoped AlGaAs layer 9 is high, electrons can cross this potential barrier and the undoped AlGaAs layer 9 There will be no inconvenience caused by the intrusion.

In this way, even with the old 5PET of this embodiment, the same effects as those of the previously described embodiment can be obtained.

In this case, compared to the optical example, the n-type GaAs layer 7/
Andip Aj! The effective level of the conduction band of the undoped AlGaAs layer 9 near the heterointerface of the GaAs layer 9 becomes higher, and the width W of the conduction band of the undoped AlGaAs layer 9, which is higher than the energy level at which electrons are stored, also becomes wider. Therefore, the safe range width of the voltage that can be applied to the gate electrode 19 also becomes wider.

FIG. 3 shows a cross-sectional view of an MfSFET according to a third embodiment of the present invention. This embodiment differs from the first embodiment in that a p-type GaAs layer 23 and an undoped GaAs layer 25 are sequentially provided between the buffer layer 3 and the undoped AlGaAs layer 5. In this example, p-type GaA
The impurity concentration of the s layer 23 is 3×10”, and its thickness is 20 nm.
I made it to the extent.

Further, the thickness of the undoped GaAs layer 25 is about 10 nm.

With such a configuration, not only the same effects as in the first embodiment can be obtained, but also the short channel effect is suppressed by the p-type GaAs layer 23, and the undoped GaAs
The p-type GaAs layer 2 generated in the manufacturing process by the s-layer 25
3 into the undoped GaAs layer 5, the memory effect, and the source.

Parasitic capacitance in the drain region can be prevented.

FIG. 4 shows a sectional view of an old 5FET according to a fourth embodiment of the present invention. This embodiment differs from the previously described third embodiment in that the second δBe 1 layer 21 is inserted into the undoped AlGaAs layer 9.

With such a configuration, not only the same effect as the third embodiment can be obtained, but also the effective level of the potential barrier at the hetero interface of the n-type GaAs layer 7/and-type AlGaAs layer 9. Since the voltage becomes higher, the safe range width of the voltage that can be applied to the gate electrode 19 becomes wider.

Note that the present invention is not limited to the embodiments described above. For example, in the above embodiments, a MISFET using three or more δ-doped layers was not described, but it goes without saying that similar effects can be obtained in this case as well. Further, in this case, even if the number of δ-doped layers increases, the essential layer thickness of the undoped AlGaAs layer 9 does not change. Therefore, deterioration in electrical properties such as deterioration in mutual conductance due to an increase in the thickness of the undoped AlGaAs layer 9 does not occur. In addition, AgGaA is used as the δ-doped layer.
Carbon atoms with a small diffusion coefficient were used in s, but this was done in order to prevent the atoms forming the δ-doped layer from diffusing as manufacturing of the MISFET in the example involves a high temperature (950°C) manufacturing process. be.

Therefore, it acts as an acceptor in AgGaAs,
Other atoms such as Be and Mg may be used as long as they have a small diffusion coefficient. Further, the quantum well may be constructed using p-type GaAs instead of n-type GaAs.

In this case, the carriers are holes, and the δ-doped layer may be doped with an impurity that acts as a toner. Furthermore, in the example, undoped Al)GaAs layer/n-type GaAs/
A quantum well was constructed with a heterojunction of an undoped AlGaAs layer, but 1 nGaAs/1 nGaAs/1 nG
It may be composed of aAs, Si/S iGe/S i, or a pseudomorphic semiconductor. In short, InGaAs/InGaA
A semiconductor material that can form a junction having the same energy band structure as the sP/InGaAs junction may be selected. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the semiconductor device of the present invention, the potential barrier that confines electrons is effectively increased by inserting an extremely thin impurity layer into the semiconductor layer that constitutes the layer that stores electrons. . As a result, it is possible to prevent the potential barrier from decreasing due to an increase in gate voltage, thereby widening the safe range of voltage that can be applied to the gate, and improving electrical characteristics such as drain current.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a MISFET according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a MISFET according to a second embodiment of the present invention.
A sectional view of T, FIG. 3 is an MI according to a third embodiment of the present invention.
4 is a cross-sectional view of the old 5FET according to the fourth embodiment of the present invention, and Figures 5 (a) to (C) are energy diagrams of the old 5PET according to the first embodiment of the present invention. Band diagrams, FIGS. 6(a) to (C) are energy band diagrams of the old 5PET according to the second embodiment of the present invention, and FIG. 7 is an energy band diagram of the conventional old 5PET.
It is an energy band diagram of FET. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 3... Buffer layer, 5...
Undoped AlGaAs layer, 7-n-type GaAs layer, 9.
...Undoped AlGaAs layer, 11...n-type GaA
s layer, 13...δ doped layer, 15... source electrode,
17...Drain electrode, 19...Gate electrode, 21
−=δ doped layer, 2:3・p-type GaAs layer, 25・
...Undoped QaAs layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3

Claims (1)

[Scope of Claims] A semiconductor device in which carriers accumulated in a superlattice formed by heterojunctions of a plurality of semiconductor layers are controlled by a voltage applied to a gate, comprising: a semiconductor closest to the gate among the plurality of semiconductor layers; 1. A semiconductor device characterized in that an impurity layer is inserted into the layer to which an impurity is added which becomes an acceptor when the carrier is an electron, or an impurity which becomes a donor when the carrier is a hole.