JP3053862B2 - Semiconductor device - Google Patents

Description

The present invention relates to a field effect transistor (FET), and more particularly to an MIS type FET having a superlattice.

(Prior Art) A technique for controlling the form of the potential (energy structure) in a compound semiconductor is one of the important semiconductor device technologies for multifunctional and high-performance devices. Generally, there are two methods for controlling the energy band structure. That is, a method using a heterojunction and a method using implantation of impurity atoms.

The former method is to form a junction with different kinds of semiconductors. However, in this method, generally, semiconductors having different lattice constants are bonded to each other, so that an interface level is generated at a bonding surface, so that the behavior of electrons is greatly disturbed and deterioration of the element is likely to occur. As a result, the practical heterojunctions are AlGaAS / GaAs, InGaAs / A
Limited to semiconductors with lInGaAs / InGaAsP / InP or some pseudomorphic structure.

An example of the latter method is to implant the same number of donor impurity atoms and acceptor impurity atoms on both sides of the junction interface. As a result, a doping interface dipole DID (Doped Interface Dipole) can be formed, and the effective potential barrier can be controlled. Another example is QUID (Quantum Interface Induced Dipole)
There is something. This is to reduce the effective potential barrier by providing an ultra-thin monoatomic layer (δ-doped layer) composed of donor atoms in the semiconductor with the smaller energy band gap among the semiconductors forming the heterojunction. is there.

In recent years, as a semiconductor device manufactured by applying the method based on the implantation of impurity atoms, a DMT (Dope-channel heter
o FETs with superlattices called MISFETs [H. Hida et
al., ED-3y (2) (1987) 1448] is a conventional GaAs MESFET.
It has attracted attention because it has better points.

As a specific DMT, Schottky metal layer (upper layer)
/ Undoped AlGaAs layer / n-doped GaAs layer / undoped AlGa
As layer (lower layer).

 Such a DMT has the following features.

First, the upper undoped AlGaAs layer minimizes the concentration of deep levels such as the DX center, which causes various kinds of unstable operations of the two-dimensional electronic FET. Also, the breakdown voltage increases.

Second, at high gate voltages, carriers are mainly concentrated in the region of the hetero-interface of the undoped AlGaAs layer / n-doped GaAs layer. Therefore, it is less susceptible to the scattering of ionized impurities, and the screening effect and the mobility are improved.

Third, the DMT has high speed (5 Gbit / s) and low power consumption. Therefore, by using this DMT, DCFL-5bi
t shift register, 31-stage DCFL ring oscillator (4.8ps / ga
te) and devices such as laser drivers (10 Gbit / s).

FIG. 7 is an energy band diagram immediately below the gate of the DMT. FIG. 7A shows an OFF state, and FIG. 7B shows an ON state. Figure 7 with the rise of the gate voltage V _G in the ON state as shown in _{(b) (V G = V} G1 → V G2) undoped
The potential barrier near the heterointerface (channel region) between the AlGaAs layer (upper layer) and the n-type GaAs layer is distorted and its height is reduced. For this reason, there is a problem in that electrons accumulated at the hetero interface between the undoped AlGaAs layer (upper layer) and the n-type GaAs layer easily cross this potential barrier and enter the gate, causing deterioration in electrical characteristics such as admittance. Was.

(Problems to be Solved by the Invention) As described above, in the conventional MIS type FET having a superlattice, when the gate voltage increases, the heterojunction interface (channel) increases.
Is distorted, resulting in a lower potential barrier. This causes a problem that electrons in the channel easily penetrate into the gate and lower the electrical characteristics.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device which prevents a potential barrier at a heterojunction interface from being lowered due to a rise in a gate voltage and has good electric characteristics. Is to do.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor device of the present invention is characterized in that a carrier accumulated in a superlattice formed by heterojunction of a plurality of semiconductor layers with each other is gated. In the semiconductor device controlled by the voltage applied to the semiconductor layer, the semiconductor layer closest to the gate among the plurality of semiconductor layers becomes an impurity serving as an acceptor when the carrier is an electron or a donor when the carrier is a hole. An impurity layer to which an impurity is added is inserted.

In particular, this semiconductor device has a first compound semiconductor layer formed on a substrate and a second compound semiconductor layer having an energy band gap smaller than that of the first compound semiconductor layer containing an impurity hetero-junctioned to the first compound semiconductor layer. And a second heterojunction with the second compound semiconductor layer.
A superlattice having a third compound semiconductor layer having an energy band gap larger than that of the compound semiconductor layer and at least one extremely thin impurity layer interposed in the third compound semiconductor layer. It is characterized by.

(Operation) According to the semiconductor device of the present invention, among the semiconductor layers forming the electron accumulation layer, the extremely thin impurity layer is inserted in the semiconductor layer closest to the gate, so that this impurity layer is inserted. The effective potential barrier at the position is higher. Therefore, even if the gate voltage increases, electrons cannot easily cross this potential barrier. As a result, it is possible to control the movement of electrons in the thickness direction, and to prevent the penetration of electrons into the gate and the like, thereby preventing deterioration of the element and deterioration of electrical characteristics.

(Example) Hereinafter, an example is described with reference to drawings.

FIG. 1 is a sectional view of a MISFET according to a first embodiment of the present invention.

On the semi-insulating substrate 1 made of GaAs, a buffer layer 3 made of undoped GaAs and having a thickness of about 500 nm is provided for adjusting the crystallinity. An undoped AlGaAs layer 5 having a thickness of about 20 nm is provided on the buffer layer 3. The undoped AlGaAs layer 5 has a Si concentration of about 1
× 10 ¹⁸ cm ^-3 , about 20 nm thick n-type GaAs layer 7, about 25 nm thick
An undoped AlGaAs layer 9 and an n-type GaAs layer 11 having a thickness of about 5 nm are sequentially provided. In the undoped AlGaAs layer 9, a δ-doped layer 13 serving as an acceptor is inserted.
The δ-doped layer 13 is made of carbon atoms and contains ions of about 1 to 5 × 10 ¹² cm ⁻² per atomic plane. Source electrode 15, drain electrode 17 and gate electrode 19 are n-type GaAs layer 1.
1 are arranged in a predetermined relationship.

FIGS. 5 (a) to 5 (c) show the MISF thus constructed.
The ET energy band diagram is shown.

The in Figure (a) is shown the gate voltage and the energy Ec and the Fermi level E _F at the lower end of the conduction band at zero. The low band gap n-type GaAs layer 7 is sandwiched between the high band gap undoped AlGaAs layers 5 and 9.
Therefore, a quantum well is formed in the GaAs layer 5. Since the δ-doped layer 13 is provided in the undoped AlGaAs layer 9 on the n-type GaAs layer 7, the bipolar between the δ-doped layer 13 and the interface between the undoped AlGaAs layer 5 and the n-type GaAs layer 7. Child moments are induced. This induced dipole moment leads to an effective increase of the potential barrier at the heterointerface of the n-type GaAs layer 7 / undoped AlGaAs layer 9.
That is, the energy Ec at the lower end of the conduction band at the position where the δ-doped layer 13 is inserted increases in a spike shape.

Next, as shown in FIG. 2B (hereinafter, the femil level Ef is omitted), when a voltage is applied to the gate electrode 19, the impurity atoms doped into the n-type GaAs layer 7 are changed with the increase of the gate voltage. Excited atoms are undoped AlGaAs layer 5 / n
It is accumulated in a quantum well formed by the type AlGaAs layer 7 / undoped AlGaAs layer 9.

Next, as shown in FIG. 3C, when a higher voltage is applied to the gate electrode 19, the n-type GaAs layer 7 / undoped
At the hetero interface of the AlGaAs layer 9, more electrons are accumulated and the pseudo Fermi level rises. When the pseudo Fermi level rises, the potential barrier at the hetero interface between the n-type AlGaAs layer 7 and the undoped AlGaAs layer 9 is effectively reduced. That is, the energy Ec at the lower end of the conduction band of the undoped AlGaAs layer 9 near the hetero interface between the n-type AlGaAs layer 7 and the undoped AlGaAs layer 9 is reduced, and the undoped AlGaAs layer 9 having an Ec equal to or higher than the energy level at which electrons are stored. Becomes narrower. However, due to the δ-doped layer 13 inserted in the undoped AlGaAs layer 9, the undoped AlGaAs
The width W of the conduction band Ec of the undoped AlGaAs layer 9 which is equal to or higher than the level of the conduction band Ec of the layer 9 and the energy level at which electrons are stored is higher and wider than that of the conventional case. For this reason, as shown in FIG.
Even if the voltage level applied to 19 reaches V _g2 shown in FIG. 7, electrons cannot cross the potential barrier, and traverse the undoped AlGaAs layer 9 vertically to form an n-type GaAs layer.
It is possible to prevent the generation of electrons that invade 11.

Thus, the MISFET of this embodiment can prevent the intrusion of electrons into the gate electrode at a high gate voltage.
The width of the safe region of the voltage that can be applied to 19 is widened, and as a result, more electrons are accumulated at the hetero interface of the n-type GaAs layer 7 and the undoped AlGaAs layer 9, so that the electrical characteristics such as drain current are improved.

The n-type GaAs layer 7 according to the present embodiment / undoped AlGaAs
The effective increase of the potential barrier at the hetero interface of layer 9 is undoped at about 5 to 19 nm away from this hetero interface.
When the δ-doped layer 13 is inserted in the AlGaAs layer 9, 50 to 150 m
It is about V. Further, when a logic circuit such as a DCFL circuit is assembled using the MISFET of the present embodiment, the noise margin is increased, so that the reliability of the circuit can be improved.

FIG. 2 is a sectional view of a MISFET according to a second embodiment of the present invention. Parts corresponding to those in the embodiment shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description is omitted.

This MISFET differs from that of the embodiment described above in that the second δ-doped layer 21 is inserted in the undoped AlGaAs layer 9. FIGS. 6A to 6C show energy band diagrams of the MISFET thus configured. FIG (a) shows the conduction band Ec and the Fermi level E _F when not in a voltage applied to the gate electrode 19. In the conduction band of the undoped AlGaAs layer 9 corresponding to the position where the δ-doped layers 13 and 21 are inserted, a spike-like level rise is observed. Next, when a voltage is applied to the gate electrode 19, as shown in FIG.
Electrons are accumulated at the hetero interface of the 7 / undoped AlGaAs layer 9. As in the previous embodiment, even if the gate voltage exceeds V _g2 , the effective potential barrier at the hetero interface of the n-type GaAs layer 7 / undoped AlGaAs layer 9 is high as shown in FIG. Therefore, the inconvenience that electrons enter the undoped AlGaAs layer 9 beyond this potential barrier does not occur.

Thus, the MISFET of this embodiment can provide the same effects as those of the above-described embodiment.

In this case, the undoped AlGaAs near the hetero interface of the n-type GaAs layer 7 / undoped AlGaAs layer 9 is different from that of the previous embodiment.
The effective level of the conduction band of layer 9 is higher and undoped Al at or above the energy level at which electrons are stored.
The width of the conduction band of the GaAs layer 9 also becomes wider. Therefore, the safe area width of the voltage that can be applied to the gate electrode 19 also becomes wider.

FIG. 3 is a sectional view of a MISFET according to a third embodiment of the present invention. This embodiment differs from the first embodiment in that a p-type GaAs layer 23 and an undoped GaAs layer 25 are sequentially provided between the buffer layer 3 and the undoped AlGaAs layer 5. In this embodiment, the impurity concentration of the p-type GaAs layer 23 is 3 × 10
¹⁷ The thickness was reduced to about 20 nm. The undoped GaAs layer 2
The thickness of 5 is about 10 nm.

With such a configuration, the same effect as that of the first embodiment can be obtained, of course, the short channel effect can be suppressed by the p-type GaAs layer 23, and the undoped GaAs layer 25 can be used in the manufacturing process. Undoped Ga in p-type GaAs layer 23
Diffusion into the As layer 5, the memory effect, and the parasitic capacitance of the source and drain regions can be prevented.

FIG. 4 is a sectional view of a MISFET according to a fourth embodiment of the present invention. This embodiment is different from the third embodiment described above in that the second δ-doped layer 21 is
That is, it is inserted in the GaAs layer 9.

With such a configuration, the same effects as those of the third embodiment can be obtained, as well as the n-type GaAs layer 7 / undoped AlGa.
Since the effective level of the potential barrier at the hetero interface of the As layer 9 is higher, the safe area width of the voltage that can be applied to the gate electrode 19 is wider.

The present invention is not limited to the embodiments described above. For example, although the MISFET using three or more δ-doped layers has not been described in the above embodiment, it goes without saying that a similar effect can be obtained in this case. Also,
In this case, even if the number of δ-doped layers increases, undoped AlGa
The essential layer thickness of the As layer 9 does not change. Therefore, a decrease in electrical characteristics such as a decrease in transconductance due to an increase in the thickness of the undoped AlGaAs layer 9 does not occur. Although carbon atoms having a small diffusion coefficient were used in AlGaAs as the δ-doped layer, the MISFET of the embodiment requires a high-temperature (950 ° C.) manufacturing process, so that atoms forming the δ-doped layer are diffused. This is to prevent the situation. Therefore, other atoms, such as Be and Mg, may be used as long as they function as acceptors in AlGaAs and have a small diffusion coefficient. Further, the quantum well may be formed using P-type GaAs instead of n-type GaAs. In this case, carriers serve as holes, and the δ-doped layer may be added with an impurity acting as a donor. Further, in the embodiment, the undoped AlGaAs layer
Although the quantum well is composed of a heterojunction of / n-type GaAs / undoped AlGaAs layer, it may be composed of InGaAs / InGaAsP / InGaAs, Si / SiGe / Si, or a semiconductor having a pseudomorphic structure. The point is that a semiconductor material that can form a junction having the same energy band structure as the InGaAs / InGaAsP / InGaAs junction may be selected. In addition, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] According to the semiconductor device of the present invention, the potential barrier for confining electrons is effectively increased by inserting an extremely thin impurity layer in the semiconductor layer constituting the layer for storing electrons. . As a result, the potential barrier can be prevented from lowering due to an increase in the gate voltage, so that the safe area of the voltage that can be applied to the gate is widened and the electrical characteristics such as the drain current are improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MISFET according to a first embodiment of the present invention,
FIG. 2 is a sectional view of a MISFET according to a second embodiment of the present invention,
FIG. 3 is a sectional view of a MISFET according to a third embodiment of the present invention,
FIG. 4 is a sectional view of a MISFET according to a fourth embodiment of the present invention,
FIGS. 5A to 5C show MIs according to the first embodiment of the present invention.
6 (a) to 6 (c) are energy band diagrams of the MISFET according to the second embodiment of the present invention, and FIG. 7 is an energy band diagram of the conventional MISFET. 1 ... semi-insulating substrate, 3 ... buffer layer, 5 ... undoped AlGaAs layer, 7 ... n-type GaAs layer, 9 ... undoped Al
GaAs layer, 11 ... n-type GaAs layer, 13 ... delta doped layer, 15 ...
Source electrode, 17 ... drain electrode, 19 ... gate electrode,
21 δ-doped layer, 23 p-type GaAs layer, 25 undoped GaAs layer.

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/336 H01L 29/78 H01L 29/812

Claims (1)

(57) [Claims] 1. A semiconductor device in which carriers accumulated in a superlattice formed by heterojunction of a plurality of semiconductor layers are controlled by a voltage applied to a gate, wherein the semiconductor layer closest to the gate among the plurality of semiconductor layers is provided. A semiconductor device, wherein an impurity layer to which an impurity serving as an acceptor when the carrier is an electron or an impurity serving as a donor when the carrier is a hole is added.