JPH04149736A - Register writing control system for central processing unit - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of the central processing unit by simultaneously writing load data fetched from a storage control part against a master register and a copy register equipped with the central processing unit in one pipe line flow. CONSTITUTION:A command decoding means 6 is constructed to issue a command indicating simultaneous load to both of a master register 4 and a copy register 5. When receiving this simultaneous load indication command, an activation means 12 performs the latch processing of the load data latched to the register 8 simultaneously to a register 10 while performing activation to a transmission bus 11 at the timing of the load data fetched from a data storage means 7 to be transferred from a register 9 to a register 8. Thus the data can be simultaneously written in both the master register 4 and the copy register 5 by performing latching. Thus, the processing efficiency of a central processing unit 1 can be improved.

Description

[Detailed Description of the Invention] [Summary] Write processing of the master register and copy register provided in the central processing unit! Regarding the register write control method in the central processing unit that performs IJW, the instruction control unit included in the central processing unit is It is configured to issue a command that instructs simultaneous loading to both the master register and the copy register, and a transfer bus that transfers the data to be loaded into the master register to the store bus of the copy register, and a command that instructs simultaneous instruction is issued. When you
By providing activation means for activating the transfer bus,
The data fetched from the storage control unit is configured to be written into both the master register and the copy register at the same time.

[Industrial application field]

The present invention relates to a register write control method in a central processing unit that controls write processing of master registers and copy registers provided in the central processing unit, and particularly relates to a register write control method in a central processing unit that controls write processing of master registers and copy registers in one pipeline flow. The present invention relates to a register write control method in a central processing unit that enables the execution of the following.

In the central processing unit, the instruction control unit and execution control unit write/
! *Configured so that load/store instructions can be executed efficiently by having a mask register for control registers that are connected to the output bus and can be loaded/stored from software in the instruction control unit or execution control unit. At the same time,
A configuration will be adopted in which the copy register is connected to the store bus and brought to the storage control unit, and is used to control storage access. The processing of loading data into these mask and copy registers must be configured to be executed as quickly as possible in order to increase the processing efficiency of the central processing unit.

(Prior Art) Conventionally, when a load instruction to these registers is issued, as shown in FIG.
), and according to this ACCS code, the local buffer storage (LBS)
The fetched load data is latched into the operand write register (OWR) provided at the input stage of the processing unit 7, and then the result register (RWR) provided at the output stage of the processing unit 7 is latched.
R) is latched and loaded into the mask register with the subsequent write cycle. Then, in the next pipeline flow, seven nodes (SET) are applied to the instruction control unit and storage control unit.
According to this ACCS code, the load data that is latched into the result register is latched into the store data register (STDR), and then loaded into the copy register in the following write cycle. Then, the load processing to the master register and copy register was executed.

(Problems to be Solved by the Invention) As described above, in the conventional technology, two pipeline flows were required for the load processing for one set of master register and copy register. The problem was that efficiency decreased.

The present invention has been made in view of such circumstances, and includes:
The object of the present invention is to provide a new register write control method in a central processing unit that allows write processing of master registers and copy registers to be executed using a vibe line flow.

[Means to solve the problem] FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 1 is a central processing unit equipped with the present invention, 2 is an instruction control unit included in the central processing unit 1 and includes a master register 4, and 3 is a storage control unit included in the central processing unit 1. , a copy register 5. Here, the master register 4 is a central processing unit 1 (not shown).
An execution control unit may also be provided.

Reference numeral 6 denotes a command decoding unit provided in the instruction control unit 2, which decodes and issues a command with a processing request, and 7 refers to a data storage unit provided in the storage control unit 3, which includes a master register 4 and a copy register 5. 8 is a register provided in the instruction@door section 2 and latches the load data to be loaded into the master register 4; 9 is a register provided in the instruction control section 2; , latches the load data fetched from the data storage means 7 and inputs it to the register 8, IO
I is a register provided in the storage control unit 3 and latches the load data to be loaded into the copy register 5;
Reference numeral I designates a transfer bus that transfers load data input to the register 8 to the register IO, and reference numeral 12 designates activation means constituted by, for example, a selector, which activates the transfer bus 11.

[Operation] In the present invention, the command decoding means 6 reads the master register 4.
It is configured to issue a command instructing simultaneous loading into both the copy register 5 and the copy register 5.

Upon receiving this simultaneous load instruction command, the activation means 12 activates the transfer bus 11 at the timing when the load data fetched from the data storage means 7 is transferred from the register 9 to the register 8. In this way, the load data latched in the register 8 is processed to be launched in the register 10 at the same time. By launching in this way, the load data can be written into both the master register 4 and the copy register 5 at the same time.

In this way, in the present invention, load data fetched from the storage control unit 3 can be written into the master register 4 and copy register 5 provided in the central processing unit 1 in one pipeline flow.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 illustrates an embodiment of the hardware mechanism of the central processing unit 1 constructed according to the present invention.

In the figure, the same parts as those explained in FIG. 1 are indicated by the same symbols, and the parts indicated by the pipeline flow of DATBEW shown in the upper row are provided in the instruction control unit 2 explained in FIG. 1. Hardware mechanism, lower PTB
The part shown by the RWS pipeline flow is the hardware mechanism included in the storage control unit 3 explained in FIG.

20 is an instruction buffer which stores the instruction code; 21 is a pace register which stores base information written in the instruction code; 22 is an index register which is written in the instruction code. 23 is a displacement register that stores the displacement information; 24 is an effective address adder that stores the base information held by the pace register 21 and the index held by the index register 22; A virtual address to be accessed is obtained by adding the displacement information held by the displacement register 23, and 25 is an effective address register which stores the virtual address calculated by the effective address adder 24. 26 is a local buffer storage that stores a copy of main memory data; 27 is a control storage that outputs processing type information (ACCS code) of the instruction code; 28-4 is a local buffer storage that stores a copy of main memory data; A.C.
This is a CS register, and is used to flow the ACCS code output from the control storage 27 into the pipeline.

29 is an operand write register which latches data read out from the local expansion storage 26; 30 is a first operand register which latches data to be operated on which is read out from the master register 4; and 31 The second operand register is a register that latches the data to be operated on that is read out from the mask register 4. The numeral 33 is an arithmetic unit that constitutes an execution control unit that performs arithmetic processing on the input data (load processing to the master register 4). 34 is a result register which latches the calculation result of the calculation unit 33, and 35 is a store data register. , a selector 36 launches the data to be loaded into the copy register 5, and 36 is a selector which launches data held in the operand write register 29 or the first one according to the ACCS code flowing through the ACOS register 28-1. Either data held in the operand register 30 or data held in the second operand register 31 is selected and transferred to the store data register 35.

In the present invention, the control storage 27 is newly
The feature is that it has a configuration that outputs the ACCS code "FETcH &sET", and the selector 3
6 selectively outputs the data held in the operand write register 29, thereby transferring the data held in the operand write register 29 to the store data register 3.
The feature is that it adopts a configuration that allows transfer to 5.

In Figure 3, this newly installed rFETCH & 5ET
An example of a circuit for generating a control signal issued when an ACCS code J flows through a pipeline flow of DATBEW is illustrated.

As shown in this figure, the decoder allows rFETCHJ
When the ACCS code rFETCH & 5ETJ is detected flowing into the B stage of the pipeline, the FETC displays that the fetch data sent from the storage controller 3 is valid.
HDATAVALID (At the timing of No. 3, the clock of the operand write register 29 is activated and the data read from the local buffer storage 26 is processed to be taken into this operand write register 29. Here, the ACCS code rFETCHJ is as follows.
This code instructs to load data into the master register 4 and copy register 5 using the conventional two-pipeline flow.

When the decoder detects that the ACOS code "rFETCH &SET" flows into the E stage of the pipeline, the selector 36 sends a SEL
By sending the OWRTo 5TDR signal, the selector 36 is controlled to selectively output the data held in the operand write register 29, thereby processing the data held in the operand write register 29 to be taken into the store data register 35. .

Then, the ACCS code rEXcEPTIONJ, which represents exception handling, or rMAcHI, which represents machine check.
Either the ACCS code NE CHECKJ or the CLEARP[PELIN
The ACCS code EJ is sent to pipeline 1 (when it is detected that it is flowing, IN) l REG WRIT
By sending the E signal, processing is performed to suppress loading to the master register 4. Furthermore, this INHREG
While sending out the WRITE signal, the decoder converts the ACCS code rsTOREj to rFE.
When it detects that ACC3I-F "TcH&sET" flows into the W stage of the pipeline, 5TOR
By sending the E5UPPRESS signal, processing is performed to suppress rotor transfer to the copy register 5.

In this way, in the present invention, as shown in FIG. 4, in the B stage of the pipeline, the operand write register 2
9 is activated to process the data read from the local buffer storage 26 into the operand write register 29, and at the E stage of the pipeline, the selector 36 is newly input according to the present invention. By controlling the data held in the operand write register 29 to be selectively output, the data held in the operand write register 29 is processed to be read into the master register 4 and into the store data register 35 at the same time. The pipeline flow makes it possible to execute load processing on the master register 4 and copy register 5.

(Effects of the Invention) As described above, according to the present invention, it is possible to write load data fetched from the storage control unit into the master register and copy register provided in the central processing unit using the l-bit line flow. Therefore, the processing efficiency of the central processing unit can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is an embodiment of the hardware mechanism of a central processing unit constructed according to the present invention, Fig. 3 is an embodiment of a control signal generation circuit, and Fig. 4 5 is a detailed explanatory diagram of the present invention, and FIG. 5 is an explanatory diagram of the prior art. In the figure, 1 is a central processing unit, 2 is an instruction control unit, 3 is a storage control unit, 4 is a master register, 5 is a copy register, 6 is a command decoding means, 7 is a data storage means, 11 is a transfer bus, and 12 is a It is an activation means.

Claims (1)

[Claims] The instruction control unit (2) or the execution control unit is connected to the master register (4).
), the storage control unit (3) has a copy register (5), fetches data from the storage control unit (3) according to commands issued by the instruction control unit (2), and transfers the data to the master register. (4) and the copy register (5), in the central processing unit of the data processing device, the instruction control unit (2) loads the master register (4) and the copy register (5). a transfer bus (11) configured to issue a command instructing simultaneous loading to both the master register (4) and transfer the data to be loaded into the master register (4) to the store bus of the copy register (5); By providing activation means (12) for activating the transfer bus (11) when a simultaneous instruction command is issued, the data fetched from the storage control unit (3) is transferred to the master register (4). ) and the copy register (5) at the same time.