CN118013897A - Register verification method and device - Google Patents
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Abstract
The invention provides a register verification method and a register verification device, which relate to the technical field of chips, wherein the register verification method comprises the following steps: executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other; where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation. According to the invention, the verification operation is carried out on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other, so that the situations that the random numbers of two registers are identical, whether adhesion exists between the two registers or not is difficult to distinguish during verification, and the like are avoided, and different random numbers are used for verification, so that each register to be verified can be effectively distinguished, whether adhesion exists between the two registers to be verified is further effectively verified, and the accuracy of the problem of adhesion verification is improved.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method and an apparatus for verifying a register.
Background
In the field of digital integrated circuits, registers are the most indispensable logic devices, whether central processing units (Central Processing Unit, CPU), graphics processors (Graphics Processing Unit, GPU), system On Chip (SOC), or common internet protocol (Internet Protoco, IP). Verification of registers may be considered an essential task for digital integrated circuit testing. The sticky problem that registers introduce in the design is a bug (bug) that is difficult to find in register testing, because it belongs to a correlation problem between registers, and in theory, there may be a sticky between any two registers.
Disclosure of Invention
The invention provides a register verification method and device, which are used for solving the problem that any two registers possibly have adhesion in the prior art.
The invention provides a register verification method, which comprises the following steps:
executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
According to the method for verifying the register provided by the invention, the verification operation is performed on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other, and the method comprises the following steps:
Executing the verification operation on the N registers to be verified according to ascending order by utilizing N first random numbers in the random numbers;
And executing the verification operation on the N registers to be verified according to descending order by using N second random numbers in the random numbers.
According to the method for verifying the register provided by the invention, the verification operation is performed on the N registers to be verified in an ascending order, and the method comprises the following steps:
The following steps are executed for each register to be verified in the N registers to be verified in ascending order:
Reading a first current value of the register to be verified, and verifying whether the first current value is consistent with a default value corresponding to the register to be verified;
Writing a first random number corresponding to the register to be verified into the register to be verified under the condition that the first current value is consistent with the default value;
And reading a second current value of the register to be verified, and verifying whether the second current value is consistent with the first random number written into the register to be verified.
According to the method for verifying a register provided by the present invention, the verifying operation is performed on the N registers to be verified according to a descending order by using N second random numbers in the random numbers, and the method includes:
the following steps are performed for each of the N registers to be verified in descending order:
Reading a third current value of the register to be verified, and verifying whether the third current value is consistent with the first random number written into the register to be verified;
Writing a second random number corresponding to the register to be verified into the register to be verified under the condition that the third current value is consistent with the first random number written into the register to be verified;
And reading a fourth current value of the register to be verified, and verifying whether the fourth current value is consistent with the second random number written into the register to be verified.
According to the verification method of the register provided by the invention, the method further comprises the following steps:
determining that the register to be verified fails to be verified under the condition that a first event occurs; wherein the occurrence of the first event includes at least one of:
The first current value is inconsistent with the default value;
the second current value is inconsistent with the first random number written into the register to be verified;
the third current value is inconsistent with the first random number written into the register to be verified;
the fourth current value is inconsistent with the second random number written into the register to be verified.
According to the register verification method provided by the invention, the N first random numbers, the N second random numbers and the N registers to be verified are different in corresponding default values.
According to the verification method of the register provided by the invention, the method further comprises the following steps:
generating the N first random numbers;
and executing the inverting operation on the N first random numbers to obtain the N second random numbers.
The invention also provides a register verification device, which comprises:
The verification module is used for: executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing a method of verifying a register as described above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of verifying a register as described in any of the above.
The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements a method of verifying a register as described in any of the above.
According to the register verification method and device, the random 2N random numbers which are not consistent with each other are utilized to execute verification operation on N registers to be verified, so that the situation that whether adhesion exists between two registers or not is difficult to distinguish during verification, for example, the random numbers of the two registers are identical is avoided, different random numbers are utilized to verify, each register to be verified can be effectively distinguished, whether adhesion exists between the two registers to be verified is further effectively verified, and accuracy of adhesion verification problem is improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a register verification method according to the present invention;
FIG. 2 is a second flow chart of the register verification method according to the present invention;
FIG. 3 is a schematic diagram of a register verification device according to the present invention;
Fig. 4 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The register verification method and device of the present invention are described below with reference to the accompanying drawings.
FIG. 1 is a schematic flow chart of a register verification method according to the present invention, as shown in FIG. 1, the register verification method includes step 101; wherein:
Step 101, executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other; where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
In the related art, registers are widely used, and the specifications of registers are generally highly uniform. Therefore, the verification technology of the register can be unified.
The sticky problem that registers introduce in the design is a bug that is difficult to find by register testing, because it belongs to a problem of association between registers, and in theory there may be a sticky between any two registers.
The following illustrates the sticky problem that registers often introduce at design time: if there are N registers in a design, the registers are respectively numbered as Reg_0, reg_1, reg_2, … and Reg_N; the addresses of the registers are addr_0, addr_1, addr_2, …, addr_n in sequence.
The following is a piece of correct register configuration Verilog HDL (Hardware Description Language ) pseudocode (config_data represents the value to be configured for a register, addr represents the address of the configuration register, the address of which register is matched to which config_data is configured to which register):
if a hardware engineer is designing, the code has an error, addr_3 should be configured to register reg_3, but the configured value is wrongly written to reg_1, and the code is as follows:
The above scenario is a typical case of register sticking, and such errors are very likely to occur. Register sticking is also understood to mean that when a certain register is configured, it has an effect on the contents of the remaining registers.
Since registers have been a few decades old, many methods of testing registers have also been developed. The test method which is more common at least comprises the following two steps:
The method comprises the following steps: the specific flow is as follows:
1) Checking whether the initial value of the register is consistent with the description of the form;
2) Writing 0x5a5a5a5a into the register in ascending order, reading and checking (check) whether the register is correct;
3) Writing 0xa5a5a5a5 into the register in ascending order, and reading out whether check is correct or not; writing a random value into the register, and reading out whether the check is correct or not;
4) Writing 0x5a5a5a5a into the register in descending order, and reading out whether check is correct or not;
5) Writing 0xa5a5a5a5 into the register in descending order, and reading out whether check is correct or not; writing a random value into the register, and reading out whether the check is correct or not;
6) Writing 0x5a5a5a5a into the register in ascending order, and reading out whether check is correct or not;
7) Writing 0xa5a5a5a5 into the register in ascending order, and reading out whether check is correct or not; writing a random value into the register, and reading out whether the check is correct or not;
8) Writing 0x5a5a5a5a into the register in descending order, and reading out whether check is correct or not;
9) The register is written with 0xa5a5a5a5 in descending order, whether the read-out and check are correct or not, the register is written with a random value, and whether the read-out and check are correct or not.
When the number of registers is N, the total number of times of reading and writing is 25N according to the steps.
The second method is as follows: the specific flow is as follows:
a) Performing W_55 in an address ascending order;
b) Performing R_55, W_AA and R_AA in an address ascending order;
c) Performing R_AA, W_55 and R_55 in an address ascending order;
d) Performing R_55, W_AA and R_AA in the descending order of addresses;
e) The address descending order performs r_aa, w_55, r_55.
The specific meanings of the operations of w_55, w_aa, r_55 and r_aa are as follows:
w_55: write 0x55555555;
R_55: write 0x55555555, read register and check;
w_aa: writing 0xAAAAAAAA;
R_aa: write 0xAAAAAAAA, read register and check.
The above two methods are all the time in ascending and descending order cyclic test during test, and the purpose is to test the adhesion problem between registers, but the accuracy of the adhesion problem of the test registers is low, mainly because: the test method can only solve the problem of adhesion of adjacent registers, but cannot solve the problem of adhesion of non-adjacent registers, especially registers far away in address.
For example, two registers, one address 0x0010 and one 0x1010, are far apart; however, the addresses of the two registers differ by only one bit (bit), and the hardware engineer may embed a bug therein. It can be said that the two register test techniques mentioned above are theoretically incomplete and have the probability of missing a bug, and the conventional register test cannot solve the sticking problem by using only a constant value, and cannot ensure that the values of each random are inconsistent although random numbers are also used.
In view of the above problems, the embodiments of the present invention provide a method for verifying a register, which may be applied to, for example, verifying a readable/writable register, where verification may not only be limited to verifying a register adhesion problem, but also may be performed on other performances of the register, for example, verifying a read/write performance.
Specifically, the embodiment of the invention uses 2N random numbers which are randomly generated and are inconsistent with each other to execute verification operation on N registers to be verified, wherein the verification operation can be realized through reading operation and writing operation, namely, when different registers to be verified execute the verification operation, the random numbers used are different, thus, the situation that for example, the random numbers of two registers are identical, and whether adhesion exists between the two registers or not is difficult to distinguish during verification can be avoided.
For example, there are two registers reg_0 and reg_1, and their corresponding random numbers are 1, for example, there is a sticky connection between the two registers, and they are allocated to reg_1 when address allocation is performed on reg_0;
If the random number 1 is written into reg_0 and is actually written into reg_1, and the random number corresponding to reg_1 is also 1, it is difficult to distinguish whether the random number 1 written into reg_1 is normally written into reg_1 itself or is written into reg_0 and reg_1 due to adhesion, which may result in neglecting the adhesion condition and further result in low accuracy of testing the register adhesion problem.
While embodiments of the present invention are strictly constrained: different registers to be verified, different random numbers are utilized to execute verification operation, so that the problems caused by the conditions can be effectively avoided, whether adhesion exists between two registers to be verified can be effectively verified, and the accuracy of verifying the adhesion problem is improved.
In the register verification method provided by the embodiment of the invention, the verification operation is performed on N registers to be verified by using 2N random numbers which are randomly generated and are inconsistent with each other, so that the situations that whether adhesion exists between two registers or not is difficult to distinguish during verification, and the like can be avoided, and different random numbers are used for verification, so that each register to be verified can be effectively distinguished, whether adhesion exists between the two registers to be verified can be effectively verified, and the accuracy of the adhesion verification problem is improved.
Optionally, the implementation manner of performing the verification operation on the N registers to be verified by using 2N random numbers that are generated randomly and are inconsistent with each other may include:
Executing the verification operation on the N registers to be verified according to ascending order by utilizing N first random numbers in the random numbers;
And executing the verification operation on the N registers to be verified according to descending order by using N second random numbers in the random numbers.
Specifically, the flow of performing the verify operation on N registers to be verified may be divided into two phases (Phase):
Phase1 (ascending): and executing verification operation on the N registers to be verified according to the ascending order, and particularly executing the verification operation on each register to be verified by utilizing the corresponding first random number.
Phase2 (descending order): and executing verification operation on the N registers to be verified according to the descending order, and particularly executing verification operation on each register to be verified by using the corresponding second random number.
It should be noted that, in the embodiment of the present invention, the execution sequence of Phase1 and Phase2 is not limited to the execution sequence of Phase1 and Phase2, and Phase2 may be executed first and then Phase1 may be executed, that is, the verification operation is executed on N registers to be verified in descending order first and the verification operation is executed on N registers to be verified in ascending order.
The ascending order may be in the order of the register addresses from small to large, and the descending order may be in the order of the register addresses from large to small.
In the embodiment of the invention, the Phase1 stage performs verification operation on the ascending order of the registers, so that whether a certain register is affected by the adhesion of any one of the registers in front of the register can be verified; the Phase2 Phase performs verification operation on the register in descending order, so that whether a certain register is affected by the adhesion of any one of the following registers can be verified, the verification is not limited to only verifying whether adjacent registers are adhered, and the problem of adhesion of non-adjacent registers can be solved, particularly the register far away in address.
Optionally, the implementation manner of performing the verification operation on the N registers to be verified in ascending order may include:
The following steps are executed for each register to be verified in the N registers to be verified in ascending order:
Reading a first current value of the register to be verified, and verifying whether the first current value is consistent with a default value corresponding to the register to be verified;
Writing a first random number corresponding to the register to be verified into the register to be verified under the condition that the first current value is consistent with the default value;
And reading a second current value of the register to be verified, and verifying whether the second current value is consistent with the first random number written into the register to be verified.
Optionally, the implementation manner of performing the verification operation on the N registers to be verified by using N second random numbers in the random numbers in descending order may include:
the following steps are performed for each of the N registers to be verified in descending order:
Reading a third current value of the register to be verified, and verifying whether the third current value is consistent with the first random number written into the register to be verified;
Writing a second random number corresponding to the register to be verified into the register to be verified under the condition that the third current value is consistent with the first random number written into the register to be verified;
And reading a fourth current value of the register to be verified, and verifying whether the fourth current value is consistent with the second random number written into the register to be verified.
Optionally, the N first random numbers may also be generated;
and executing the inverting operation on the N first random numbers to obtain the N second random numbers.
Specifically, in the ascending stage, a first random number is written into each register to be verified, in the descending stage, the first random number is written into each register to be verified after being inverted, namely a second random number is written into each register to be verified, so that each bit of each register to be verified is guaranteed to be subjected to 0 and 1 writing operation, namely each bit is traversed by 0 and 1, and on the basis of whether the register to be verified is adhered, the reading and writing functions of the register can be effectively verified, and the completeness of register verification is guaranteed.
Alternatively, it may be determined that the register to be verified fails to verify in the event of the first event;
Wherein the occurrence of the first event includes at least one of:
1) The first current value is inconsistent with the default value;
2) The second current value is inconsistent with the first random number written into the register to be verified;
3) The third current value is inconsistent with the first random number written into the register to be verified;
4) The fourth current value is inconsistent with the second random number written into the register to be verified.
Specifically, in the Phase1 stage (ascending order), for each register to be verified, if the first current value of the register to be verified is not consistent with the default value corresponding to the register to be verified, the register to be verified is considered to fail to verify, and an error can be reported to the register to be verified; or after the first random number is written into the corresponding register to be verified, if the second current value of the register to be verified is not consistent with the written first random number, the register to be verified is considered to fail to verify, and the error can be reported.
In Phase2 (descending order), for each register to be verified, if the third current value of the register to be verified is not consistent with the first random number written in correspondingly before, the register to be verified is considered to fail verification, and error reporting can be carried out on the register to be verified; or after the second random number is written into the corresponding register to be verified, if the fourth current value of the register to be verified is not consistent with the written second random number, the register to be verified is considered to be failed to verify, and the error can be reported.
Optionally, the N first random numbers, the N second random numbers are all different from default values corresponding to the N registers to be verified.
Specifically, the random numbers may be further constrained, where N first random numbers used in ascending order and N second random numbers used in descending order are both constrained to be different, and the set random numbers need to be different from default values corresponding to N registers to be verified, so that situations that after the first random value is written into a certain register, for example, due to the fact that the default value corresponding to the certain register is the same as the first random value, it is unclear whether the first random value has been successfully written into the register can be avoided.
For example, for the register reg_0 to be verified, in the process of executing the verification operation on the register to be verified in ascending order, it is required to read whether the current value of reg_0 is the default value, then write the first random number into reg_0 and read, if both the default value of reg_0 and the first random number are 1, in the process of executing the verification operation, the default value of reg_0 is 1, then write the first random number 1 into reg_0, then find that the read value is 1, so it is difficult to distinguish whether the first random number 1 is successfully written into reg_0 here, and further it is difficult to effectively verify the register reg_0.
The default value is different from the first random value, so that the process of reading the default value and the process of writing and reading the first random value can be clearly distinguished, and further, whether the adhesion problem exists between the registers can be effectively verified.
The following illustrates a method and an apparatus for verifying a register according to an embodiment of the present invention.
The traditional register test method mainly has the following defects:
1) The total number of times of register reading and writing is too much, and in particular, the second method is adopted;
2) The problem of blocking of adjacent registers can only be solved, and the problem of blocking of non-adjacent registers cannot be solved, especially for registers far away in address. For example, two registers, one address 0x0010 and one 0x1010, are far apart; however, the addresses of the two registers are not identical with one bit, and the hardware engineer may embed a bug therein. It can be said that the two register test techniques mentioned above are theoretically incomplete and are probability of having a leakage bug.
The embodiment of the invention aims at the loopholes of the traditional register test. The conventional register test cannot solve the adhesion problem by only using a fixed value, and although a random number is also used, the random number cannot be ensured to be inconsistent every time the random number is random, and the random number cannot be ensured to be inconsistent with the default value of the register.
The embodiment of the invention fully utilizes the method for restraining the random number, and carries out strict restraint on the random number: any two random numbers used in the verification operation process cannot be consistent; and none of the random numbers described above can be consistent with any of the default values of the registers. The defect that the traditional register test method can only ensure that adjacent registers are not adhered is overcome, and the total number of times of reading and writing of the test is obviously reduced.
The embodiment of the invention provides a verification method of a register, which can perform omnibearing test on the adhesion problem of the register, ensure that all the adhesion problems of the register in the design are tested, and ensure the completeness of the adhesion test of the register.
Assuming that the logic to be tested contains n+1 registers (i.e., registers to be verified), the registers are numbered reg_0, reg_1, reg_2, …, reg_n; default values for each register are data_0, data_1, data_2, …, data_n; the bit width of the register is 32 bits; the 32 bits of each register are readable and writable, i.e. the invention is mainly directed to readable and writable registers.
Using a register test program, generating a random number for each register, the random numbers being in turn: rand_0, rand_1, rand_2, …, rand_n. The values rand_0, rand_1, rand_2, …, rand_n are each bit inverted with the number nRand _0, nRand _1, nRand _2, …, nRand _n.
The random number requirements of the embodiment of the invention are as follows: the 2N+2 numbers rand_0 to rand_N and nRand _0 to nRand _N cannot be identical to any two. Any of the numbers 2n+2 of rand_0 to rand_n and nRand _0 to nRand _n cannot be the same as any of the numbers data_0 to data_n.
Before the register test, the test program generates 2N+2 numbers of rand_0 to rand_N and nRand _0 to nRand _N according to the above requirements. After the generation is completed, fig. 2 is a second flow chart of the register verification method provided by the invention, and as shown in fig. 2, the test of the register is performed according to the flow chart in the figure. The test flow of the register is mainly divided into two stages: phase 1 and Phase 2:
The specific flow of Phase1 (ascending order) includes:
1) Reading a default value of Reg_0, detecting whether the read value is equal to Data_0, if so, executing the next step, otherwise, reporting an error;
2) Writing rand_0 to reg_0; reading Reg_0, detecting whether the read value is equal to rand_0, if so, executing the next step, otherwise, reporting an error;
3) Reading a default value of Reg_1, detecting whether the read value is equal to data_1, if so, executing the next step, otherwise, reporting an error;
4) Writing rand_1 to reg_1; reading Reg_1, detecting whether the read value is equal to rand_1, if so, executing the next step, otherwise, reporting an error;
5) The operations of 3) -4) are sequentially executed on the remaining registers reg_2 to reg_n according to the sequence from the small register address to the large register address, imitating reg_1, and are not repeated here.
The specific flow of Phase2 (descending order) includes:
6) Writing nRand _N to reg_N; then, reading Reg_N, detecting whether the read value is equal to nRand _N, if so, executing the next step, otherwise, reporting an error;
7) Reading Reg_N-1, detecting whether the read numerical value is equal to rand_N-1, if so, executing the next step, otherwise, reporting an error;
8) Writing nRand _N-1 to Reg_N-1; then, reading Reg_N-1, detecting whether the read value is equal to nRand _N-1, if so, executing the next step, otherwise, reporting an error;
9) Reading Reg_N-2, detecting whether the read numerical value is equal to rand_N-2, if so, executing the next step, otherwise, reporting an error;
10 nRand _n-2 to reg_n-2; then, reading Reg_N-2, detecting whether the read value is equal to nRand _N-2, if so, executing the next step, otherwise, reporting an error;
11 For the rest reg_n-3 to reg_0, according to the sequence of register addresses from big to small, the operations of 9) -10) are executed in sequence by imitating reg_n-2, and are not repeated here;
12 Ending the test.
The Phase1 stage is to operate the registers in ascending order, so that a certain register can be prevented from being affected by any register adhesion in front of the register.
The Phase2 stage is a descending operation on registers, and can avoid that a certain register is affected by any register adhesion after the register.
The 2N+2 values mentioned above for rand_0 to rand_N and nRand _0 to nRand _N have a strict random constraint. Such constraints are present because some false authentication situations can be avoided.
For example, two registers reg_a and reg_b, with default values of data_a and data_b, respectively, and corresponding random numbers of rand_a and rand_b;
If rand_a and rand_b are generated completely randomly, then rand_a is likely to be equal to data_b, and in Phase1, reg_a is written with rand_a, then when reg_b is operated, the value of reg_b is read, and data_b is read, which makes it difficult to determine whether data_b was wrongly written due to adherence between reg_a and reg_b when reg_a was configured. In the embodiment of the invention, the constraint that rand_a cannot be equal to data_b is basically avoided.
In addition, the embodiment of the invention writes random numbers into each register in the ascending Phase1 stage; in the Phase2 of descending order, the random number is fetched and written back into each register, so that each bit of each register can be guaranteed to be written with 0 and 1, and each bit of each register is guaranteed to be traversed with 0 and 1.
The embodiment of the invention has at least the following beneficial effects:
1) The probability of verifying any two registers to be stuck is effectively improved;
2) The total times of reading and writing the register are effectively reduced. Assuming that there are N registers to be detected, even the first method in the related art with a smaller total number of reads and writes requires performing a total of 25N reads and writes operations; the embodiment of the invention only needs to execute 6N read-write operations, thereby effectively reducing the total read-write times of the register.
The verification device of the register provided by the invention is described below, and the verification device of the register described below and the verification method of the register described above can be referred to correspondingly.
Fig. 3 is a schematic structural diagram of a register verification device according to the present invention, and as shown in fig. 3, a register verification device 300 includes:
A verification module 301, configured to: executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
In the register verification device provided by the embodiment of the invention, the verification module performs verification operation on N registers to be verified by using 2N random numbers which are randomly generated and are inconsistent with each other, so that the situations that whether adhesion exists between two registers or not is difficult to distinguish during verification, and the like are avoided, and different random numbers are used for verification, so that each register to be verified can be effectively distinguished, whether adhesion exists between the two registers to be verified is further effectively verified, and the accuracy of the adhesion verification problem is improved.
Optionally, the verification module 301 is specifically configured to:
Executing the verification operation on the N registers to be verified according to ascending order by utilizing N first random numbers in the random numbers;
And executing the verification operation on the N registers to be verified according to descending order by using N second random numbers in the random numbers.
Optionally, the verification module 301 is further specifically configured to:
The following steps are executed for each register to be verified in the N registers to be verified in ascending order:
Reading a first current value of the register to be verified, and verifying whether the first current value is consistent with a default value corresponding to the register to be verified;
Writing a first random number corresponding to the register to be verified into the register to be verified under the condition that the first current value is consistent with the default value;
And reading a second current value of the register to be verified, and verifying whether the second current value is consistent with the first random number written into the register to be verified.
Optionally, the verification module 301 is further specifically configured to:
the following steps are performed for each of the N registers to be verified in descending order:
Reading a third current value of the register to be verified, and verifying whether the third current value is consistent with the first random number written into the register to be verified;
Writing a second random number corresponding to the register to be verified into the register to be verified under the condition that the third current value is consistent with the first random number written into the register to be verified;
And reading a fourth current value of the register to be verified, and verifying whether the fourth current value is consistent with the second random number written into the register to be verified.
Optionally, the register verification apparatus 300 further includes:
a processing module for: determining that the register to be verified fails to be verified under the condition that a first event occurs; wherein the occurrence of the first event includes at least one of:
1) The first current value is inconsistent with the default value;
2) The second current value is inconsistent with the first random number written into the register to be verified;
3) The third current value is inconsistent with the first random number written into the register to be verified;
4) The fourth current value is inconsistent with the second random number written into the register to be verified.
Optionally, the N first random numbers, the N second random numbers are all different from default values corresponding to the N registers to be verified.
Optionally, the processing module is further configured to:
generating the N first random numbers;
and executing the inverting operation on the N first random numbers to obtain the N second random numbers.
Fig. 4 is a schematic structural diagram of an electronic device according to the present invention, and as shown in fig. 4, the electronic device 400 may include: processor 410, communication interface (Communications Interface) 420, memory 430, and communication bus 440, wherein processor 410, communication interface 420, and memory 430 communicate with each other via communication bus 440. Processor 410 may invoke logic instructions in memory 430 to perform a method of verifying a register, the method comprising:
executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
Further, the logic instructions in the memory 430 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product comprising a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of performing a method of verifying a register provided by the methods described above, the method comprising:
executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method of verifying a register provided by the above methods, the method comprising:
executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of verifying a register, comprising:
executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
2. The method according to claim 1, wherein the performing a verification operation on N registers to be verified using 2N random numbers that are not identical to each other, which are randomly generated, includes:
Executing the verification operation on the N registers to be verified according to ascending order by utilizing N first random numbers in the random numbers;
And executing the verification operation on the N registers to be verified according to descending order by using N second random numbers in the random numbers.
3. The method according to claim 2, wherein the performing the verification operation on the N registers to be verified in ascending order includes:
The following steps are executed for each register to be verified in the N registers to be verified in ascending order:
Reading a first current value of the register to be verified, and verifying whether the first current value is consistent with a default value corresponding to the register to be verified;
Writing a first random number corresponding to the register to be verified into the register to be verified under the condition that the first current value is consistent with the default value;
And reading a second current value of the register to be verified, and verifying whether the second current value is consistent with the first random number written into the register to be verified.
4. A method of verifying a register as defined in claim 3, wherein said performing said verification operation on said N registers to be verified in descending order using N second ones of said random numbers comprises:
the following steps are performed for each of the N registers to be verified in descending order:
Reading a third current value of the register to be verified, and verifying whether the third current value is consistent with the first random number written into the register to be verified;
Writing a second random number corresponding to the register to be verified into the register to be verified under the condition that the third current value is consistent with the first random number written into the register to be verified;
And reading a fourth current value of the register to be verified, and verifying whether the fourth current value is consistent with the second random number written into the register to be verified.
5. The method of register verification according to claim 4, further comprising:
determining that the register to be verified fails to be verified under the condition that a first event occurs; wherein the occurrence of the first event includes at least one of:
The first current value is inconsistent with the default value;
the second current value is inconsistent with the first random number written into the register to be verified;
the third current value is inconsistent with the first random number written into the register to be verified;
the fourth current value is inconsistent with the second random number written into the register to be verified.
6. The method according to claim 5, wherein the N first random numbers, the N second random numbers are each different from default values corresponding to the N registers to be verified.
7. A method of register verification according to any one of claims 2 to 6, further comprising:
generating the N first random numbers;
and executing the inverting operation on the N first random numbers to obtain the N second random numbers.
8. A register verification apparatus, comprising:
The verification module is used for: executing verification operation on N registers to be verified by using 2N random numbers which are generated randomly and are inconsistent with each other;
where N is an integer greater than 1, the verify operation is associated with at least one of a read operation and a write operation.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements a method of verifying a register as claimed in any one of claims 1 to 7 when the program is executed by the processor.
10. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a method of verifying a register according to any of claims 1 to 7.
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| CN202410205763.3A CN118013897A (en) | 2024-02-23 | 2024-02-23 | Register verification method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410205763.3A CN118013897A (en) | 2024-02-23 | 2024-02-23 | Register verification method and device |
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| CN202410205763.3A Pending CN118013897A (en) | 2024-02-23 | 2024-02-23 | Register verification method and device |
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