JP7528436B2 - Display devices and electronic devices - Google Patents

Description

The present invention relates to a display device and an electronic device.

Display devices using, for example, OLEDs (Organic Light Emitting Diodes) as display elements are known. In such display devices, pixel circuits including display elements and transistors are generally provided corresponding to the pixels of an image to be displayed. In addition, display devices are often required to have a smaller display size and higher resolution. In order to achieve both a smaller display size and higher resolution, it is necessary to miniaturize the pixel circuits, and therefore a technology has been proposed for integrating display devices on a semiconductor substrate such as silicon (see, for example, Patent Document 1).
Patent document 1 also describes that in order to reduce the number of circuits for supplying data signals to pixel circuits, such as latch circuits, data lines corresponding to pixel circuits are grouped (blocked) in groups of multiple lines and a latch circuit is provided for each group.

JP 2017-146535 A

However, in the above technology, if the power supply wiring to the circuit that supplies the data signal is inappropriate, it can cause malfunction.

A display device according to one aspect of the present disclosure is a display device having a display region, a data signal output circuit, and a plurality of terminals provided on a semiconductor substrate, the display region including a first pixel circuit corresponding to a first series of data lines and a second pixel circuit corresponding to a second series of data lines, the data signal output circuit including a latch circuit that latches first image data corresponding to the first pixel circuit and second image data corresponding to the second pixel circuit, the data signal output circuit converts the first image data latched by the latch circuit into an analog data signal and outputs it toward the first series of data lines, converts the second image data latched by the latch circuit into an analog data signal and outputs it toward the second series of data lines, and has a first power supply wiring that extends linearly from a first terminal of the plurality of terminals to a first end of both ends of the data signal output circuit, and a second power supply wiring that extends linearly from a second terminal of the plurality of terminals to a second end of both ends of the data signal output circuit.

1 is a perspective view showing a configuration of a display device according to a first embodiment. FIG. 2 is a block diagram showing a configuration of a display device. FIG. 2 is a circuit diagram showing a configuration of a main part of the display device. FIG. 2 is a diagram showing a configuration of a pixel circuit in a display device. 4 is a timing chart showing the operation of the display device. FIG. 2 is a diagram for explaining the operation of the display device. FIG. 2 is a diagram for explaining the operation of the display device. FIG. 2 is a diagram for explaining the operation of the display device. FIG. 2 is a diagram for explaining the operation of the display device. FIG. 2 is a plan view showing the arrangement of elements and wiring in the display device. FIG. 11 is a plan view showing the arrangement of elements and wiring of a display device according to a second embodiment. FIG. 1 is a perspective view showing a head mounted display using a display device. FIG. 2 is a diagram showing an optical configuration of a head mounted display. FIG. 1 is a plan view showing a display device according to a first comparative example. FIG. 11 is a plan view showing a display device according to a second comparative example.

The display device according to the embodiment of the present invention will be described below with reference to the drawings. Note that in each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present invention is not limited to these forms unless otherwise specified in the following description to the effect that the present invention is limited.

FIG. 1 is a perspective view showing the configuration of a display device 10 according to the first embodiment, and FIG. 2 is a block diagram showing the configuration of the display device 10. As shown in FIG.
The display device 10 is, for example, a micro display panel that displays color images in a head mounted display or the like, and has a plurality of pixel circuits and a drive circuit for driving the pixel circuits formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

The display device 10 is housed in a frame-shaped case 192 that opens in the display area, and one end of an FPC (Flexible Printed Circuits) board 194 is connected to it. The other end of the FPC board 194 is provided with a number of terminals 196 for connection to an external host device. The host device outputs image signals and synchronization signals for display on the display device 10 as differential signals, such as mini-LVDS (mini-Low Voltage Differential Signaling) format.

As shown in FIG. 2, the display device 10 includes an interface 15 , a control circuit 20 , a data signal output circuit 30 , a switch group 40 , an initialization circuit 50 , an auxiliary circuit 70 , a display area 100 and a scanning line driving circuit 120 .
In the display area 100, m rows of scanning lines 12 are arranged along the left-right direction in the figure, and (3q) columns of data lines 14b are arranged along the top-bottom direction and are electrically insulated from each other.
Here, m and q are integers equal to or greater than 2. As will be described later, pixel circuits are provided corresponding to intersections of the mth row of scanning lines 12 and the (3q)th column of data lines 14b.

The interface 15 receives the differential signal output from the higher-level device and restores it to an image signal Vid and a synchronization signal Sync. The interface 15 is a small-amplitude differential interface such as the above-mentioned mini-LVDS.
The control circuit 20 controls each unit based on the image signal Vid and the synchronization signal Sync restored by the interface 15. The image signal Vid supplied in synchronization with the synchronization signal Sync specifies the gradation level of the pixel in the image to be displayed, for example, by 8 bits for each of RGB. The synchronization signal Sync also includes a vertical synchronization signal that instructs the start of vertical scanning of the image signal Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the image signal.
The control circuit 20 generates control signals Gcp, Gref, Y_Ctr, /Gini, L_Ctr, S_Ctr, Sel(1) to Sel(q) and a clock signal Clk to control each unit. Although omitted in Fig. 2, the control circuit 20 outputs a control signal /Gcp which is the logical inverse of the control signal Gcp, and control signals /Sel(1) to /Sel(q) which are the logical inverse of Sel(1) to Sel(q).
The control circuit 20 also appropriately processes the image signal Vid, up-converts it to, for example, 10 bits, and outputs it as an image signal Vdat. The control circuit 20 includes a look-up table for converting the image signal Vid into the image signal Vdat, a register for storing various setting parameters, and the like.

The scanning line driving circuit 120 is a circuit for driving the pixel circuits arranged in m rows and 3q columns in units of one row in accordance with a control signal Y_Ctr.
The data signal output circuit 30 outputs a first data signal. In detail, the data signal output circuit 30 outputs the first data signal, which is a voltage according to the gradation level of a pixel represented by the pixel circuit, i.e., a pixel in an image to be displayed, and has a voltage amplitude before being compressed.
In this embodiment, the voltage amplitude of the first data signal output from the data signal output circuit 30 is compressed and supplied to the data line 14b as the second data signal. Therefore, the second data signal after compression also has a voltage corresponding to the gradation level of the pixel. In other words, the voltage of the data line 14b is a voltage corresponding to the gradation level of the pixel.
The data signal output circuit 30 also has a function of converting the serially supplied image signal Vdat into a parallel signal having multiple phases (in this example, three phases, which is the coefficient of q) and outputting the parallel signal.

The data signal output circuit 30 includes a shift register 31, a latch circuit 32, a D/A conversion circuit group 33, and an amplifier group .
The shift register 31 sequentially transfers the image signal Vdat supplied serially in synchronization with the clock signal Clk, and stores one row's worth, that is, (3q) pixel circuits' worth.

The latch circuit 32 latches the (3q) image signals Vdat stored in the shift register 31 in accordance with a control signal L_Ctr, converts the latched image signals Vdat into three-phase parallel signals in accordance with the control signal L_Ctr, and outputs the signals.
The D/A conversion circuit group 33 includes three D/A (Digital to Analog) converters. The three D/A converters convert the three-phase image signal Vdat output from the latch circuit 32 into an analog signal.
The amplifier group 34 includes three amplifiers. The three amplifiers amplify the three-phase analog signals output from the D/A conversion circuit group 33 and output them as first data signals Vd(1), Vd(2), and Vd(3).

The control circuit 20 outputs control signals Sel(1) to Sel(q) that are successively and exclusively at H level prior to the writing period, as described below. In this embodiment, the control circuit 20 outputs control signals Sel(1) to Sel(q) that are successively and exclusively at H level during the initialization period and compensation period of the horizontal scanning period.

FIG. 3 is a circuit diagram showing the configuration of the switch group 40, the initialization circuit 50, the auxiliary circuit 70, and the display area 100 of the display device 10. As shown in FIG.
In the display area 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. In detail, the pixel circuits 110 are arranged corresponding to the intersections of m rows of scanning lines 12 and (3p) columns of data lines 14b. Therefore, the pixel circuits 110 are arranged in a matrix of m rows by (3q) columns in the figure. Here, in order to distinguish the rows of the matrix arrangement, they may be called 1, 2, 3, ..., (m-1), m rows from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be called 1, 2, 3, ..., (3q-1), (3q) columns from the left in the figure.
2 and 3, the data lines 14b are grouped into groups of three columns. In order to generalize the groups, an integer j between 1 and q can be used to mean that the j-th group counting from the left includes the data lines 14b in the (3j-2)th, (3j-1)th, and (3j)th columns, a total of three columns.

The data line 14b in the (3j-2)th column is an example of a first series of data lines, and the data line 14b in the (3j-1)th column is an example of a second series of data lines.
In addition, of the m pixel circuits corresponding to the data line 14b in the (3j-2)th column, any one is an example of a first pixel circuit, and of the m pixel circuits corresponding to the data line 14b in the (3j-1)th column, any one is an example of a second pixel circuit.

The three pixel circuits 110 corresponding to the intersections of the scanning line 12 in the same row and the data lines 14b in three columns belonging to the same group correspond to R (red), G (green), and B (blue) pixels, respectively, and these three pixels represent one dot of the color image to be displayed. That is, in the first embodiment, the color of one dot is represented by additive color mixing using a total of three pixel circuits 110 corresponding to RGB.

The scanning line driving circuit 120 generates scanning signals for scanning the scanning lines 12 in sequence, row by row, in accordance with a control signal Y_Ctr. Here, the scanning signals supplied to the 1st, 2nd, 3rd, ..., (m-1) and mth scanning lines 12 are represented as /Gwr(1), /Gwr(2), ..., /Gwr(m-1) and /Gwr(m), respectively.
In addition to the scanning signals /Gwr(1) to /Gwr(m), the scanning line driving circuit 120 generates control signals synchronized with the scanning signals for each row and supplies them to the display area 100, but these are not shown in FIG. 3.

In the display device 10, data transfer lines 14a are provided corresponding to the data lines 14b.
The switch group 40 is a collection of capacitance elements 41 provided for each data transfer line 14a and transmission gates 45 provided for each data transfer line 14a.
Among these, the input terminals of the q transmission gates 45 corresponding to columns 1, 4, 7, ..., (3q-2) are commonly connected to each other. Note that the first data signal Vd(1) is supplied to this input terminal in time series for each pixel.
Furthermore, the input terminals of the q transmission gates 45 corresponding to the 2nd, 5th, 8th, . . . , (3q-1)th columns are commonly connected, and the first data signal Vd(2) is supplied in time series for each pixel.
Similarly, the input terminals of q transmission gates 45 corresponding to columns 3, 6, 9, . . . (3q) are commonly connected, and a first data signal Vd(3) is supplied in time series for each pixel.
The output terminal of the transmission gate 45 in a certain column is connected to one end of the data transfer line 14a of that column.

The three transmission gates 45 corresponding to columns (3j-2), (3j-1), and (3j) belonging to the jth group are turned on between the input terminal and the output terminal when the control signal Sel(j) is at H level (when the control signal /Sel(j) is at L level).
In addition, due to space limitations, only the first group and the qth group are shown in Fig. 3, and the other groups are omitted. Also, the transmission gate 45 in Fig. 3 is simplified and depicted as a simple switch in Fig. 2.

One end of the capacitive element 41 in a column is connected to one end of the data transfer line 14a corresponding to that column, and the other end of the capacitive element 41 is grounded to a constant potential, for example a reference potential of zero voltage.

The auxiliary circuit 70 is a collection of a transmission gate 72 provided for each column, an N-channel MOS transistor 73 provided for each column, and a capacitance element 75 provided for each column.
Here, the input terminal of the transmission gate 72 in a certain column is connected to the other end of the data transfer line 14a, and the output terminal of the transmission gate 72 in that column is connected to the drain node of the transistor 73 corresponding to that column and one terminal of the capacitive element 75 corresponding to that column.
In each column, a control signal Gref is supplied to the gate node of the transistor 73, and a voltage Vref is applied to the source node of the transistor 73.
The other end of the capacitive element 75 corresponding to a certain column is connected to one end of the data line 14b corresponding to that column.

The initialization circuit 50 is a collection of P-channel MOS transistors 56 arranged for each column. In each example, a control signal /Gini is supplied to the gate node of the transistor 56, and a voltage Vini is applied to the source node of the transistor 56. In addition, the drain node of the transistor 56 corresponding to a certain column is connected to the data line 14b corresponding to that column.

In this embodiment, one end of the data transfer line 14a is connected to the output terminal of the transmission gate 45 and one end of the capacitive element 41, and the other end of the data transfer line 14a is connected to the input terminal of the transmission gate 72. Since the display area 100 is located between the switch group 40 and the auxiliary circuit 70, the data transfer line 14a passes through the display area 100.
On the other hand, the first data signal supplied to the data transfer line 14a via the transmission gate 45 is supplied to the pixel circuit 110 as a second data signal via the transmission gate 72, the capacitive element 75, and the data line 14b.
As a result, the first data signal output from the data signal output circuit 30 travels via the data transfer line 14a to the auxiliary circuit 70 located on the opposite side of the display area 100, then turns around and becomes a second data signal, which is then supplied to the pixel circuit 110 via the data line 14b.

Figure 4 is a diagram showing the configuration of a pixel circuit 110. The pixel circuits 110 arranged in m rows (3q columns) are electrically identical to each other. For this reason, the pixel circuits 110 will be described by using one pixel circuit 110 in the i-th row that corresponds to a given column.

As shown in the figure, the pixel circuit 110 includes an OLED 130 , P-channel transistors 121 to 125 , and a capacitance element 132 .
In addition to the scanning signal /Gwr(i), control signals /Gel(i) and /Gcmp(i) are supplied to the pixel circuits 110 in the i-th row from the scanning line driving circuit 120.

The OLED 130 is an example of a display element, and has a light-emitting functional layer 216 sandwiched between a pixel electrode 213 and a common electrode 218. The pixel electrode 213 functions as an anode, and the common electrode 218 functions as a cathode. The common electrode 218 is optically transparent.
In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 216 to generate excitons, generating white light. The white light generated at this time resonates in an optical resonator composed of a reflective film and a half mirror (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors RGB. A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is visually recognized by an observer after being colored by the optical resonator and the color filter.

The OLED 130 provided in the pixel circuit 110 is the smallest unit of a display image. One pixel circuit 110 includes one OLED 130. A certain pixel circuit 110 is controlled independently of other pixel circuits 110, and the OLED 130 emits light in a color corresponding to the pixel circuit 110 to express one of the three primary colors.
That is, one pixel circuit 110 expresses one of the three primary colors among the colors to be displayed, and therefore, strictly speaking, it should be called a sub-pixel circuit, but for the sake of simplicity, it will be called a pixel circuit. Note that, when the display device 10 simply displays a monochromatic image of only light and dark, the above-mentioned color filter may be omitted.

In the transistor 121, the gate node is connected to the drain node of the transistor 122, the source node is connected to the power supply line 116 of the voltage Vel, and the drain node is connected to the source node of the transistor 123 and the source node of the transistor 124. In addition, in the capacitance element 132, one end is connected to the gate node of the transistor 121, and the other end is connected to a constant voltage, for example, the power supply line 116 of the voltage Vel. Therefore, the capacitance element 132 holds the voltage of the gate node g of the transistor 121.
As the capacitance element 132, a capacitance parasitic to the gate node of the transistor 121 may be used, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate may be used.

In the transistor 122 of the pixel circuit 110 in the i-th row and an arbitrary column, the gate node is connected to the scanning line 12 in the i-th row, and the source node is connected to the data line 14b of that column.
In the transistor 123 of the pixel circuit 110 in the i-th row and an arbitrary column, a control signal /Gcmp(i) is supplied to the gate node, and the drain node is connected to the data line 14b of that column.
In the transistor 124 of the pixel circuit 110 in the i-th row and an arbitrary column, a control signal /Gel(i) is supplied to the gate node, and the drain node is connected to the pixel electrode 213 which is the anode of the OLED 130 and the drain node of the transistor 125.
In the transistor 125 of the pixel circuit 110 in the i-th row and an arbitrary column, a control signal /Gcmp(i) is supplied to the gate node, and the source node is connected to the power supply line of the voltage Vorst.
The common electrode 218 functioning as the cathode of the OLED 130 is connected to a power supply line of a voltage Vct. Since the display device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to a potential equivalent to the voltage Vel, for example.

FIG. 5 is a timing chart for explaining the operation of the display device 10. As shown in FIG.
In the display device 10, rows are scanned in the order of 1, 2, 3, ..., m-th row over the period of one frame (F). In detail, as shown in the figure, the scanning signals /Gwr(1), /Gwr(2), ..., /Gwr(m-1), /Gwr(m) are sequentially and exclusively set to L level by the scanning line driving circuit 120 for each horizontal scanning period (H).
In this description, the period of one frame refers to the period required to display one frame of the image specified by the image signal Vid. If the length of the period of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, the period of one frame is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Also, in FIG. 5, the vertical scale indicating the voltage is not necessarily the same for each signal.

The operation during the horizontal scanning period (H) is common to the pixel circuits in the non-selected rows.
The operations of the pixel circuits 110 in the 1st to (3q)th columns of a row scanned in a certain horizontal scanning period (H) are also almost the same, so the following description will focus on the pixel circuit 110 in the i-th row and the (3j-2)th column.

In the first embodiment, the horizontal scanning period (H) is mainly divided into three periods: an initialization period (A), a compensation period (B), and a writing period (C). The operation of the pixel circuit 110 further includes a light emission period (D) in addition to the above three periods.
In each horizontal scanning period (H), in the initialization period (A), the control signal /Gini becomes L level, the control signal /Gref becomes H level, and the control signal Gcp becomes L level. In the compensation period (B), the control signal /Gini becomes H level, the control signal /Gref maintains H level, and the control signal Gcp maintains L level. In the writing period (C), the control signal /Gini maintains H level, the control signal /Gref becomes L level, and the control signal Gcp becomes H level.
The light emitting period (D) of the pixel circuit 110 in the i-th row refers to a period during which the control signal /Gel(i) is at the L level.

During the horizontal scanning period (H) in which the i-th row scanning line 112 is selected, the scanning signal /Gwr(i) goes to L level, so the transistor 122 in the i-th row pixel circuit 110 is turned on. Also, during this horizontal scanning period (H), the control signal /Gel goes to H level, so the transistor 124 in this pixel circuit 110 is turned off.

During the initialization period (A) of the horizontal scanning period (H), the control signal /Gini goes to the L level, turning on transistor 56, so that data line 14b, gate node g of transistor 121, one end of capacitance element 132, and the other end of capacitance element 75 are initialized to voltage Vini, as shown in FIG. 6. During the initialization period (A), the control signal /Gcmp(i) goes to the H level, turning off transistors 123 and 125. During the initialization period (A), the control signal Gref goes to the L level, turning on transistor 73, so that one end of capacitance element 75 is initialized to voltage Vref, as shown in FIG. 6.

Next, during the compensation period (B) of the horizontal scanning period (H) in which the i-th row scanning line 112 is selected, the control signal /Gcmp(i) becomes L level while the scanning signal /Gwr(i) is at L level. Therefore, in the pixel circuit 110 in the i-th row (3j-2) column, as shown in FIG. 7, the transistor 123 turns on while the transistor 121 is on. Therefore, the transistor 121 is in a state in which the gate node and the drain node are connected, that is, in a diode-connected state, and the voltage between the gate node and the source node of the transistor 121 converges to the threshold voltage of the transistor 121. Here, if the threshold voltage is denoted as Vth for convenience, the gate node g of the transistor 121 converges to a voltage (Vel-Vth) corresponding to the threshold voltage Vth.

In addition, during the compensation period (B), the gate node and drain node of transistor 121 are connected to data line 14b, so the voltage of data line 14b also becomes voltage (Vel-Vth). During the compensation period (B), the control signal Gref is at H level and transistor 73 is on, so that one end of capacitive element 75 becomes voltage Vref and the other end becomes voltage (Vel-Vth).

In addition, during the compensation period (B), the control signal /Gcmp(i) is at the L level, turning on transistor 125, so that the anode (pixel electrode) of OLED 130 is reset to voltage Vorst.

The control signals Sel(1) to Sel(q) are sequentially and exclusively at H level during the initialization period (A) and the compensation period (B). Note that, although omitted in Figures 5, 6 and 7, the control signals /Sel(1) to /Sel(q) are sequentially and exclusively at L level during the initialization period (A) and the compensation period (B) in synchronization with the control signals Sel(1) to Sel(q).
On the other hand, when, for example, the control signal Sel(j) among the control signals Sel(1) to Sel(q) becomes H level, the data signal output circuit 30 outputs the first data signals Vd(1) to Vd(3) of the three pixels corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14b belonging to the j-th group. More specifically, during the period when the control signal Sel(j) becomes H level, the data signal output circuit 30 outputs the first data signal Vd(1) corresponding to the pixel in the i-th row (3j-2) column, outputs the first data signal Vd(2) corresponding to the pixel in the i-th row (3j-1) column, and outputs the first data signal Vd(3) corresponding to the pixel in the i-th row (3j) column.
As a specific example, if j is "2", during a period in which the control signal Sel(2) is at the H level, the data signal output circuit 30 outputs a first data signal Vd(1) corresponding to the pixel in the i-th row and column 4, outputs a first data signal Vd(2) corresponding to the pixel in the i-th row and column 5, and outputs a first data signal Vd(3) corresponding to the pixel in the i-th row and column 6.

In this way, when the control signals Sel(1) to Sel(q) sequentially and exclusively become H level, the voltage of the first data signal corresponding to each pixel is held in the capacitive elements 41 corresponding to the first through (3q)th columns.
Note that FIG. 6 shows a state in which the control signal Sel(j) corresponding to the j-th group to which the pixel circuit 110 belongs becomes an H level in the initialization period (A), and the voltage of the first data signal Vd(1) is held in the capacitive element 41.
FIG. 7 also shows a state in which the control signal Sel(j) corresponding to the j-th group becomes H level in the compensation period (B) and the voltage of the first data signal Vd(1) is held in the capacitive element 41.

Next, during the horizontal scanning period (H) in which the i-th scanning line 112 is selected, the control signal /Gcmp(i) goes to H level while the scanning signal /Gwr(i) is at L level during the writing period (C). As a result, in the pixel circuit 110 in the i-th row (3j-2) column, the transistors 123 and 125 are turned off.
8, in the write period (C), the control signal Gref goes to the L level, so that the transistor 73 is turned off, and the control signal Gcp goes to the H level (the control signal /Gcp goes to the L level), so that the transmission gate 72 is turned on. As a result, one end of the capacitance element 75 changes from the voltage Vref to the voltage held in the capacitance element 41. This voltage change is transmitted to the data line 14b and the gate node g via the capacitance element 75.
Here, if the capacitance of the capacitance element 75 is Crf1 and the capacitance parasitic on the data line 14b is Cdt, the gate node g in the pixel circuit 110 changes from the voltage (Vel-Vth) by an amount obtained by multiplying the voltage change at one end of the capacitance element 75 by the ratio of the capacitance Crf1 to the sum of the capacitances Crf1 and Cdt, and the voltage of the gate node g after the change is held in the capacitance element 132.
The above ratio should take into consideration the capacitance of the capacitive element 132, but if the capacitance of the capacitive element 132 is sufficiently small compared with the capacitances Crf1 and Cdt, it can be ignored.

After the writing period (C) ends, the light emission period (D) begins. That is, after the selection of the i-th row scanning line 12 ends, when the light emission period (D) begins, the control signal /Gel(i) is inverted to the L level, and the transistor 124 is turned on. Therefore, a current corresponding to the voltage Vgs held by the capacitance element 132 flows through the OLED 130, and the OLED 130 emits light with a luminance corresponding to the current.
5 shows an example in which the light emission period (D) continues after the selection of the i-th row scanning line 12 is completed, but the period during which the control signal /Gel(i) is at the L level may be intermittent, or may be adjusted according to the brightness adjustment. The level of the control signal /Gel(i) in the light emission period (D) may be increased from the L level in the compensation period (B). In other words, the level of the control signal /Gel(i) in the light emission period (D) may be a level between the H level and the L level.

In the pixel circuit 110 of interest, the gate-source voltage Vgs during the writing period (C) and the light emission period (D) is a voltage that is changed from the threshold voltage Vth during the compensation period (B) according to the gradation level of the pixel circuit 110, as described above. Similar operations are performed in the other pixel circuits 110, so in the first embodiment, a current according to the gradation level flows through the OLED 130 in a state in which the threshold voltages of the transistors 121 are compensated across all pixel circuits 110 in the mth row (3q) column. Therefore, in the first embodiment, the luminance variation is reduced, making it possible to display a high quality image.

Note that in Figures 6 to 9, the areas in which the switch group 40 and the initialization circuit 50 are provided are not particularly distinguished.

The electrical configuration of the display device 10 is as described above. Next, we will explain points to note about the wiring from a specific terminal among the multiple terminals 180 to each element in the display device 10, particularly the power supply wiring.

FIG. 10 is a plan view showing the positions of the elements and power supply wiring in the display device 10 according to the first embodiment.
The display device 10 is rectangular because it is diced from a wafer-like semiconductor substrate. For the sake of convenience, the upper side of the rectangular display device 10 is designated by the symbol U, the lower side by the symbol D, the left side by the symbol L, and the right side by the symbol R, as shown in the figure.
An auxiliary circuit 70 is provided between the upper side U and the display area 100. Furthermore, a scanning line driving circuit 120 is provided between the left side L and the display area 100, as indicated by a dashed line. A plurality of terminals 180, an interface 15, a data signal output circuit 30, a switch group 40, and an initialization circuit 50 are provided between the lower side D and the display area 100, in this order from the lower side D.
The multiple terminals 180 are provided along the lower side D, specifically along the horizontal direction in the figure.

The capacitive element 41 and the transmission gate 45 in the switch group 40 are provided corresponding to the data transfer line 14a, so in the figure, the horizontal length of the switch group 40 is approximately the same as the length of the display area 100. Similarly, the transistor 56 in the initialization circuit 50 is provided corresponding to the data line 14b, so in the figure, the horizontal length of the initialization circuit 500 is approximately the same as the length of the display area 100.
On the other hand, the data signal output circuit 30 does not correspond to the data transfer line 14a, and is therefore arranged toward the left in the figure. When the data signal output circuit 30 is arranged toward the left, an empty space is generated to the right of the data signal output circuit 30. In the first embodiment, the control circuit 20 is provided in this empty space. The interface 15 is provided between the multiple terminals 180 and the data signal output circuit 30, in the vicinity of the control circuit 20.

In FIG. 2 and FIG. 3, for convenience of explanation, the total number of data lines 14b is set to "3q",
In the above description, the number of groups is q, and the number of phases of parallel conversion is 3. To be more specific, the following description will be given assuming that the total number of data lines 14b is 5760 (=1920×3), the number of groups is 24, and the number of phases of parallel conversion is 240.
The data signal output circuit 30 includes a shift register 31, a latch circuit 32, a D/A conversion circuit group 33, and an amplifier group 34. Of these, the D/A converters in the D/A conversion circuit group 33 and the amplifiers in the amplifier group 34 are provided corresponding to the parallel-converted phases, so the number of D/A converters and the number of amplifiers are also "240." The D/A converters and amplifiers in the data signal output circuit 30 are each arranged in the horizontal direction, and in accordance with this arrangement, the unit circuits of the shift register 31 and the unit circuits of the latch circuit 32 are also arranged in the horizontal direction.

In other words, if the number of phases of parallel conversion is 240, the number of sets of unit circuits of the shift register 31, unit circuits of the latch circuit 32, amplifiers, and D/A converters will also be 240, and these 240 sets of circuits will be arranged side by side in the horizontal direction.
It should be noted that the unit circuit of the shift register 31 refers to a circuit that is cascaded to sequentially transfer the image signal Vdat, and the unit circuit of the latch circuit 32 refers to a circuit for storing one pixel of the image signal Vdat transferred by the shift register 31.

In the figure, if power to the data signal output circuit 30 extending in the horizontal direction is configured to be supplied to either the left or right, a voltage drop occurs on the other side. For this reason, in the first embodiment, power to the data signal output circuit 30 is configured to be supplied to both the left and right ends. Specifically, power to the data signal output circuit 30 is configured to be supplied via a line Lna extending linearly from one specific terminal 180a and a line Lnb extending linearly from another specific terminal 180b.
More specifically, the wiring Lna branches rightward, for example, into four, as indicated by solid lines in the figure, and the four branched wirings extend rightward along the regions of the shift register 31, the latch circuit 32, the D/A conversion circuit group 33, and the amplifier group 34. Similarly, the wiring Lnb branches leftward, for example, into four, and the four branched wirings extend rightward along the regions of the shift register 31, the latch circuit 32, the D/A conversion circuit group 33, and the amplifier group 34, and are each connected to the wirings branched from the wiring Lna.
The arrangement direction of the multiple terminals 180 is aligned with the left-right direction of the data signal output circuit 30. Specifically, the multiple terminals 180 are arranged along the bottom side D, and the left-right direction, which is the longitudinal direction of the data signal output circuit 30, is also aligned with the bottom side D. For this reason, the length of the wiring Lna extending in a straight line from the terminal 180a to the left end of the data signal output circuit 30 and the length of the wiring Lnb from the terminal 180b to the right end of the data signal output circuit 30 are approximately the same.
Therefore, if the line width is the same, the resistance of the line Lna and the resistance of the line Lnb are also approximately the same. Note that the length of the line refers to the distance from the terminal 180 to the data signal output circuit 30, excluding the connection portion with the FPC board 194, and the line width refers to the distance in the direction perpendicular to the extension direction.

Power to the control circuit 20 is also supplied from both the left and right ends. Specifically, power to the control circuit 20 is supplied via a line Lnc extending linearly from one terminal 180c and a line Lnd extending linearly from another terminal 180d.
Since the length of the wiring Lnc is approximately the same as the length of the wiring Lnd, if the line width is the same, the resistance of the wiring Lnc is approximately the same as the resistance of the wiring Lnd.

Similarly, power is supplied to the interface 15 from both the left and right ends. Specifically, power is supplied to the interface 15 via a line Lne extending linearly from one terminal 180e and a line Lnf extending linearly from another terminal 180f.
Since the length of the wiring Lne and the length of the wiring Lnf are approximately the same, if the line width is the same, the resistance of the wiring Lne and the resistance of the wiring Lnf will be approximately the same.

In the first embodiment, a built-in power supply is provided at each of the four corners of the display area 100. In detail, in the figure, a built-in power supply PUL is provided at the upper left end of the display area 100, a built-in power supply PUR is provided at the upper right end, a built-in power supply PDL is provided at the lower left end, and a built-in power supply PDR is provided at the lower right end. Of these, the built-in power supply PUL supplies a voltage Vref to the left end of the auxiliary circuit 70, and the built-in power supply PUR supplies a voltage Vref to the right end of the auxiliary circuit 70. Therefore, the auxiliary circuit 70 is supplied with the voltage Vref from both the left and right ends.
The built-in power supply PDL supplies the voltage Vini to the left end of the initialization circuit 50, and the built-in power supply PDR supplies the voltage Vini to the right end of the initialization circuit 50. Therefore, the voltage Vini is supplied to the initialization circuit 50 from both the left and right ends.

The built-in power supply PDL generates the voltage Vini using as its source a voltage supplied via a line Lng that extends linearly from a terminal 180g of the multiple terminals 180. The built-in power supply PDR generates the voltage Vini using as its source a voltage supplied via a line Lnh that extends linearly from a terminal 180h of the multiple terminals 180.
The role of the built-in power supplies PDL and PDR is to suppress the voltage drop at the other end of the voltage Vini, compared to a configuration in which the voltage Vini is supplied from either the left or right end. For this reason, one of the built-in power supplies PDL and PDR may be designated as the main power supply and the other as the slave power supply, with the voltage Vini being supplied from the main power supply and a voltage compensating for the shortage due to the voltage drop being supplied from the slave power supply. Whether one of the built-in power supplies PDL and PDR is the main power supply and the other is the slave power supply is determined by, for example, the control circuit 20, and the control of the slave power supply is set by, for example, rewriting the stored value of a register in the control circuit 20. In addition, a capacitance element for stabilization (smoothing) is provided in the main built-in power supply.

Although wiring to the built-in power supplies PUL and PUR is not particularly shown, the voltage Vref is generated using as a power supply the voltage supplied via the terminal 180. Note that the built-in power supplies PUL and PUR may generate the voltage Vref using as a power supply the voltage supplied via wiring that is an extension of the wiring Lng and Lnh, for example.
The role of the built-in power supplies PUL and PUR is to supply the voltage Vref from both the left and right ends, suppressing the voltage drop at the other end compared to a configuration in which the voltage Vref is supplied from one of the left and right ends. For this reason, the built-in power supplies PUL and PUR may also be configured so that one of them is the main power supply and the other is the slave power supply, with the main power supply supplying the voltage Vref and the slave power supply supplying a voltage that compensates for the shortage due to the voltage drop. Whether one of the built-in power supplies PUL and PUR is the main power supply and the other is the slave power supply is determined by, for example, the control circuit 20, and the control of the slave power supply is set by, for example, rewriting the stored value of a register in the control circuit 20.

FIG. 14 is a diagram showing a first comparative example for explaining the effect of the power supply wiring in the first embodiment.
In the first comparative example, the interface 15 is located near the control circuit 20, so that the length from the terminal 180b of the wiring Lnb to the right end of the data signal output circuit 30 is longer than that of the wiring Lna and the resistance is also larger in order to avoid the interface 15. Similarly, the length from the terminal 180c of the wiring Lnc to the left end of the control circuit 20 is longer than that of the wiring Lnd in order to avoid the interface 15, and the resistance is also larger.
In the data signal output circuit 30, when the resistance of the wiring Lnb becomes larger than the resistance of the wiring Lna, the power supply voltage becomes uneven when viewed horizontally in the figure. When the power supply voltage becomes uneven in the data signal output circuit 30, in the analog system, differences occur in the output of the D/A converter and the output of the amplifier, leading to display unevenness, and in the digital system, a transfer error occurs in the shift register 31, causing a latch malfunction in the latch circuit 32.
In the control circuit 20, if the power supply voltages are uneven when compared between the left end and the right end, this will affect the look-up table (RAM), registers, etc., causing malfunctions.
Furthermore, since the interface 15 consumes more power than the control circuit 20 and the data signal output circuit 30, if it is provided in a position that interferes with other circuits or the power supply wiring to those circuits, this may cause malfunctions.

In contrast, in the first embodiment shown in Fig. 10, in the data signal output circuit 30, the length of the wiring Lna is approximately the same as the length of the wiring Lnb, and the resistance of the wiring Lna is also approximately the same as the resistance of the wiring Lnb, so that the power supply voltage is equalized on the left and right. Therefore, in the analog system, the difference in the output of the D/A converter and the amplifier is reduced, so that display unevenness is suppressed. Also, in the digital system, transfer errors and latch malfunctions are suppressed.
In the control circuit 20, the length of the wiring Lnc is approximately the same as the length of the wiring Lnd, and the resistance of the wiring Lnc is also approximately the same as the resistance of the wiring Lnd, so that the power supply voltage is equalized on the left and right sides, thereby suppressing malfunctions in the control circuit 20.
Furthermore, the interface 15 is provided between the data signal output circuit 30 and the multiple terminals 180, and is provided at a position that does not interfere with the wirings Lnb and Lnc, which are power supply wirings for other circuits, thereby suppressing the occurrence of operational malfunctions.

Here, assuming that the difference between the H level and L level of the logic signal in the display device 10 in the first embodiment is 1.8V and that the interface 15, the control circuit 20, or the data signal output circuit is configured to flow at peak times of approximately 200mA, if the difference in the power supply voltage is within 0.4V, then malfunction of the logic circuit can be suppressed. Conversely, if the resistance of each of the wirings Lna, Lnb, Lnc, Lnd, Lne, and Lnf is 2Ω or less, the difference in the power supply voltage can be kept within 0.4V.

Next, we will explain the display device 10 according to the second embodiment.

FIG. 11 is a plan view showing the positions of the elements and power supply wiring in a display device 10 according to the second embodiment.
10, it is assumed that the total number of data lines 14b is "5760" and the number of phases of parallel conversion is "240", but in the second embodiment, it is assumed that the total number of data lines 14b is reduced to 1/3, "1920", while maintaining the size of the display area 100 and maintaining the number of groups at "24". In this case, the number of phases of parallel conversion becomes "80", so in FIG. 11, the horizontal size of the data signal output circuit 30 is shortened compared to FIG. 10.

In addition, because the total number of data lines 14b has been reduced to one-third, the amount of data per unit time supplied from the higher-level device is also reduced to one-third. As a result, the interface 15 is also made smaller than that shown in FIG. 10. Therefore, the interface 15 can be positioned between the control circuit 20 and the multiple terminals 180 so that it fits within the horizontal size of the control circuit 20.

FIG. 15 is a diagram showing a second comparative example for explaining the effect of the power supply wiring in the second embodiment.
Since the horizontal size of the data signal output circuit 30 is shortened, an empty space is generated between the control circuit 20 and the data signal output circuit 30. The second comparative example is an example in which the built-in power supply PDR is disposed in this empty space.
However, in this example, the voltage output from the built-in power supply PDR is supplied to the initialization circuit 50 via wiring along the left and top sides of the control circuit 20, as shown by the thick arrows in the figure, and is therefore susceptible to the effects of the wiring. Also, in this example, there is no space to the left of the data signal output circuit 30, so the built-in power supply PDL cannot be provided, and the initialization circuit 50 is only supplied to the right end, and is affected by voltage drops at the left end.
It should be noted that the wiring from one terminal 180 to the built-in power supply PDR is omitted.

In contrast, in the second embodiment shown in FIG. 11, the control circuit 20 and the data signal output circuit 30 are moved to the center, and free space is provided to the left of the data signal output circuit 30 and to the right of the control circuit 20, with the built-in power supply PDL provided in the free space to the left of the data signal output circuit 30 and the built-in power supply PDR provided in the free space to the right of the control circuit 20.

In the display device 10 according to the second embodiment, the voltage Vini is supplied to the initialization circuit 50 from both the left and right ends by the built-in power supplies PDL and PDR, so degradation of display quality due to voltage drops is suppressed.

<Modifications, Applications, etc.>
The above-described embodiment can be applied or modified as follows.

In the example of FIGS. 2 and 3, three data lines 14b, equal to the number of phases, are selected in turn for each group, and the first data signals Vd(1) to Vd(3) output from the data signal output circuit 30 are sampled by the transmission gate 45 of the selected column and held in the capacitance element 41.
Since the path length from the data signal output circuit 30 to the input terminal of the transmission gate 45 differs for each group, even if the same voltage is output from the data signal output circuit 30, the voltage held in the capacitive element 41 may differ, which may affect the display.
Therefore, the control circuit 20 may be configured to output a correction value for each group selected, that is, to output a correction value in accordance with the number “j” of the control signal Sel that is to be set to the H level among the control signals Sel(1)-Sel(q), and the data signal output circuit 30 may be configured to correct the first data signals Vd(1)-Vd(3) in accordance with the correction value.

The power supply wiring actually includes high-level wiring and low-level wiring, and the low-level wiring may be common to, for example, the ground potential.
In the above embodiment, an example has been shown in which conversion to 3 phases, 80 phases, or 240 phases is performed by serial-parallel conversion, but the number of phases may be two or more.
In the display device 10, the threshold value of the transistor 121 in the pixel circuit 110 is compensated for, but the display device 10 may be configured not to compensate, specifically, to omit the transistor 123.
In the embodiment, the OLED 130 has been described as an example of a display element, but other display elements may be used. For example, a liquid crystal element may be used as the display element. The liquid crystal element may also be formed on a semiconductor substrate such as a silicon substrate. In this case, too, a serial-parallel converted data signal is applied to the liquid crystal element via a capacitive element.
The channels of the transistors 56, 73, and 121 to 125 are not limited to those in the embodiment. The transistors 56, 73, and 121 to 125 may be replaced with transmission gates as appropriate. Conversely, the transmission gates 45 and 72 may be replaced with single-channel transistors.

<Electronic devices>
Next, an electronic device to which the display device 10 according to the embodiment is applied will be described. The display device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

FIG. 12 is a diagram showing the appearance of a head mounted display, and FIG. 13 is a diagram showing its optical configuration.
First, as shown in Fig. 12, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. In addition, as shown in Fig. 13, the head mounted display 300 has a display device 10L for the left eye and a display device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure).
The image display surface of the display device 10L is disposed to the left in FIG. 13. As a result, the image displayed by the display device 10L is output in the direction of 9 o'clock in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the display device 10L in the direction of 6 o'clock, while transmitting light incident from the direction of 12 o'clock. The image display surface of the display device 10R is disposed to the right, opposite the display device 10L. As a result, the image displayed by the display device 10R is output in the direction of 3 o'clock in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the display device 10R in the direction of 6 o'clock, while transmitting light incident from the direction of 12 o'clock.

In this configuration, a person wearing the head mounted display 300 can observe the images displayed by the display devices 10L and 10R in a see-through state in which the images are superimposed on the outside world.
Furthermore, in this head mounted display 300, when an image for the left eye is displayed on display device 10L and an image for the right eye is displayed on display device 10R, among the binocular images with parallax, the wearer can perceive the displayed image as if it has depth and a three-dimensional effect.

In addition, electronic devices including the display device 10 can be applied to electronic viewfinders in video cameras and digital cameras with interchangeable lenses, in addition to the head-mounted display 300.

<Additional Notes>
A display device according to one aspect (aspect 1) is a display device having a display area, a data signal output circuit, and a plurality of terminals provided on a semiconductor substrate, the display area including first pixel circuits corresponding to a first series of data lines and second pixel circuits corresponding to a second series of data lines, the data signal output circuit including a latch circuit that latches first image data corresponding to the first pixel circuits and second image data corresponding to the second pixel circuits, the data signal output circuit converts the first image data latched by the latch circuit into an analog data signal, amplifies the data signal, and outputs the data signal toward the first series of data lines, and converts the second image data latched by the latch circuit into an analog data signal, amplifies the data signal, and outputs the data signal toward the second series of data lines, a first power supply wiring extending in a straight line from a first terminal of the plurality of terminals to a first end of the data signal output circuit, and a second power supply wiring extending in a straight line from a second terminal of the plurality of terminals to a second end of the data signal output circuit.
According to this embodiment, power is supplied to both ends of the data signal output circuit via the first power supply wiring and the second power supply wiring. The first power supply wiring extends linearly from the first terminal, and the second power supply wiring extends linearly from the second terminal, so that the resistances are low and almost the same. This makes it possible to suppress display unevenness and malfunctions caused by a voltage drop at either one of the ends in the data signal output circuit.
The line Lna is an example of a first power supply line, and the line Lnb is an example of a second power supply line. The terminal 180a is an example of a first terminal, and the terminal 180b is an example of a second terminal.
Here, the term "linear" does not only mean a straight line, but also means that slight curves or slight bends are acceptable as long as they are within a range where the above-mentioned low resistance can be obtained and no malfunction occurs. Specifically, this should be expressed in the form of a resistance value within a certain number of Ω, but since the range where no malfunction occurs varies depending on the amplitude difference of the logic signal (1.8 V, 3.3 V, 5.0 V) and the circuit conditions, it is not something that can be specified by a specific numerical value.
Moreover, outputting from A to B includes the presence of one or more intermediate elements between two elements A and B. For example, when the data signal output circuit 30 outputs the analog first data signal Vd(1) to the data line 14b, this includes the fact that the transmission gates 45, 72 and the capacitive element 75 may be present as intermediate elements when the first data signal Vd(1) is output to the data line 14b.

In the display device according to a specific aspect (aspect 2) of aspect 1, the direction in which the plurality of terminals are arranged is aligned with a direction connecting both ends of the data signal output circuit.
According to this aspect, the direction in which the multiple terminals are arranged is aligned with the direction connecting both ends of the data signal output circuit, so that the length of the first power supply wiring and the length of the second power supply wiring are substantially the same.

A display device according to a specific aspect (aspect 3) of aspect 1 or aspect 2 includes a control circuit that supplies the first image data and the second image data to the data signal output circuit, and has a third power supply wiring that extends in a straight line from a third terminal of the plurality of terminals to a first end of both ends of the control circuit, and a fourth power supply wiring that extends in a straight line from a fourth terminal of the plurality of terminals to a second end of both ends of the control circuit.
According to this aspect, power is supplied to both ends of the control circuit via the third power supply wiring and the fourth power supply wiring, and since the third power supply wiring and the fourth power supply wiring have low resistance and substantially the same resistance, it is possible to suppress the occurrence of malfunctions in the control circuit due to a voltage drop at one of the ends.
The line Lnc is an example of a third power supply line, and the line Lnd is an example of a fourth power supply line. The terminal 180c is an example of a third terminal, and the terminal 180d is an example of a fourth terminal.

A display device according to a specific aspect (aspect 4) of any of aspects 1 to 4 includes an interface that receives a signal from an external device and outputs it to the control circuit, and has a fifth power supply wiring that extends in a straight line from a fifth terminal of the plurality of terminals to a first end of both ends of the interface, and a sixth power supply wiring that extends in a straight line from a sixth terminal of the plurality of terminals to a second end of both ends of the interface.
According to this embodiment, power is supplied to both ends of the control circuit via the fifth power supply wiring and the sixth power supply wiring, and since the fifth power supply wiring and the sixth power supply wiring have low resistance and substantially the same resistance, it is possible to suppress the occurrence of malfunction due to a voltage drop at one of the ends at the interface.
The line Lne is an example of a fifth power supply line, and the line Lnf is an example of a sixth power supply line. The terminal 180e is an example of a fifth terminal, and the terminal 180f is an example of a sixth terminal.

An electronic device according to a specific aspect (aspect 5) of aspects 1 to 4 has a display device according to any of the above aspects. According to this aspect, malfunctions in a miniaturized display device are suppressed.

10...display device, 12...scanning line, 14a...data transfer line, 14b...data line, 20...control circuit, 30...data signal output circuit, 31...shift register, 32...latch circuit, 33...D/A conversion circuit group, 34...amplifier group, 45, 72...transmission gate, 61, 75...capacitive element, 100...display area, 110...pixel circuit, 12...scanning line, 121-125...transistor, 130...OLED, 300...head mounted display.

Claims (3)

A display device including a rectangular semiconductor substrate, the display region, a data signal output circuit, a control circuit for supplying image data to the data signal output circuit, an interface for outputting a signal from an external device to the control circuit, and a plurality of terminals,
The display area is
a first pixel circuit corresponding to a first series of data lines;
a second pixel circuit corresponding to a second series of data lines;
Including,
The data signal output circuit includes:
a latch circuit that latches first image data, which is the image data corresponding to the first pixel circuit, and second image data, which is the image data corresponding to the second pixel circuit, converting the first image data latched by the latch circuit into an analog data signal and outputting it toward the first group of data lines, and converting the second image data latched by the latch circuit into an analog data signal and outputting it toward the second group of data lines,
The plurality of terminals are arranged in a first direction along one side of the rectangle ,
a first power supply wiring that extends linearly from a first terminal of the plurality of terminals to a first end of the data signal output circuit;
a second power supply wiring that extends linearly from a second terminal of the plurality of terminals to a second end of the data signal output circuit;
a third power supply wiring extending linearly from a third terminal of the plurality of terminals to a first end of the control circuit;
a fourth power supply wiring extending linearly from a fourth terminal of the plurality of terminals to a second end of the control circuit;
a fifth power supply wiring extending linearly from a fifth terminal of the plurality of terminals to a first end of the interface;
a sixth power supply wiring extending linearly from a sixth terminal of the plurality of terminals to a second end of the interface;
having
the data signal output circuit and the control circuit are disposed at positions not overlapping each other when viewed from a second direction along a side perpendicular to the one side ,
When viewed from the second direction, the interface is disposed between one of the data signal output circuit and the control circuit and the multiple terminals, at a position overlapping with either one of the data signal output circuit and the control circuit, and is disposed at a position not overlapping with any of the first terminal, the second terminal, the third terminal, and the fourth terminal, the first power supply wiring, the second power supply wiring, the third power supply wiring, and the fourth power supply wiring.
Display device.
The first direction;
The display device according to claim 1 , wherein the direction of the data signal output circuit is aligned with a direction connecting both ends of the data signal output circuit.
3. An electronic device comprising the display device according to claim 1.

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