JP2024117945A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumed by parasitic capacitance of a data line in an electro-optic device.

SOLUTION: A pixel circuit 110 includes an OLED that emits light with luminance corresponding to a current flowing from an anode to a cathode and a transistor that allows a current corresponding to a voltage between a gate node and a source node to flow to the OLED. A control circuit 30 supplies a potential corresponding to a gradation level to the gate node via a data line 14 in a writing period and performs first operation and second operation according to the gradation level in a first initialization period before the writing period. The first operation is the operation of supplying a potential Vorst via the data line 14, and the second operation is the operation of setting the potential of the data line 14 and the potential of the anode to a second potential between a potential Vel and the potential Vorst.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to an electro-optical device and an electronic device.

In recent years, various electro-optical devices (display devices) using light-emitting elements such as organic light-emitting diodes (OLEDs) have been proposed. In electro-optical devices, pixel circuits including the light-emitting elements and driving transistors are typically provided at intersections between scanning lines and data lines, corresponding to the pixels of the image to be displayed.

In such a configuration, when a data signal having a potential corresponding to the grayscale level of a pixel is supplied to the gate node of the driving transistor, the driving transistor supplies a current corresponding to the voltage between the gate node and the source node to the light-emitting element, causing the light-emitting element to emit light with a brightness corresponding to the grayscale level.
A pixel circuit having four transistors including a drive transistor is known (see, for example, Japanese Patent Application Laid-Open No. 2003-233663).

JP 2021-179628 A

When electro-optical devices are miniaturized and applied to portable devices, there is a strong demand for low power consumption due to battery and other factors. However, the above configuration has the problem that it does not achieve sufficient low power consumption.

In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a pixel circuit provided in correspondence with a data line and a scanning line, and a control circuit that controls the pixel circuit, the pixel circuit includes a light-emitting element having two electrodes and emitting light with a luminance corresponding to a current flowing between the two electrodes, and a drive transistor that flows a current corresponding to a voltage between a gate node potential and a source node potential to the light-emitting element, the control circuit supplies a potential corresponding to a gradation level to the gate node via the data line during a writing period, and executes a first operation or a second operation according to the gradation level during a first initialization period prior to the writing period, the first operation being an operation of supplying a first potential different from the potential corresponding to the gradation level to one of the two electrodes via the data line, and the second operation being an operation of setting the potential of the data line and the potential of the one electrode to a second potential between the first potential and an off potential that turns the drive transistor into an off state.

1 is a perspective view of an electro-optical device according to a first embodiment. FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. 4 is a timing chart showing the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 1 is an example of a display screen for illustrating the advantages of an electro-optical device. FIG. 11 is a block diagram showing an electrical configuration of an electro-optical device according to a second embodiment. 4 is a timing chart showing the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. FIG. 2 is a diagram showing an optical configuration of a head mounted display.

The electro-optical device according to the embodiment will be described below with reference to the drawings. Note that in each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

FIG. 1 is a perspective view showing an electro-optical device 10 according to a first embodiment. The electro-optical device 10 is a micro display panel that displays an image, for example, in a head-mounted display. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit that drives the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display area 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane determined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of the light emitted from the OLED.

2 is a block diagram showing an electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an auxiliary circuit 60, n capacitive elements 70, an initialization circuit 80, a display area 100, and a scanning line driving circuit 120.
In the display region 100, m rows of scanning lines 12 are provided along the X direction in the drawing, and n columns of data lines 14 are provided along the Y direction and are electrically insulated from each other of the scanning lines 12. Note that m and n are integers of 2 or more.

In the display region 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure.
An integer i between 1 and m inclusive is used to generally describe the scan lines 12. Similarly, an integer j between 1 and n inclusive is used to generally describe the data lines 14.

The control circuit 30 controls each section based on video data Vid and a synchronous signal Sync supplied from a host device. The video data Vid specifies the gradation level of a pixel in an image to be displayed, for example, in 8 bits.
The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one.
The brightness characteristics indicated by the gradation level in the video data Vid supplied from the host device do not necessarily match the luminance characteristics of the OLED included in the pixel circuit 110. Therefore, in order to cause the OLED to emit light at a luminance corresponding to the gradation level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in this embodiment and outputs the up-converted data as the video data Vdata. Therefore, the gradation level is also specified for the 10-bit video data Vdata. In other words, the video data Vdata specifies the gradation level obtained by converting the gradation level specified by the video data Vid.

For up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of input video data Vid and the 10 bits of output video data Vdata. The control circuit 30 also generates various control signals to control each section, as will be described in detail later.

The scanning line driving circuit 120 is a circuit that outputs various signals to drive the pixel circuits 110 arranged in m rows and n columns, row by row, according to the control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals /Gwr(1), /Gwr(2), ..., /Gwr(m-1), /Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), mth scanning lines 12 in order. In general, the scanning signal supplied to the ith scanning line 12 is represented as /Gwr(i). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals /Gwr(1) to /Gwr(m), but details will be described later.

The data signal output circuit 50 is a circuit that outputs a voltage signal according to the luminance to the pixel circuits 110 located in the row selected by the scanning line driving circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, n DA conversion circuits 500, and n determination circuits 510.
The selection circuit group 52 includes a selection circuit 520 having a one-to-one correspondence with the n columns, the first latch circuit group 54 includes a first latch circuit L1 having a one-to-one correspondence with the n columns, and the second latch circuit group 56 includes a second latch circuit L2 having a one-to-one correspondence with the n columns. In addition, the n DA conversion circuits 500 and the n determination circuits 510 have a one-to-one correspondence with the n columns.

That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, a DA conversion circuit 500, and a judgment circuit 510 is provided corresponding to each example. Here, the jth column selection circuit 520 instructs the jth column first latch circuit L1 to select the jth column video data from the video data Vdata output from the control circuit 30, and the jth column first latch circuit L1 latches the video data Vdata according to the instruction. The jth column second latch circuit L2 outputs the video data Vdata latched by the jth column first latch circuit L1 to the jth column DA conversion circuit 500 in a writing period (C) described later, according to the control of the control circuit 30, and outputs it to the jth column judgment circuit 510 in an initialization period (A2).

The jth column DA conversion circuit 500 converts the 10-bit video data Vdata output from the jth column second latch circuit L2 into an analog signal and outputs it to the jth column data signal output line 14c. In other words, the data signal output line 14c is provided in one-to-one correspondence with the data line 14, and the output terminal of the jth column DA conversion circuit 500 is connected to the jth column data signal output line 14c.

The j-th column determination circuit 510 determines the gradation level specified by the video data Vdata output from the j-th column second latch circuit L2, and outputs a control signal /Yr(j) according to the determination result. Note that the control signal /Yr(j) is a generalized representation of the control signals /Yr(1), /Yr(2), ..., /Yr(n-1), /Yr(n) that are supplied in order corresponding to the 1st, 2nd, ..., (n-1), nth columns.
If the grayscale level is the highest grayscale white level (brightest level), the jth column decision circuit 510 outputs the control signal /Yr(j) at H level throughout the entire horizontal scanning period (H) described below. If the grayscale level is other than the white level, the jth column decision circuit 510 outputs the control signal /Yr(j) at L level during the initialization period (A2) of the horizontal scanning period (H) and at H level during the other periods.

The auxiliary circuit 60 is a collection of transistors 62 arranged in one-to-one correspondence with the data signal output lines 14c. The source node of the transistor 62 corresponding to the jth column is connected to a power supply line of potential Vref, and the drain node of the transistor 62 is connected to the data signal output line 14c of the jth column. In addition, a control signal /Gref output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

The n capacitance elements 70 are provided in one-to-one correspondence with pairs of data signal output lines 14c and data lines 14. In detail, one end of the capacitance element 70 in the jth column is connected to the data signal output line 14c in the jth column, and the other end of the capacitance element 70 in the jth column is connected to the data line 14 in the jth column.
The video data Vdata corresponds to a gradation level specified by the video data Vid, and the DA conversion circuit 500 converts the video data Vdata into an analog signal, which is supplied as a data signal to the data line 14 via the capacitive element 70. Therefore, the potential of the data signal supplied to the data line 14 corresponds to the video data Vid and the gradation level specified by the video data Vdata.

The initialization circuit 80 is a collection of pairs of transistors 82 , 84 and 86 provided in one-to-one correspondence with the data lines 14 .
A source node of the transistor 82 corresponding to the jth column is connected to a power supply line of potential Vel, and a drain node of the transistor 82 is connected to the jth column data line 14. A control signal /Drst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 82 in each column. The potential Vel is used as a high-level potential of the power supply voltage.

The source node of the transistor 84 corresponding to the jth column is connected to a power supply line of potential Vini, and the drain node of the transistor 84 is connected to the data line 14 of the jth column. In addition, the control signal /Gini output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 84 in each column.

The source node of the transistor 86 corresponding to the jth column is connected to the power supply line of potential Vorst, and the drain node of the transistor 86 is connected to the data line 14 of the jth column. A control signal /Yr(j) from the decision circuit 510 of the jth column is supplied to the gate node of the transistor 86 in the jth column. The potential Vorst is, for example, the potential Gnd or a low potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED if power is supplied to the anode of the OLED.

A capacitance component parasitic on each data line 14 in each column. In the figure, the capacitance component is represented as a parasitic capacitance 72. That is, the parasitic capacitance 72 is represented electrically as a capacitance element having one end connected to the data line 14 and the other end connected to a power supply line having a constant potential.
In addition, in the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are represented as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is represented as Vd(j).

Figure 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to each other. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the i row and j column as a representative.

As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor.
In addition to the scanning signal /Gwr(i), control signals /Gel(i) and /Gcmp(i) are supplied to the pixel circuits 110 in the i-th row from the scanning line driving circuit 120.

Control signal /Gel(i) is a generalized notation of the control signals /Gel(1), /Gel(2), ..., /Gel(m-1), /Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, control signal /Gcmp(i) is a generalized notation of the control signals /Gcmp(1), /Gcmp(2), ..., /Gcmp(m-1), /Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is light-transmitting.
In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby generating white light.

When a color display is desired, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), or B (blue). A color filter corresponding to the color is provided on the light emission side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter in order, and is then visible to the observer. Note that the optical resonator is not shown. Furthermore, when the electro-optical device 10 simply displays a monochromatic image of light and dark, the color filter is omitted.

In the transistor 121 of the pixel circuit 110 in the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 to which the potential Vel is supplied, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and source node s of the transistor 121.
The other end of the capacitance element 140 may be connected to a power supply line of a potential other than the power supply line of the potential Vel, as long as the potential is kept substantially constant.

In this embodiment, the capacitance element 140 is, for example, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of the transistor. Note that the capacitance element 140 may be a parasitic capacitance of the gate node g of the transistor 121, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate.

In the transistor 122 of the pixel circuit 110 in the i-th row and j-th column, a gate node is connected to the i-th row scanning line 12, and a source node is connected to the j-th column data line 14. In the transistor 123 of the pixel circuit 110 in the i-th row and j-th column, a control signal /Gcmp(i) is supplied to a gate node, and a drain node is connected to the j-th column data line 14. In the transistor 124 of the pixel circuit 110 in the i-th row and j-th column, a control signal /Gel(i) is supplied to a gate node, and a drain node is connected to the pixel electrode 131 which is the anode of the OLED 130.
A potential Vct is supplied to the common electrode 133 which functions as the cathode of the OLED 130. Note that the potential Vct is, for example, the potential Gnd or a low potential close to the potential Gnd.

In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes, even if the elements are not directly connected to each other.

The control circuit 30 also controls the driving of the pixel circuits 110 via the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120. For this reason, the control circuit 30, the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120 are sometimes referred to as a control circuit in a broad sense.

Next, the operation of the electro-optical device 10 will be described.

4 is a timing chart for explaining the operation of the electro-optical device 10. In the electro-optical device 10, m scanning lines 12 are horizontally scanned one by one during a frame (V) period in the order of 1st, 2nd, 3rd, . . . , mth rows.
In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by the video data Vid. If the length of the period of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, the period is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Also, the period required for horizontal scanning of one row is the horizontal scanning period (H).

The operation of the pixel circuits 110 in each row during the horizontal scanning period (H) is common to all the pixel circuits 110. Furthermore, the operation of the pixel circuits 110 in columns 1 to n of a row scanned during a horizontal scanning period (H) is also almost common. Therefore, the following description focuses on the pixel circuit 110 in row i and column j.

In the electro-optical device 10, the horizontal scanning period (H) is divided, in chronological order, into an initialization period (A), a compensation period (B), and a writing period (C). Of these, the initialization period (A) is further divided into three initialization periods (A1), (A2), and (A3). In addition to the initialization period (A), compensation period (B), and writing period (C), the operation of the pixel circuit 110 further includes a light emission period (D).

The initialization period (A1) is a period for setting the transistor 121 to an off state. The initialization period (A2) is a period for resetting the anode potential of the OLEDs 130 other than the specific OLED 130. The specific OLED 130 refers to an OLED that emits light with a luminance equivalent to the highest white level in the gradation level. The initialization period (A3) is a period for supplying a potential Vini for turning the transistor 121 to an on state to the gate node g.
The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a potential corresponding to the threshold voltage of the transistor 121 .
The write period (C) is a period in which a potential corresponding to the gradation level is held (written) at the gate node g of the transistor 121, and more specifically, is a period in which the gate node g of the transistor 121 is changed from a potential corresponding to the threshold voltage by an amount corresponding to a voltage corresponding to the current flowing through the OLED 130.
The light emitting period (D) is a period for causing a current corresponding to the potential of the gate node g held in the writing period (C) to flow through the OLED 130 to emit light.

In the initialization period (A1) of each horizontal scanning period (H), the control signal /Drst is at L level, the control signal /Gini is at H level, and the control signal /Gref is at L level. Therefore, the transistors 82 in each column are turned on, the transistors 84 in each column are turned off, and the transistors 62 in each column are turned on.
In the initialization period (A1), the control signal Yr(j) is at H level. In FIG. 4, the control signal Yr(j) for the jth column is shown, and in the initialization period (A1), the control signals Yr(1) to Yr(j) are at H level regardless of the grayscale level. As a result, the transistors 86 in each column are turned off.

In addition, during the initialization period (A1) of the horizontal scanning period (H) in the i-th row, the scanning signal /Gwr(i) is at the L level, the control signal /Gcmp(i) is at the H level, and the control signal /Gel(i) is at the H level. Therefore, during the initialization period (A1), in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state.

Therefore, in the initialization period (A1), as shown in FIG. 5, in the pixel circuit 110 in the i-th row and j-th column, the potential Vel is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 82, the j-th column data line 14, and the transistor 122 in that order. When the gate node g reaches the potential Vel, the voltage between the gate node g and the source node s becomes zero, and the transistor 121 is forced to be in the off state.

In addition, during the initialization period (A1), the data signal output line 14c in the jth column is set to the potential Vref because the transistor 62 is in the on state.
In addition, since the data line 14 in the jth column is at the potential Vel, the voltage across the capacitive element 70 is |Vel-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vel. Since the potential Vel is the higher level of the power supply voltage, the capacitive element 70 and the parasitic capacitance 72 in the jth column are charged.

In the initialization period (A2) of each horizontal scanning period (H), the control signal /Drst changes to H level, the control signal /Gini maintains H level, and the control signal /Gref maintains L level. As a result, the transistors 82 in each column change to the OFF state, the transistors 84 in each column maintain the OFF state, and the transistors 62 in each column maintain the ON state.
In the initialization period (A2), the level of the control signal Yr(j) changes depending on the judgment result of the j-th column judgment circuit 510. In detail, in the initialization period (A2) of the i-th row, if the gradation level of the i-th row and j-th column is other than the white level, the j-th column judgment circuit 510 sets the control signal /Yr(j) to the L level as shown by (Nw) in Fig. 4, and if the gradation level is the white level, sets the control signal /Yr(j) to the H level as shown by (W) in Fig. 4.

In addition, during the initialization period (A2) of the horizontal scanning period (H) in the i-th row, the scanning signal /Gwr(i) changes to the H level, the control signal /Gcmp(i) changes to the L level, and the control signal /Gel(i) changes to the L level. As a result, in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 changes to the ON state.

If the control signal /Yr(j) is at the L level during the initialization period (A2), the transistor 86 changes to the ON state, and the jth column data line 14 becomes the potential Vorst. Therefore, if the gradation level of the ith row and jth column is other than the white level, as shown in FIG. 6, the anode of the OLED 130 in the ith row and jth column pixel circuit 110 is reset to the first potential, Vorst, via the transistors 124, 123, the jth column data line 14, and the transistor 86 in that order, i.e., a reset operation is performed.

In addition, during the initialization period (A2), the jth column data signal output line 14c continues to be at the potential Vref from the initialization period (A1) because the transistor 62 is maintained in the on state.
In addition, since the j-th data line 14 is at the potential Vorst, the voltage across the capacitive element 70 is |Vorst-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vorst. The potentials Vel and Vorst are expressed as follows:
Vel>Vorst
Since this relationship holds, the capacitive element 70 and the parasitic capacitance 72 in the jth column are discharged.

On the other hand, if the control signal /Yr(j) is at H level during the initialization period (A2), the transistor 86 remains in the off state. During the immediately preceding initialization period (A1), the data line 14 is at potential Vel, and this potential Vel is held at the other end of the capacitance element 70 and one end of the parasitic capacitance 72. For this reason, if the gradation level of row i, column j is the white level, as shown in FIG. 7, in the OLED 130 in the pixel circuit 110 of row i, column j, charge flows out of the capacitance element 70 and parasitic capacitance 72, and a non-reset operation is performed toward the OLED 130 via the data line 14, transistors 123, 124 in that order.

When the parasitic capacitance of the OLED 130 becomes fully charged due to the charge flowing out from the capacitive element 70 and the parasitic capacitance 72, the charge overflows and flows into the OLED 130 (the light-emitting functional layer 132), which may cause the OLED 130 to emit light. However, since the gradation level of row i and column j is set to the highest gradation, white level, the effect of light emission outside the expected period, i.e., during the initialization period (A2) other than the light-emitting period (D), can be ignored.

Since the charge outflow causes the capacitive element 70 and the parasitic capacitance 72 in the jth column to discharge, the data line 14 drops from the potential Vel. This discharge is only a small amount, and is only sufficient to distribute the charge to the parasitic capacitance of the OLED 130 via the jth data line 14.
For this reason, during the horizontal scanning period of the i-th row, if the gradation level of the i-th row and j-th column is the white level in the initialization period (A2), the j-th data line 14 and the anode in the i-th row and j-th column will be at a potential between the potential Vorst and the potential Vel, i.e., the second potential, but it is safe to say that they are approximately at the potential Vel.
That is, in the non-reset operation performed when the gradation level is the white level, the influence of the discharge of the capacitive element 70 and the parasitic capacitance 72 in the jth column can be ignored compared to the reset operation when the gradation level is a level other than the white level. In this embodiment, the transistor 121 is set to the off state in the initialization period (A1), but this is not limited, and the initialization period (A1) may not be necessary. That is, the anode potential in the OLED 130 may be reset in the initialization period (A2) without setting the transistor 121 to the off state in the initialization period (A1). In this case, the anode potential in the OLED 130 may be reset by turning off the transistor 122.

In the initialization period (A3) of each horizontal scanning period (H), the control signal /Drst maintains the H level, the control signal /Gini changes to the L level, and the control signal /Gref maintains the L level. As a result, the transistors 82 in each column maintain the OFF state, the transistors 84 in each column change to the ON state, and the transistors 62 in each column maintain the ON state.
In the initialization period (A3), the control signal Yr(j) is at H level. Note that, although the control signal Yr(j) for the jth column is described here, after the initialization period (A3), the control signals Yr(1) to Yr(j) are at H level regardless of the gradation level. As a result, the transistors 86 in each column are turned off.

In addition, during the initialization period (A3) of the horizontal scanning period (H) in the i-th row, the scanning signal /Gwr(i) changes to the L level, the control signal /Gcmp(i) changes to the H level, and the control signal /Gel(i) changes to the H level. As a result, in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 changes to the ON state, the transistor 123 changes to the OFF state, and the transistor 124 changes to the OFF state.

Therefore, in the initialization period (A3), as shown in FIG. 8, in the pixel circuit 110 in the i-th row and j-th column, the potential Vini is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 84, the j-th column data line 14, and the transistor 122 in that order.

In addition, during the initialization period (A3), the data signal output line 14c in the jth column continues to be at the potential Vref from the initialization period (A1) because the transistor 62 is maintained in the on state.
In addition, since the j-th data line 14 is at the potential Vini, the voltage across the capacitive element 70 is |Vini-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vini. The potentials Vini and Vorst are expressed as follows:
(Vel＞)Vini＞Vorst
This is the relationship.
Therefore, if the data line 14 is at the potential Vorst during the initialization period (A2), the capacitive element 70 and the parasitic capacitance 72 are charged, and if the data line 14 has hardly changed from the potential Vel during the initialization period (A2), the capacitive element 70 and the parasitic capacitance 72 are discharged.
FIG. 8 shows a case where the capacitive element 70 and the parasitic capacitance 72 are charged.

When the initialization period (A3) ends, the compensation period (B) begins. In the compensation period (B) of each horizontal scanning period (H), the control signal /Drst maintains the H level, the control signal /Gini changes to the H level, and the control signal /Gref maintains the L level. Therefore, the transistors 82 in each column maintain the OFF state, the transistors 84 in each column change to the OFF state, and the transistors 62 in each column maintain the ON state.
4, only the control signal /Yr(j) is shown, but as described above, during the compensation period (B), the control signals /Yr(1) to /Yr(j) are at H level, so that the transistors 86 in each column are maintained in the off state.

In addition, during the compensation period (B) of the horizontal scanning period (H) of the i-th row, the scanning signal /Gwr(i) maintains the L level, the control signal /Gcmp(i) changes to the L level, and the control signal /Gel(i) maintains the H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

At the start of the compensation period (B), in the pixel circuit 110 in the i-th row, the gate node g of the transistor 121 is held at the potential Vini by the capacitance element 140. When the gate node g is at the potential Vini and the transistor 123 is turned on, the transistor 121 becomes diode-connected.

Therefore, in the compensation period (B), as shown in FIG. 9, the voltage between the gate node g and the source node s of the transistor 121 converges to (a voltage close to) the threshold voltage Vth of the transistor 121. In other words, the potentials of the gate node g of the transistor 121 and the data line 14 converge to a potential equivalent to the threshold (Vel-Vth).

During the compensation period (B) of the i-th row, the transistor 62 of each column maintains the on state, so that the data signal output line 14c of each column is maintained at the potential Vref.
Furthermore, since the data line 14 converges to the potential equivalent to the threshold voltage (Vel-Vth), the voltage across the capacitive element 70 becomes |Vel-Vth-Vref|, and one end of the parasitic capacitance 72 is held at the potential equivalent to the threshold voltage (Vel-Vth).

When the compensation period (B) ends, the writing period (C) begins. In the writing period (C) of each horizontal scanning period (H), the control signal /Drst maintains the H level, the control signal /Gini maintains the H level, and the control signal /Gref changes to the H level. Therefore, the transistors 82 in each column maintain the off state, the transistors 84 in each column maintain the off state, and the transistors 62 in each column change to the off state.
4, the control signal /Yr(j) is shown, but as described above, in the writing period (C), the control signals /Yr(1) to /Yr(j) are at H level, so that the transistors 86 in each column are turned off.

In addition, during the writing period (C) of the horizontal scanning period (H) of the i-th row, the scanning signal /Gwr(i) maintains the L level, the control signal /Gcmp(i) changes to the H level, and the control signal /Gel(i) maintains the H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

During the write period (C), the transistors 62 in each column are turned off. In addition, the DA conversion circuit 500 in each column is supplied with 10-bit video data Vdata corresponding to the i-th row and column. Therefore, the DA conversion circuit 500 in the j-th column outputs a data signal with a potential corresponding to the gradation level of the i-th row and j-th column to the data signal output line 14c.

Therefore, during the write period (C), as shown in FIG. 10, one end of the capacitive element 70 in the jth column rises from potential Vref to a potential of the gradation level corresponding to row i and column j. This potential rise reaches the gate node g of transistor 121 via the capacitive element 70, data line 14, and transistor 122 in that order.

The change in potential of the gate node g during the write period (C) is the increase in potential at one end of the capacitance element 70 multiplied by the ratio of the capacitance value of the capacitance element 70 to the "composite capacitance value." The "composite capacitance value" here refers to the capacitance value of the composite capacitance of the capacitance element 70, the parasitic capacitance 72, and the capacitance element 140. Note that the capacitance value of the capacitance element 140 can be ignored if it is sufficiently small compared to the other capacitance values.

When the scanning signal /Gwr(i) changes to the H level, the writing period (D) of the i-th row ends. When the scanning signal /Gwr(i) becomes the H level, the transistor 122 in the pixel circuit 110 in the i-th row and j-th column is turned off, but the voltage difference between the potential of the gate node g and the potential Vel is held in the capacitance element 140.

After the writing period (C) ends, a light emitting period (D) begins.
When the light emission period (E) of the i-th row is reached, the control signal /Gel(i) is inverted to the L level, so that the transistor 124 is turned on.
11 , in the light emission period (D), a current Iel according to the potential of the gate node g held by the capacitance element 140 flows through the OLED 130 by the transistor 121. Therefore, the OLED 130 emits light with a luminance according to the current Iel.

Note that, although FIG. 4 shows an example in which the light emission period (D) of the i-th row starts immediately after the end of the writing period (C) of the i-th row, the light emission period (D) of the i-th row may start, for example, one horizontal scanning period (H) after the end of the writing period (C) of the i-th row.
4 shows an example in which the light emission period (D) is continuous, the period in which the control signal /Gel(i) is at the L level may be intermittent, may be changed in response to the adjustment of the luminance, or may be adjusted in response to the luminance of the ambient light. Also, the level of the control signal /Gel(i) in the light emission period (D) may be an intermediate level between the H level and the L level.

In the horizontal scanning period (H) of the i-th row, a similar operation is performed for the pixel circuits 110 in columns 1 to n. Also, in FIG. 4, attention is focused on the horizontal scanning period (H) of the i-th row, and the operation of that horizontal scanning period (H) is explained, but a similar operation is sequentially performed for the horizontal scanning periods (H) of the 1st, 2nd, 3rd, ..., mth rows.

The potential of the gate node g in the pixel circuit 110 in the i row and j column is a potential that has been changed from the threshold equivalent potential in the compensation period (B) according to the gradation level of the i row and j column. Similar operations are performed in the other pixel circuits 110, so in this embodiment, a current according to the gradation level flows through the OLED 130 with the thresholds of the transistors 121 compensated across all pixel circuits 110 in the m rows and n columns. Therefore, in this embodiment, the variation in luminance is reduced, enabling a high-quality display.

The main reason why a reset operation that discharges the anode of the OLED 130 is performed is as follows. In the OLED 130, the light-emitting functional layer 132 is sandwiched between the pixel electrode 131, which is the anode, and the common electrode 133, which is the cathode, so that the OLED 130 has a parasitic capacitance. As described above, in the compensation period (B), the gate node g and drain node d (the source node of the transistor 124) of the transistor 121 are at a potential equivalent to the threshold value. Next, in the writing period (C), a potential corresponding to the gradation level is supplied to the gate node g of the transistor 121.

If the lowest gradation black level (darkest level) is supplied to the gate node g, the gate node g should ideally be at potential Vel, but in reality, it is at a potential lower than potential Vel. For this reason, when the transistor 124 is turned on during the light emission period (D), a leakage current flows from the source node s to the drain node d in the transistor 121. If the charge stored in the parasitic capacitance of the OLED 130 is not reset in advance, the leakage current will eventually fully charge the parasitic capacitance, causing current to start flowing through the OLED 130 and emitting light. This phenomenon is called black floating, because even though the black level, i.e., a luminance that does not emit light, is specified, a slight amount of light is emitted, and it is perceived as if the black is floating.

Therefore, in the initialization period (A2) prior to the light emission period (D), the anode of OLED 130 is set to potential Vorst, the anode is discharged in advance, and the charge accumulated in the parasitic capacitance of the OLED 130 is reset. As a result, even if a leakage current flows through the transistor 121 during the light emission period (D), the leakage current does not fully charge the parasitic capacitance of the OLED 130, and light is not emitted, thereby suppressing the so-called black floating.

However, a configuration in which a reset operation is performed can be a factor that hinders low power consumption. To explain this, a comparative example will be described. In terms of configuration, the comparative example is a configuration in which the determination circuit 510 for each column is not included in the embodiment, and the anode of the OLED 130 is reset to the potential Vorst and the reset operation is performed regardless of the grayscale level in the initialization period (A2).
In this configuration, the other end of the capacitive element 70 and one end of the parasitic capacitance 72 in all columns are at the potential Vel in the initialization period (A1), at the potential Vorst in the initialization period (A2), and at the potential Vini in the initialization period (A3).

As described above, the potentials Vel, Vorst, and Vini are expressed as follows:
Vel>Vini>Vorst (≒Vct)
This is the relationship.
Of these, the potential Vel is a high level of the power supply voltage, and the potential Vorst is a low level of the power supply voltage Gnd or a potential close to the potential Gnd. Therefore, in the above comparative example, the capacitive element 70 and the parasitic capacitance 72 are charged in the initialization period (A1), discharged in the initialization period (A2), and charged in the initialization period (A3). In the comparative example, such a charge-discharge-charge cycle of the capacitive element 70 and the parasitic capacitance 72 is performed for each column every horizontal scanning period (H), so that the power consumed is large.

This embodiment is the same as the comparative example in that the other end of the capacitance element 70 and one end of the parasitic capacitance 72 are charged to the potential Vel in the initialization period (A1). However, in this embodiment, in a column whose gradation level is the white level, a non-reset operation that distributes charge is performed in the initialization period (A2) instead of a reset operation, so that the discharge of the capacitance element 70 and the parasitic capacitance 72 in that column can be ignored compared to when the gradation level is other than the white level. Furthermore, in this embodiment, in the initialization period (A3), the other end of the capacitance element 70 and one end of the parasitic capacitance 72 become the potential Vini, but in a column whose gradation level is the white level, they are discharged from the potential Vel.

In other words, in the comparative example, the capacitive element 70 and the parasitic capacitance 72 go from charge to discharge to charge in all columns during the initialization period (A1) → (A2) → (A3), whereas in this embodiment, in columns with gradation levels other than the white level, they are the same as in the comparative example, but in columns with a gradation level of the white level, they go from charge to almost no change to discharge.

Therefore, in the first embodiment, if there is a column whose gradation level is the white level, the power consumed by charging and discharging the capacitive element 70 and the parasitic capacitance 72 can be reduced compared to the comparative example.

A case where there is a row in which the gradation level is the highest gradation level, that is, white level, is specifically a case where a screen such as that shown in FIG. 12 is displayed.
In this case, since the data line 14Nw is a column whose gradation level is other than the white level, the capacitive element 70 and the parasitic capacitance 72 are charged by the potential Vel in the initialization period (A1), discharged by the potential Vorst in the initialization period (A2), and recharged by the potential Vini in the initialization period (A3).
On the other hand, since data line 14W is a column whose gradation level is the white level, capacitive element 70 and parasitic capacitance 72 are charged by potential Vel during the initialization period (A1), are hardly discharged during the initialization period (A2), and are discharged by potential Vini during the initialization period (A3).

In the first embodiment, the transistors 86 in the columns whose gradation level is the white level during the initialization period (A2) are turned off to perform a non-reset operation instead of a reset operation, but other configurations are also possible. Therefore, a second embodiment will be described in which the non-reset operation of the columns whose gradation level is the white level is performed by an operation different from that of the first embodiment.

Figure 13 is a block diagram showing the electrical configuration of the electro-optical device 10 according to the second embodiment, and Figure 14 is a timing chart showing the operation of the electro-optical device 10.

The second embodiment shown in FIG. 13 differs from the first embodiment shown in FIG. 2 in that the determination circuit 510 outputs control signals /Yini(1) to /Yini(n) corresponding to columns 1 to n in sequence in addition to control signals /Yr(1) to /Yr(n), and that the control signals /Yini(1) to /Yini(n) are supplied to the gate nodes of the transistors 84 in columns 1 to n in sequence. Note that, due to space limitations, only the control signals /Yini(3) and /Yini(n) are shown in FIG. 13.

In the second embodiment, during the initialization period (A2), the level of the control signal Yini(j) changes depending on the judgment result of the jth column judgment circuit 510. In detail, during the initialization period (A2) of the ith row, if the gradation level of the ith row and jth column is not the highest white level, the jth column judgment circuit 510 sets the control signal /Yini(j) to the H level as shown by (Nw) in FIG. 14, and if the gradation level is the white level, sets the control signal /Yini(j) to the L level as shown by (W).

Furthermore, the decision circuit 510 in the jth column sets the control signal /Yini(j) to the L level during the initialization period (A3) of the i-th row, regardless of the grayscale level of the i-th row and j-th column.
In addition, the jth column decision circuit 510 sets the control signal /Yini(j) to the H level in periods other than the initialization periods (A2) and (A3). In addition, the jth column decision circuit 510 outputs the same control signal /Yr(j) as in the first embodiment.

The electro-optical device 10 according to the second embodiment differs from the first embodiment only in the operation when the gradation level of the i-th row and j-th column is the white level in the initialization period (A2) during the horizontal scanning period (H) of the i-th row.
In other words, in the electro-optical device 10 according to the second embodiment, the initialization period (A1), the initialization period (A2) when the gradation level of the i-th row and j-th column is not the white level, the initialization period (A3), the compensation period (B), and the writing period (C) during the horizontal scanning period (H) of the i-th row are common to the first embodiment. Also, in the electro-optical device 10 according to the second embodiment, the operation of the light emission period (D) during periods other than the i-th row horizontal scanning period (H) is also common to the first embodiment.

FIG. 15 is a diagram showing an operation when the grayscale level of the i-th row and j-th column is the white level in the initialization period (A2) of the horizontal scanning period (H) of the i-th row.
In the initialization period (A2) of each horizontal scanning period (H), the control signal /Drst changes to H level, and the control signal /Gref maintains L level. As a result, the transistors 82 in each column change to the OFF state, and the transistors 62 in each column maintain the ON state.
Furthermore, in the initialization period (A2) of the horizontal scanning period (H) in the i-th row, the scanning signal /Gwr(i) changes to H level, the control signal /Gcmp(i) changes to L level, and the control signal /Gel(i) changes to L level. As a result, in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 changes to the ON state.

In the initialization period (A2) in the horizontal scanning period (H) of the i-th row, if the gradation level of the i-th row and j-th column is the white level, the control signal /Yini(j) becomes the L level and the control signal /Yr(j) becomes the H level. As a result, the transistor 84 of the j-th column changes to the ON state and the transistor 86 of the j-th column maintains the ON state, so that a non-reset operation is performed to set the data line 14 of the j-th column to the potential Vini.
Therefore, as shown in FIG. 15, a current flows to the OLED 130 via the data line 14 in the jth column, the transistors 123 and 124 in this order, so that the OLED 130 emits light in the initialization period (A2).
However, the potentials Vel and Vini are
Vel>Vini
Because of this relationship, the luminance of light emitted by the OLED 130 is lower than that in the first embodiment.

In the second embodiment, during the initialization period (A3) of the horizontal scanning period (H) of the i-th row, if the gradation level of the i-th row and j-th column is the white level, the transistor 82 maintains the off state, the transistor 84 is on, the transistor 86 maintains the off state, and the transistor 62 maintains the on state. In the pixel circuit 110, the transistor 122 is turned on, the transistor 123 changes to the off state, and the transistor 124 changes to the off state. Therefore, the other end of the capacitance element 140 and the gate node g of the transistor 121 are supplied with the potential Vini via the j-th column data line 14 and the transistor 122 in that order, as in the first embodiment.

However, if the gradation level of the jth column is the white level, the data line 14 of the jth column does not change from the potential Vini in the initialization period (A2). Therefore, in the second embodiment, the capacitive element 70 and the parasitic capacitance 72 are charged, discharged, and remain unchanged in the columns whose gradation level is the white level during the initialization period (A1) → (A2) → (A3).

Therefore, in the second embodiment, if there is a column whose gradation level is the white level, the power consumed by the charging and discharging of the capacitive element 70 and the parasitic capacitance 72 can be reduced in the same manner as in the first embodiment, compared to the comparative example described above.
In addition, in the second embodiment, when the gradation level is the white level, the data line 14 in the initialization period (A2) is at a potential Vini lower than the potential Vel, so that it is expected that the luminance emitted outside the expected period can be kept low.

The above-described first and second embodiments (hereinafter referred to as "embodiments") can be modified or applied in various ways as follows.

In the embodiment and the like, in the initialization period (A2), if the gradation level is other than the white level, the reset operation is performed, and if the gradation level is the white level, the non-reset operation is performed.
As described above, the reason why the charge accumulated in the OLED 130 is reset by the reset operation is to suppress the occurrence of so-called black floating. Black floating occurs not only when the gradation level is the lowest black level, but also when it is near the black level, that is, when the gradation level is below a threshold value.
Therefore, if the gradation level is less than a threshold value, a reset operation is performed in which the anode of OLED 130 is discharged in the initialization period (A2) as shown in FIG. 6, and if the gradation level is equal to or greater than the threshold value, a non-reset operation is performed in which the anode is not discharged in the initialization period (A2) as shown in FIG. 7 or FIG. 15.
In the embodiment, the determination circuit 510 determines the gradation level based on the 10-bit video data Vdata. That is, whether the gradation level is less than the threshold value or equal to or greater than the threshold value is determined based on the video data Vdata after converting the 8-bit video data Vid to 10-bit.

In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14.
In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500, but the present invention is not limited to this.

The channel types of transistors 64, 82, 84, 86, 121 to 124, etc. are not limited to those in the embodiments. In addition, these transistors, etc. may be replaced with transmission gates as appropriate.

Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be used as an example of an electronic device.

FIG. 16 is a diagram showing the appearance of a head mounted display, and FIG. 17 is a diagram showing its optical configuration.
First, as shown in Fig. 16, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. In addition, as shown in Fig. 17, the head mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure).
The image display surface of the electro-optical device 10L is disposed to the left in FIG. 17. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world.
Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

In addition to the head-mounted display 300, electronic devices including the electro-optical device 10 can also be used in electronic viewfinders in video cameras and interchangeable lens digital cameras, portable information terminals, display units in wristwatches, and light bulbs in projection projectors.

From the above examples, the following aspects can be understood:

An electro-optical device according to one embodiment (embodiment 1) includes a pixel circuit provided in correspondence with a data line and a scanning line, and a control circuit for controlling the pixel circuit, the pixel circuit including a light-emitting element having two electrodes and emitting light with a luminance corresponding to a current flowing between the two electrodes, and a drive transistor for causing a current corresponding to a voltage between a gate node potential and a source node potential to flow through the light-emitting element, the control circuit supplying a potential corresponding to a gradation level to the gate node via the data line during a write period, and performing a first operation or a second operation according to the gradation level during a first initialization period prior to the write period, the first operation being an operation of supplying a first potential different from the potential corresponding to the gradation level to one of the two electrodes via the data line, and the second operation being an operation of causing the potential of the data line and the potential of the one electrode to become a second potential between the first potential and an off potential that turns the drive transistor into an off state.

According to the first aspect, in the first initialization period, the first operation or the second operation is executed according to the grayscale level. In the first operation, the data line goes from the immediately preceding potential to the first potential, so that the amount of discharge is large, whereas in the second operation, the data line goes from the immediately preceding potential to the off potential to the second potential between the first potential and the off potential, so that the amount of discharge in the parasitic capacitance of the data line is suppressed compared to the first operation.
The LED 130 is an example of a light-emitting element, the pixel electrode 131 is an example of one of the two electrodes, the transistor 121 is an example of a drive transistor, the potential Vel is an example of an off potential, and the potential Vorst is an example of a first potential. A potential slightly lower than the potential Vel is an example of a second potential. Specifically, the potential after the charge accumulated in the parasitic capacitance of the data line held at the off potential is distributed to one electrode in the light-emitting element is also an example of the second potential. The initialization period (A2) is an example of a first initialization period.

An electro-optical device according to a specific aspect 2 of aspect 1 has a first switching element having one end and the other end, the one end being electrically connected to the data line and the other end being electrically connected to the power supply line of the first potential, and the control circuit controls the first switching element to an on or off state depending on the gradation level during the first initialization period.
According to the second aspect, in the first operation of the first initialization period, the first switching element is turned on, so that the data line has the first potential. The transistor 86 is an example of the first switching element.

In the electro-optical device according to a third specific example of the second example, the control circuit controls the first switching element to an off state during the first initialization period if the grayscale level is equal to or higher than a threshold value.
According to the third aspect, if the grayscale level is equal to or higher than the threshold value, the first switching element is controlled to the off state in the first initialization period, and the second operation is executed.

An electro-optical device relating to a specific aspect 4 of aspect 2 has a second switching element having one end and the other end, one end electrically connected to the data line and the other end electrically connected to a power supply line that supplies the second potential, and when the control circuit controls the first switching element to an off state during the first initialization period, it controls the second switching element to an on state.
According to the fourth aspect, in the second operation of the first initialization period, the first switching element is turned off and the second switching element is turned on, so that the potential of the data line and the potential of the one electrode become the second potential.
The transistor 84 is an example of a second switching element, and the potential Vini is an example of a second potential.

In the electro-optical device according to a fifth specific aspect of the fourth aspect, the second potential is an on potential that turns on the driving transistor when supplied to the gate node.
According to aspect 5, the on-potential that turns the driving transistor on can be used as the second potential. In addition, in the configuration in which the on-potential is used as the second potential, the luminance of the light-emitting element can be kept low, compared to a configuration in which the electric charge accumulated in the parasitic capacitance of the data line held at the off-potential in the second initialization period is distributed to one electrode of the light-emitting element and the second potential is used.

In an electro-optical device relating to a specific aspect 6 of aspect 5, the control circuit supplies the second potential to the gate node via the data line in a second initialization period after the first initialization period and before the writing period, and converges the gate node to a potential corresponding to the threshold value of the driving transistor in a compensation period after the second initialization period and before the writing period.
In order to make the gate node converge to a potential corresponding to the threshold voltage of the driving transistor during the compensation period, it is necessary to turn the driving transistor on before the compensation period. According to aspect 6, the on potential for turning on the driving transistor is used as the second potential, so that the complexity of the configuration can be suppressed.
The initialization period (A2) is an example of a first initialization period.

In a seventh specific aspect of the first aspect, the control circuit supplies a potential according to a grayscale level to the gate node via a coupling capacitance and the data line during the writing period.
According to the seventh aspect, it is possible to suppress not only the parasitic capacitance of the data line but also the discharge amount of the coupling capacitance. Note that the capacitive element 70 is an example of a coupling capacitance.
In another specific aspect 8 of aspect 1, in a third initialization period before the first initialization period, an off potential for turning off the driving transistor is supplied to the gate node via the data line. Note that the initialization period (A1) is an example of the third initialization period.

The electronic device according to aspect 9 includes an electro-optical device according to any one of aspects 1 to 8.

10... electro-optical device, 12... scanning line, 14... data line, 14c... data signal output line, 30... control circuit, 50... data signal output circuit, 60... auxiliary circuit, 62... transistor, 70... capacitance element, 72... parasitic capacitance, 80... initialization circuit, 82, 84, 86... transistor, 110... pixel circuit, 120... scanning line drive circuit, 121 to 124... transistor, 130... OLED.

Claims (9)

a pixel circuit provided corresponding to the data line and the scanning line;
A control circuit for controlling the pixel circuit;
Including,
The pixel circuit includes:
A light-emitting element having two electrodes and emitting light with a luminance corresponding to a current flowing between the two electrodes;
a drive transistor that causes a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow through the light emitting element;
Including,
The control circuit includes:
During the writing period,
supplying a potential corresponding to a gray level to the gate node via the data line;
In a first initialization period before the writing period,
performing a first operation or a second operation in response to the gray level;
The first operation includes:
an operation of supplying a first potential different from a potential corresponding to the gradation level to one of the two electrodes via the data line;
The second operation includes:
an operation of setting the potential of the data line and the potential of the one electrode to a second potential between the first potential and an off potential that turns off the driving transistor, the electro-optical device comprising:
a first switching element having one end and the other end, the one end being electrically connected to the data line and the other end being electrically connected to the power supply line of the first potential;
The control circuit includes:
In the first initialization period,
The electro-optical device according to claim 1 , wherein the first switching element is controlled to be in an on state or an off state in accordance with the grayscale level.
The control circuit includes:
The electro-optical device according to claim 2 , wherein, in the first initialization period, if the grayscale level is equal to or higher than a threshold value, the first switching element is controlled to an off state.
a second switching element having one end and the other end, the one end being electrically connected to the data line and the other end being electrically connected to a power supply line that supplies the second potential;
The control circuit includes:
In the first initialization period,
The electro-optical device according to claim 2 , wherein when the first switching element is controlled to be in an off state, the second switching element is controlled to be in an on state.
The second potential is
The electro-optical device according to claim 4 , wherein the potential is an on potential that turns on the driving transistor when supplied to the gate node.
The control circuit includes:
In a second initialization period after the first initialization period and before the writing period,
supplying the second potential to the gate node via the data line;
In a compensation period after the second initialization period and before the writing period,
The electro-optical device according to claim 5 , wherein the gate node is converged to a potential corresponding to a threshold value of the driving transistor.
The control circuit includes:
During the writing period,
The electro-optical device according to claim 1 , wherein a potential according to a grayscale level is supplied to the gate node via a coupling capacitance and the data line.
In a third initialization period prior to the first initialization period,
supplying an off potential to the gate node via the data line to turn off the driving transistor;
2. The electro-optical device according to claim 1.
An electronic device having an electro-optical device according to any one of claims 1 to 8.

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