JP7540362B2 - Electro-optical device and electronic device - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device.

Patent document 1 discloses a liquid crystal device as an electro-optical device that includes transistors for supplying image signals to pixel electrodes and storage capacitors for storing the image signals for a certain period of time. For example, the transistors and storage capacitors are formed from part of the same semiconductor layer. In addition, the transistors are arranged along the scanning lines to ensure storage capacitance and improve the aperture ratio.

JP 2001-66633 A

However, transistors arranged along the scan lines have the problem that light passing through the pixels is easily incident on the transistors, which can affect display quality. In other words, in addition to a high aperture ratio, there is a demand for ensuring light blocking properties and storage capacitance.

The electro-optical device comprises a substrate having a recess , a scanning line extending along a first direction, a data line extending along a second direction intersecting the first direction, a transistor having a semiconductor layer in which one source/drain region, one LDD region, a channel region, the other LDD region, and a first portion of the other source/drain region extend along the first direction at a position overlapping the scanning line, and a second portion of the other source/drain region extends along the second direction at a position overlapping the data line, and a light-shielding wall arranged along the one LDD region or the other LDD region , with a portion of the light-shielding wall arranged within the recess of the substrate .

The electronic device includes the electro-optical device described above.

FIG. 1 is a schematic plan view showing a configuration of a liquid crystal device as an electro-optical device. 2 is a cross-sectional view of the liquid crystal device shown in FIG. 1 taken along line H-H'. FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device. FIG. 2 is a schematic plan view showing an arrangement of pixels. FIG. 2 is a schematic cross-sectional view showing the structure of an element substrate. 5 is a process flow diagram showing a method for manufacturing an element substrate, which is one example of a method for manufacturing a liquid crystal device. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. 5A to 5C are schematic cross-sectional views showing a method for manufacturing an element substrate. 5A to 5C are schematic plan views showing a method for manufacturing an element substrate. FIG. 1 is a schematic diagram showing a configuration of a projection type display device as an electronic device.

In the following figures, where necessary, XYZ axes are added as mutually orthogonal coordinate axes, the direction in which each arrow points is the + direction, and the direction opposite the + direction is the - direction. Note that the +Z direction is sometimes referred to as upward and the -Z direction as downward, and a view from the +Z direction is referred to as a planar view or planar. Furthermore, in the following explanation, for example, the expression "on the substrate" with respect to a substrate refers to either a case in which the substrate is placed in contact with the substrate, a case in which the substrate is placed on the substrate via another structure, or a case in which a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed on the substrate via another structure.

In this embodiment, an active drive type liquid crystal device having a thin film transistor (Thin Film Transistor) as a transistor for each pixel is exemplified as the electro-optical device. Hereinafter, thin film transistor is abbreviated to TFT. This liquid crystal device can be suitably used as a light modulation device, for example, in a projection display device as an electronic device described later.

First, the configuration of the liquid crystal device 100 will be described with reference to Figures 1 to 3.

As shown in Figures 1 and 2, the liquid crystal device 100 of this embodiment includes an element substrate 10, a counter substrate 20 disposed opposite the element substrate 10, and a liquid crystal layer 50 containing liquid crystal sandwiched between the element substrate 10 and the counter substrate 20.

The substrate 10s of the element substrate 10 is, for example, a glass substrate, a quartz substrate, or the like. The substrate 20s of the opposing substrate 20 is, for example, a transparent substrate such as a glass substrate, a quartz substrate, or the like.

The element substrate 10 is larger than the opposing substrate 20 in plan view. The element substrate 10 and the opposing substrate 20 are joined via a sealant 40 arranged along the outer edge of the opposing substrate 20. A liquid crystal layer 50 is provided by sealing the gap between the element substrate 10 and the opposing substrate 20 with liquid crystal having positive or negative dielectric anisotropy.

Inside the sealing material 40, a display area E including a plurality of pixels P arranged in a matrix is provided. Between the sealing material 40 and the display area E, a partition 24 is provided surrounding the display area E. Around the display area E, a dummy pixel area (not shown) that does not contribute to the display is provided.

The element substrate 10 is provided with a terminal section in which a plurality of external connection terminals 104 are arranged. A data line driving circuit 101 is provided between a first side section along the terminal section and the sealing material 40. In addition, an inspection circuit 103 is provided between the sealing material 40 and the display area E along a second side section opposite the first side section.

A scanning line driving circuit 102 is provided between the seal material 40 and the display area E along the third and fourth sides that are perpendicular to the first side and face each other. In addition, a plurality of wirings 107 that connect the two scanning line driving circuits 102 are provided between the seal material 40 on the second side and the inspection circuit 103.

The wiring connected to the data line driving circuit 101 and the scanning line driving circuit 102 is connected to a plurality of external connection terminals 104 arranged along the first side. Note that the arrangement of the inspection circuit 103 is not limited to the above.

Here, in this specification, the direction along the first side portion is the ±X direction as the first direction. Furthermore, the second direction intersecting the first direction is the ±Y direction, which is perpendicular to the first side portion and parallel to the third and fourth sides that face each other. Furthermore, the ±Z direction is perpendicular to the ±X and ±Y directions and is the normal direction of the element substrate 10 and the opposing substrate 20.

As shown in FIG. 2, the surface of the substrate 10s facing the liquid crystal layer 50 is provided with a light-transmitting pixel electrode 15 provided for each pixel P, a TFT 30 serving as a transistor that is a switching element, signal wiring, and an alignment film 18 that covers these. The TFT 30 and pixel electrode 15 are components of the pixel P. The element substrate 10 includes the substrate 10s, the pixel electrode 15 provided on the substrate 10s, the TFT 30, the signal wiring, and the alignment film 18. The pixel electrode 15 is provided corresponding to the TFT 30.

On the surface of the substrate 20s facing the liquid crystal layer 50, a parting portion 24, an insulating layer 25 formed to cover the parting portion 24, a counter electrode 21 as a common electrode provided to cover the insulating layer 25, and an alignment film 22 covering the counter electrode 21 are provided. The counter substrate 20 in this embodiment includes at least the parting portion 24, the counter electrode 21, and the alignment film 22. Note that, although this embodiment shows an example in which a common electrode is disposed on the counter substrate 20 side as the counter electrode 21, this is not limiting.

As shown in FIG. 1, the parting portion 24 surrounds the display area E and is provided at a position overlapping the scanning line driving circuit 102 and the inspection circuit 103 in plan view. This blocks light entering these circuits from the opposing substrate 20 side, preventing malfunction of the circuits due to the incidence of light. In addition, unnecessary stray light is blocked from entering the display area E, ensuring high contrast in the display of the display area E.

The insulating layer 25 is made of an inorganic material such as silicon oxide that is optically transparent. The insulating layer 25 covers the parting portion 24 and is provided so that the surface on the liquid crystal layer 50 side is flat.

The counter electrode 21 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), covers the insulating layer 25, and is electrically connected to vertical conductive parts 106 provided at the four corners of the counter substrate 20. The vertical conductive parts 106 are electrically connected to wiring on the element substrate 10 side.

The alignment film 18 that covers the pixel electrode 15 and the alignment film 22 that covers the counter electrode 21 are selected based on the optical design of the liquid crystal device 100. Materials for forming the alignment films 18 and 22 include inorganic alignment films such as silicon oxide and organic alignment films such as polyimide.

Such a liquid crystal device 100 is, for example, a transmissive type, and employs an optical design of a normally white mode in which the transmittance of pixel P when no voltage is applied is greater than the transmittance when voltage is applied, or a normally black mode in which the transmittance of pixel P when no voltage is applied is less than the transmittance when voltage is applied. In a liquid crystal panel including an element substrate 10 and an opposing substrate 20, polarizing elements are arranged on the light entrance side and light exit side according to the optical design.

In this embodiment, we will explain an example in which the inorganic alignment film described above is used as the alignment films 18 and 22, and liquid crystal with negative dielectric anisotropy is used, and a normally black mode optical design is applied.

Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG. 3.

As shown in FIG. 3, the liquid crystal device 100 has a plurality of scanning lines 3, data lines 6, and capacitance lines 8 arranged in parallel along the data lines 6, which serve as signal wiring that is insulated from and perpendicular to each other at least in the display region E. The scanning lines 3 extend in the ±X direction as a first direction. The data lines 6 extend in the ±Y direction as a second direction intersecting the first direction. Note that, although the direction in which the capacitance lines 8 extend is the ±Y direction in FIG. 3, this is not limiting.

A pixel electrode 15, a TFT 30, and a capacitance element 16 are provided in an area partitioned by the scanning line 3, the data line 6, the capacitance line 8, and these signal wirings, and these constitute the pixel circuit of the pixel P. The pixel electrode 15, the TFT 30, and the capacitance element 16 are arranged for each pixel P.

The scanning line 3 is electrically connected to the gate of the TFT 30. More specifically, the data line 6 is electrically connected to one of the source drain regions of the TFT 30, which is the data line side source drain region. The scanning line 3 has the function of simultaneously controlling the on/off of the TFTs 30 arranged in the same row. The pixel electrode 15 is electrically connected to the pixel electrode side source drain region, which is the other of the source drain regions of the TFT 30. The semiconductor layer including the source drain region of the TFT 30 will be described later.

The data lines 6 are electrically connected to the data line driving circuit 101 described above, and supply image signals D1, D2, ..., Dn supplied from the data line driving circuit 101 to the pixels P. The scanning lines 3 are electrically connected to the scanning line driving circuit 102 described above, and supply scanning signals SC1, SC2, ..., SCm supplied from the scanning line driving circuit 102 to each pixel P.

The image signals D1 to Dn supplied from the data line driving circuit 101 to the data lines 6 may be supplied line-sequentially in this order, or may be supplied in groups to adjacent data lines 6. The scanning line driving circuit 102 supplies the scanning signals SC1 to SCm to the scanning lines 3 in a line-sequential manner in pulses at a predetermined timing.

In the liquid crystal device 100, the switching element TFT 30 is turned on for a certain period of time by the input of scanning signals SC1 to SCm. As a result, image signals D1 to Dn supplied from the data line 6 are written to the pixel electrode 15 at a certain timing. A drain potential corresponding to the image signal Dn is supplied to the pixel electrode 15. Then, the image signals D1 to Dn of a certain level written to the liquid crystal layer 50 via the pixel electrode 15 are held for a certain period of time between the pixel electrode 15 and the opposing electrode 21 arranged opposite to the liquid crystal layer 50 via the pixel electrode 15.

To prevent the image signal Dn from leaking from the held image signal D1, a capacitive element 16 is electrically connected in parallel to the liquid crystal capacitance provided between the pixel electrode 15 and the counter electrode 21. The semiconductor layer and the capacitive element 16 will be described in detail later.

Although not shown in FIG. 3, the data line 6 is connected to the inspection circuit 103 described above. Therefore, during the manufacturing process of the liquid crystal device 100, it is possible to detect the image signal via the inspection circuit 103 and check for operational defects of the liquid crystal device 100.

Next, the configuration of pixel P in the liquid crystal device 100 will be described with reference to FIG.

As shown in FIG. 4, the pixels P in the liquid crystal device 100 are arranged in a matrix in the ±X and ±Y directions in the display region E. The pixels P have, for example, an aperture region OP that is substantially rectangular in plan view. The aperture region OP extends in the ±X and ±Y directions and is surrounded by light-shielding non-aperture regions CL arranged in a lattice pattern.

The above-mentioned scanning lines 3 are provided in the non-opening region CL extending in the ±X direction. A light-shielding conductive material is used for the scanning lines 3, and the scanning lines 3 form part of the non-opening region CL.

The above-mentioned data lines 6 are provided in the non-aperture region CL extending in the ±Y direction. The data lines 6 are also made of a light-shielding conductive material, and form part of the non-aperture region CL.

The non-aperture region CL is composed of the scanning lines 3, data lines 6, TFTs 30, and capacitance lines 8 provided on the element substrate 10. Furthermore, the non-aperture region CL may include a light-shielding portion that is a black matrix patterned in a lattice shape and is provided on the opposing substrate 20 in the same layer as the parting portion 24 shown in FIG. 2.

In the non-aperture region CL extending in the ±X direction, the above-mentioned TFT 30 is provided in the middle of the ±X direction corresponding to each pixel P. In addition, in the non-aperture region CL extending in the ±Y direction, a capacitive element 16 is provided between adjacent pixels P. The detailed structure of the pixel P, including the contact hole and the capacitive element 16, will be described later.

A pixel electrode 15 having a substantially square shape in plan view is provided for each pixel P. The pixel electrode 15 is provided in the opening region OP so that its outer edge overlaps with the non-opening region CL. Multiple pixel electrodes 15 are arranged in a matrix corresponding to the pixels P.

As described above, the liquid crystal device 100 of this embodiment is a transmissive type, and is premised on light being incident from the opposing substrate 20 side. Therefore, the element substrate 10 has a structure that reduces not only the light that is directly incident on the TFT 30, but also diffracted light and reflected light that originate from the incident light. In addition, the liquid crystal device 100 has a capacitive element 16 with an increased storage capacitance.

The direction of incidence of light into the liquid crystal device 100 is not limited to the direction from the opposing substrate 20 side, but may be from the element substrate 10 side. In addition, the liquid crystal device 100 may be configured to include a focusing means, such as a microlens, that focuses the incident light for each pixel P on the substrate on the side where the light is incident.

Next, the cross-sectional configuration of the element substrate 10 of the liquid crystal device 100 will be described with reference to FIG. 5. Note that FIG. 5 shows four cross sections along the ±Z directions, including lines A1-A2, C1-C2, B1-B2, and D1-D2 in FIG. 4. Also, the alignment film 18 is not shown in FIG. 5.

As shown in FIG. 5, the element substrate 10 of the liquid crystal device 100 includes a substrate 10s, a scanning line 3, a TFT 30 including a semiconductor layer 30S and a gate electrode 30G, a capacitance element 16, a data line 6, and a plurality of interlayer insulating layers. The substrate 10s of the element substrate 10 has a trench TR. A first layer to a sixth layer are stacked on the substrate 10s as a plurality of layers.

The multiple layers in the element substrate 10 include, from the bottom up, a first layer including the scanning lines 3, a second layer including the semiconductor layers 30S, a third layer including the gate electrodes 30G, a fourth layer including the data lines 6, a fifth layer including the capacitance lines 8 as capacitance wiring, and a sixth layer including the pixel electrodes 15.

A first interlayer insulating layer 11a is provided between the first and second layers, a gate insulating layer 11b and a capacitance insulating layer 16b are provided between the second and third layers, a second interlayer insulating layer 11c is provided between the third and fourth layers, a third interlayer insulating layer 12 is provided between the fourth and fifth layers, and a fourth interlayer insulating layer 13 is provided between the fifth and sixth layers. This prevents short circuits from occurring between the layers.

The scanning lines 3 are provided in the first layer on the substrate 10s. The scanning lines 3 are provided in the non-opening region CL shown in FIG. 4 in plan view. The scanning lines 3 have a portion extending in the ±X direction and a portion protruding from the portion in the ±Y direction.

The scanning lines 3 can be made of a known material having light-shielding and electrical conductivity. Therefore, the scanning lines 3 mainly have the function of blocking light incident on the semiconductor layer 30S from below. In this embodiment, tungsten silicide is used as the material for the scanning lines 3. The thickness of the scanning lines 3 is, for example, about 150 nm. In this specification, the thickness of each layer in the ±Z direction is also simply referred to as the thickness.

A first interlayer insulating layer 11a is provided between the scanning line 3 and the second layer. The first interlayer insulating layer 11a insulates the scanning line 3 from the semiconductor layer 30S. A silicon-based oxide film or the like is used as the material for forming the first interlayer insulating layer 11a. Examples of the material include silicon oxide (None-doped Silicate Glass: NSG) and silicon nitride. In this embodiment, silicon oxide is used as the material for forming the first interlayer insulating layer 11a. The thickness of the first interlayer insulating layer 11a is, for example, about 200 nm.

The TFT 30 and the capacitance element 16 are provided in the second and third layers on the first layer. The TFT 30 has a semiconductor layer 30S provided in the second layer and a gate electrode 30G provided in the third layer. The semiconductor layer 30S of the TFT 30 has an LDD (Lightly Doped Drain) structure.

The semiconductor layer 30S is provided in the non-opening region CL shown in FIG. 4 in plan view. More specifically, the semiconductor layer 30S is bent from the ±X direction to the ±Y direction in response to the portion where the ±X direction and the ±Y direction intersect in the non-opening region CL (see FIG. 12). Of the semiconductor layer 30S, one source drain region s1, one LDD region s2, channel region s3, the other LDD region s4, and a part of the other source drain region s5 extend along the ±X direction at a position overlapping with the scanning line 3 in plan view.

The other source drain region s5 of the semiconductor layer 30S is bent from the ±X direction to the ±Y direction in a plan view and extends along the ±Y direction (see FIG. 16). The other source drain region s5 includes a first portion s5a and a second portion s5b. The first portion s5a is part of the other source drain region s5 extending in the ±Y direction, is located at a position overlapping the data line 6 in a plan view, and is also provided inside the trench TR described below. The second portion s5b is part of the other source drain region s5 extending in the ±Y direction, and also functions as a lower capacitance electrode of the capacitance element 16.

The semiconductor layer 30S has LDD regions s2 and s4, which have high electrical resistance, sandwiching the channel region s3. This suppresses leakage current when the device is off. From the viewpoint of suppressing leakage current when the device is off, the LDD region s4 may be included in the junction between the channel region s3 and the other source/drain region s5, to which the capacitance element 16 or pixel electrode 15 is electrically connected. The semiconductor layer 30S is made of, for example, a polysilicon film obtained by crystallizing an amorphous silicon film. The thickness of the semiconductor layer 30S is, for example, about 50 nm.

A gate insulating layer 11b is provided covering the semiconductor layer 30S. The gate insulating layer 11b is between the semiconductor layer 30S and the gate electrode 30G, and insulates the semiconductor layer 30S from the gate electrode 30G. The gate insulating layer 11b has a double structure made of, for example, two types of silicon oxide. The thickness of the gate insulating layer 11b is, for example, about 75 nm.

A capacitance insulating layer 16b is provided to cover a portion of the gate insulating layer 11b and a portion of the other source drain region s5. The portion of the capacitance insulating layer 16b that overlaps with the channel region s3 in a planar view, together with the gate insulating layer 11b, insulates the semiconductor layer 30S from the gate electrode 30G. The portion of the capacitance insulating layer 16b that overlaps with the other source drain region s5 functions as a dielectric layer of the capacitance element 16.

A dielectric material is used for the capacitive insulating layer 16b. Examples of dielectric materials include hafnium oxide, aluminum oxide, silicon oxide, silicon nitride, and tantalum oxide, and these films are used as a single layer or in combination. In this embodiment, silicon nitride is used as the dielectric material for the capacitive insulating layer 16b. The thickness of the capacitive insulating layer 16b is preferably thinner than the thickness of the gate insulating layer 11b, and is, for example, about 20 nm.

The third layer is provided with a gate electrode 30G facing the channel region s3 of the semiconductor layer 30S in the ±Z direction. The gate electrode 30G is composed of a first gate electrode g1 and a second gate electrode g2. The first gate electrode g1 is disposed above the channel region s3 via the gate insulating layer 11b and the capacitance insulating layer 16b. The second gate electrode g2 is disposed above the first gate electrode g1.

The material for forming the first gate electrode g1 is conductive polysilicon, metal silicide, metal, or metal compound. In this embodiment, the first gate electrode g1 has a two-layer structure of a conductive polysilicon film and a tungsten silicide film. The thickness of the first gate electrode g1 is, for example, about 150 nm.

Hereinafter, in this embodiment, a conductive polysilicon film refers to a polysilicon film that has been given conductivity by implanting phosphorus atoms. Note that the atoms to be implanted are not limited to phosphorus atoms.

The second gate electrode g2 is formed from a metal compound having light-shielding properties, such as tungsten silicide. The thickness of the second gate electrode g2 is, for example, about 60 nm.

The second gate electrode g2 is electrically connected to the scanning line 3 via a contact hole CNT1. The contact hole CNT1 penetrates the first interlayer insulating layer 11a, the gate insulating layer 11b, the capacitance insulating layer 16b, and the first gate electrode g1. The contact hole CNT1 is spaced apart from the semiconductor layer 30S and is disposed in a portion of the scanning line 3 that protrudes in the +Y direction (see Figures 19A and 20).

The trench TR is provided in the non-opening region CL described above along the +X direction side of the pixel P in a planar view. The trench TR is a recess that is approximately rectangular in planar view. The trench TR includes a bottom surface along the XY plane and side surfaces along the ±Z directions, and is open at the top.

The above-mentioned capacitance element 16 is provided within the trench TR. The capacitance element 16 is composed of the other source-drain region s5, the capacitance insulating layer 16b, the first upper capacitance electrode 16c, and the second upper capacitance electrode 4. The capacitance element 16 has the function of increasing the storage capacitance and improving the potential storage characteristics of the pixel electrode 15.

The layers constituting the capacitance element 16 described above are provided to cover the side and bottom surfaces of the trench TR. In addition to being provided inside the trench TR, a portion of the capacitance element 16 is also provided on the upper edge of the trench TR.

A second interlayer insulating layer 11c is provided above the gate electrode 30G, the first upper capacitance electrode 16c, and the second upper capacitance electrode 4, covering them. The second interlayer insulating layer 11c is also provided at a position where it overlaps with the TFT 30 in plan view. The second interlayer insulating layer 11c is provided using one or more types of silicon oxide films, such as a TEOS (Tetraethyl Orthosilicate) film, an NSG film, a PSG (Phosphosilicate Glass) film containing phosphorus (P), a BSG (Borosilicate Glass) film containing boron (B), and a BPSG (Borophosphosilicate Glass) film containing boron and phosphorus. In this embodiment, silicon oxide is used as the material for forming the second interlayer insulating layer 11c. The thickness of the second interlayer insulating layer 11c is, for example, about 400 nm.

Contact holes CNT2 and CNT3 are provided in the second interlayer insulating layer 11c. The contact holes CNT2 and CNT3 penetrate the second interlayer insulating layer 11c and the gate insulating layer 11b to reach the semiconductor layer 30S. In more detail, the contact hole CNT2 electrically connects one source drain region s1 of the semiconductor layer 30S to the data line 6 in the upper layer. The contact hole CNT3 electrically connects the other source drain region s5 of the semiconductor layer 30S to the second relay layer 7 described later.

In the fourth layer on the third layer, the data line 6 and the second relay layer 7 are provided, covering the second interlayer insulating layer 11c and the like. As described above, the data line 6 extends in the ±Y direction in the non-aperture region CL of the pixel P. The data line 6 is electrically connected to one of the source/drain regions s1 of the semiconductor layer 30S via the contact hole CNT2.

The second relay layer 7 is provided in an independent island shape in a plan view (see FIG. 30). The second relay layer 7 is electrically connected to the other source/drain region s5 of the semiconductor layer 30S via the contact hole CNT3.

The second relay layer 7 also functions as a first light-shielding wall 7a and a second light-shielding wall 7b by covering the side and bottom surfaces of the first slit 17a and the second slit 17b, which are recesses provided along the scanning line 3 (see FIG. 30). The first light-shielding wall 7a and the second light-shielding wall 7b mainly block light from the ±Z direction and its diagonal directions, and the ±Y direction and its diagonal directions.

The first light-shielding wall 7a and the second light-shielding wall 7b are arranged on both sides of the ±Y direction (second direction) sandwiching the TFT 30. Specifically, the first light-shielding wall 7a and the second light-shielding wall 7b are arranged on both sides of the ±Y direction (second direction) sandwiching at least the LDD regions s2 and s4 of the semiconductor layer 30S. Therefore, since the light-shielding walls 7a and 7b are arranged on both sides of the second direction sandwiching the LDD regions s2 and s4 that are likely to affect the characteristics of the TFT 30, it is possible to suppress light from entering the LDD regions s2 and s4. The light-shielding of the structure in which the semiconductor layer 30S is stacked along the scanning line 3 can be strengthened.

The first slit 17a and the second slit 17b penetrate the second interlayer insulating layer 11c, the gate insulating layer 11b, and the first interlayer insulating layer 11a, and are formed by being dug into the substrate 10s. That is, the light-shielding walls 7a and 7b are arranged from above the gate electrode 30G to below the scanning line 3. Therefore, the light-shielding walls 7a and 7b can block light incident from above the TFT 30. Furthermore, it is possible to block light reflected on the substrate 10s side (i.e., back reflection), and light incident on the TFT 30 can be suppressed.

The materials for forming the data line 6, the second relay layer 7, and the light-shielding walls 7a and 7b are not particularly limited as long as they are conductive low-resistance wiring materials, and examples include metals such as aluminum (Al) and titanium (Ti) and their metal compounds. In this embodiment, the data line 6 and the second relay layer 7 have a four-layer structure of a titanium (Ti) layer/titanium nitride (TiN) layer/aluminum (Al) layer/titanium nitride (TiN) layer. The thickness of the data line 6 and the second relay layer 7 is, for example, about 350 nm.

A third interlayer insulating layer 12 is provided to cover the data line 6, the second relay layer 7, and the light-shielding walls 7a, 7b. For example, the same material as the first interlayer insulating layer 11a is used for the third interlayer insulating layer 12. In this embodiment, silicon oxide is used for the third interlayer insulating layer 12. The thickness of the third interlayer insulating layer 12 is, for example, about 400 nm.

Contact holes CNT4 and CNT5 are provided in the third interlayer insulating layer 12. The contact hole CNT4 penetrates the second interlayer insulating layer 11c and the third interlayer insulating layer 12 to electrically connect the second upper capacitance electrode 4 of the capacitance element 16 to the capacitance line 8.

The contact hole CNT5 penetrates the third interlayer insulating layer 12 and electrically connects the second relay layer 7 and the first relay layer 9.

The fifth layer above the fourth layer is provided with a capacitance line 8 and a first relay layer 9. The capacitance line 8 overlaps with the data line 6 extending in the ±Y direction in plan view (see Figures 32 and 33). Although not shown, the capacitance line 8 is electrically connected to the upper and lower conductive parts 106 of the counter substrate 20 described above. Therefore, the capacitance line 8 is electrically connected to the counter electrode 21 and a common potential is applied. This prevents the potential of the data line 6 and the scanning line 3 from affecting the pixel electrode 15 by the capacitance line 8. The capacitance line 8 is also electrically connected to the first upper capacitance electrode 16c and the second upper capacitance electrode 4 of the capacitance element 16 through the contact hole CNT4.

The first relay layer 9 is provided in an independent island shape in a plan view (see FIG. 34). The first relay layer 9 is electrically connected to the second relay layer 7 via the contact hole CNT5.

The material for forming the capacitance line 8 and the first relay layer 9 is not particularly limited as long as it is a conductive low-resistance wiring material, as with the data line 6, but examples include metals such as aluminum (Al) and titanium (Ti) and their metal compounds. In this embodiment, the capacitance line 8 and the first relay layer 9 have a four-layer structure of a titanium (Ti) layer/titanium nitride (TiN) layer/aluminum (Al) layer/titanium nitride (TiN) layer. The thickness of the capacitance line 8 and the first relay layer 9 is, for example, about 250 nm.

A fourth interlayer insulating layer 13 is provided to cover the capacitance line 8 and the first relay layer 9. Examples of materials for the fourth interlayer insulating layer 13 include a silicon-based oxide film similar to the first interlayer insulating layer 11a. In this embodiment, silicon oxide is used for the fourth interlayer insulating layer 13. The thickness of the fourth interlayer insulating layer 13 is, for example, about 300 nm.

A contact hole CNT6 is provided in the fourth interlayer insulating layer 13. The contact hole CNT6 electrically connects the first relay layer 9 and the pixel electrode 15. The contact hole CNT6 overlaps with the contact hole CNT1 in a plan view (see Figures 22 and 36).

A pixel electrode 15 is provided on the sixth layer above the fifth layer. The pixel electrode 15 is electrically connected to the other source/drain region s5, which also serves as the lower capacitance electrode of the capacitance element 16, via the contact hole CNT6, the first relay layer 9, the contact hole CNT5, the second relay layer 7, and the contact hole CNT3. The pixel electrode 15 is provided by forming a transparent conductive film such as ITO or IZO, and then patterning it. In this embodiment, ITO is used for the pixel electrode 15. The thickness of the pixel electrode 15 is, for example, about 145 nm.

Although not shown, an alignment film 18 is provided to cover the pixel electrodes 15. The alignment film 18 of the element substrate 10 and the alignment film 22 of the opposing substrate 20 described above are made of a collection of columns in which an inorganic material such as silicon oxide is evaporated from a specific direction, such as an oblique direction, and grown into a columnar shape. In addition, the liquid crystal molecules contained in the liquid crystal layer 50 shown in FIG. 2 have negative dielectric anisotropy with respect to the alignment films 18 and 22.

Next, a method for manufacturing the liquid crystal device 100 will be described with reference to Figures 6 to 38.

Figure 6 is a process flow diagram showing the manufacturing method of the element substrate 10 in the manufacturing method of the liquid crystal device 100. Figures 7, 9, 11, 13, 15A, 15B, 17, 19A, 19B, 21, 23, 25, 27, 29, 31, 33, 35, and 37 are schematic cross-sectional views showing the manufacturing method of the element substrate 10. Figures 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 are schematic plan views showing the manufacturing method of the element substrate 10. In the following description, reference will also be made to Figure 5.

In the schematic cross-sectional view, as in FIG. 5, four cross sections corresponding to lines A1-A2, C1-C2, B1-B2, and D1-D2 (see FIG. 25 onwards) shown in FIG. 4 are shown side by side. Furthermore, the schematic plan view shows an enlarged view of the periphery of one opening region OP shown in FIG. 4. In the following explanation of the schematic plan view, unless otherwise specified, the plan view will be described.

The manufacturing method of the liquid crystal device 100 of this embodiment includes the manufacturing method of the element substrate 10 described below, and publicly known techniques can be used for the steps other than those included in the manufacturing method of the element substrate 10. Therefore, in the following explanation, only the manufacturing method of the element substrate 10 will be described. Furthermore, publicly known techniques can be used for the manufacturing method of the element substrate 10, unless otherwise specified.

As shown in FIG. 6, the method for manufacturing the element substrate 10 of this embodiment includes steps S1 to S13. Each step from step S1 to step S13 will be described below. Note that the process flow shown in FIG. 6 is an example and is not limited to this.

In step S1, as shown in Figures 7 and 8, a scanning line 3 and a trench TR are formed on a substrate 10s. First, a scanning line 3 is provided on the substrate 10s. The scanning line 3 has a portion extending in the ±X direction and a portion protruding from the above portion in the +Y direction. A contact hole CNT1 is provided in the portion protruding in the +Y direction (see Figure 20). The scanning line 3 is formed, for example, by patterning using a photolithography method.

Next, a trench TR is provided. The trench TR is a substantially rectangular recess between adjacent pixels P in the ±X direction and fits into the non-opening region CL. The trench TR has, for example, a depth of about 3 μm in the ±Z direction and a width of about 1 μm in the ±X direction. The trench TR is formed, for example, by wet etching using a hard mask. Then, proceed to step S2.

9 and 10, a first interlayer insulating layer 11a is provided in a solid form on the substrate 10s including the inside of the scanning line 3 and the trench TR. The first interlayer insulating layer 11a is formed by atmospheric pressure chemical vapor deposition (CVD), low pressure CVD, plasma CVD, or the like using a process gas such as monosilane ( _SiH4 ), silane _dichloride ( _SiH2Cl2 ), tetraethyl orthosilicate (TEOS), or ammonia ( _NH3 ).

At this time, the trench TR is also covered with the first interlayer insulating layer 11a, and the forming conditions are adjusted so that the width of the recess in the ±X direction is narrowed. The ±X direction width of the recess covered with the first interlayer insulating layer 11a is narrower than the ±X direction width of the trench TR when formed by wet etching. For example, the ±X direction width of the recess is set to about 0.3 μm compared to the ±X direction width of about 1 μm when the trench TR is formed. This makes it possible to narrow the ±X direction width of the capacitance element 16 provided in the trench TR, and the capacitance element 16 can be accommodated in the non-opening region CL. Furthermore, the trench TR is filled with the capacitance element 16 provided in the trench TR. Therefore, the data line 6 provided in the upper layer will not fall into the recess caused by the trench TR, and disconnection of the data line 6 can be prevented. Then proceed to step S3.

In step S3, a semiconductor layer 30S is provided on the first interlayer insulating layer 11a, including inside the trench TR. The semiconductor layer 30S is a polysilicon film, and is formed by using a low-pressure CVD method or the like, and is patterned as shown in Figures 11 and 12.

The semiconductor layer 30S is bent from the ±X direction to the ±Y direction. Although not shown in the figure, the semiconductor layer 30S is arranged so as to overlap the non-opening region CL. Then, proceed to step S4.

In step S4, as shown in Figures 13 and 14, a gate insulating layer 11b is provided in a solid form on the semiconductor layer 30S and the first interlayer insulating layer 11a. When, for example, a double structure made of two types of silicon oxide is used as the gate insulating layer 11b, a first silicon oxide film obtained by thermally oxidizing a polysilicon film is provided, and then a second silicon oxide film is provided under high temperature conditions of 700°C to 900°C using a reduced pressure CVD method. At this time, the inside of the trench TR is also covered with the gate insulating layer 11b. Then, proceed to step S5.

In step S5, as shown in Figures 15A, 15B, and 16, the other source/drain region s5, which is the lower capacitance electrode of the capacitance element 16, is formed. First, a resist RE is formed in the trench TR and in the area excluding the edge of the trench TR. The area where the resist RE is not arranged corresponds to the portion of the other source/drain region s5 of the semiconductor layer 30S that functions as the lower capacitance electrode of the capacitance element 16.

Next, ions are implanted into the semiconductor layer 30S. First, the semiconductor layer 30S in the trench TR and at the edge of the trench TR, which are areas where the resist RE is not arranged, is made conductive. At this time, ions are implanted into the semiconductor layer 30S through the gate insulating layer 11b. As a result, as shown in FIG. 15A, the semiconductor layer 30S in the trench TR and at the edge of the trench TR becomes the other source/drain region s5. The ions implanted are, for example, phosphorus (P).

Next, the gate insulating layer 11b in the trench TR and at the edge of the trench TR where the resist RE is not placed is removed by wet etching. After that, all of the resist RE is removed. Then, proceed to step S6.

In step S6, an insulating layer 16x is formed. The insulating layer 16x is a layer that will become the capacitive insulating layer 16b in a later step. As shown in Figures 17 and 18, the insulating layer 16x is provided in a solid form in the trench TR and on the other source/drain region s5 at the edge of the trench TR, and on the gate insulating layer 11b. Specifically, the insulating layer 16x is provided by low-pressure CVD or plasma CVD using silicon nitride. Then, proceed to step S7.

In step S7, a second conductive layer 16y and a third conductive layer 4x are formed. The second conductive layer 16y is a layer that will become the first gate electrode g1 and the first upper capacitance electrode 16c in a later process. The third conductive layer 4x is a layer that will become the second gate electrode g2 and the second upper capacitance electrode 4 in a later process.

First, the second conductive layer 16y is provided in a solid form on the insulating layer 16x. Specifically, after providing a polycrystalline silicon film by low pressure CVD, phosphorus is injected into the polycrystalline silicon film and then diffused to form a conductive polysilicon film. The concentration of phosphorus atoms in the second conductive layer 16y is set to 1×10 ¹⁹ atoms/cm ³ or more. At this time, the trench TR is filled with the second conductive layer 16y.

Next, as shown in FIG. 19A, a contact hole CNT1 is provided that is spaced apart from the semiconductor layer 30S in the +Y direction. The contact hole CNT1 penetrates the second conductive layer 16y, the insulating layer 16x, the gate insulating layer 11b, and the first interlayer insulating layer 11a, and reaches the scanning line 3. The contact hole CNT1 is formed by, for example, dry etching.

Next, as shown in FIG. 19B and FIG. 20, a third conductive layer 4x is provided in a solid manner on the second conductive layer 16y. At this time, the third conductive layer 4x is provided so as to fill the contact hole CNT1, and electrically connects the scanning line 3 and the third conductive layer 4x. Then, proceed to step S8.

In step S8, as shown in FIG. 21, the gate electrode 30G and the capacitance element 16 are formed. Specifically, the insulating layer 16x, the second conductive layer 16y, and the third conductive layer 4x are patterned using dry etching.

As a result, a gate electrode 30G consisting of a first gate electrode g1 and a second gate electrode g2 is provided on the gate insulating layer 11b via the capacitance insulating layer 16b. At this time, in a plan view, the silicon nitride insulating layer 16x is removed from areas other than the gate electrode 30G and the second upper capacitance electrode 4. This makes it easier to hydrogenate the semiconductor layer 30S.

The above patterning also provides a capacitance element 16 consisting of a portion of the other source drain region s5, the capacitance insulating layer 16b, the first upper capacitance electrode 16c, and the second upper capacitance electrode 4.

As shown in FIG. 22, the gate electrode 30G is arranged in an island shape in a plan view, and has a portion that overlaps with the contact hole CNT1 and a portion that overlaps with the semiconductor layer 30S (not shown).

The second upper capacitive electrode 4 is provided extending in the ±Y direction so as to overlap with the non-opening region CL extending in the ±Y direction. The second upper capacitive electrode 4 has a main body portion 4a extending in the ±Y direction and overlapping with the data line 6 provided above, and a protruding portion 4b protruding in the -X direction from the main body portion 4a. The protruding portion 4b overlaps with a portion of the semiconductor layer 30S extending in the ±X direction. The capacitive insulating layer 16b and the first upper capacitive electrode 16c are arranged so as to overlap with the second upper capacitive electrode 4. Then, proceed to step S9.

In step S9, as shown in FIG. 23, one source/drain region s1, LDD regions s2 and s4, a channel region s3, and a portion of the other source/drain region s5 are formed in the semiconductor layer 30S by ion implantation. Specifically, medium-concentration ion implantation and subsequent high-concentration ion implantation are performed on the semiconductor layer 30S.

First, LDD regions s2 and s4 are formed by medium-concentration ion implantation, sandwiching channel region s3 in the ±X direction. Next, the LDD regions s2 and s4 and channel region s3 of semiconductor layer 30S are masked with the resist RE pattern shown in FIG. 24, and high-concentration ion implantation is performed on the rest of semiconductor layer 30S. This forms source-drain regions s1 and s5. Then proceed to step S10.

In step S10, as shown in FIG. 25, the second interlayer insulating layer 11c and the like are formed. First, the second interlayer insulating layer 11c is provided on the second gate electrode g2, the second upper capacitance electrode 4, and the gate insulating layer 11b exposed upward. Examples of methods for forming the silicon oxide that constitutes the second interlayer insulating layer 11c include atmospheric pressure CVD, reduced pressure CVD, and plasma CVD using monosilane, silane dichloride, TEOS, TEB (Triethyl Borate), and the like.

Next, impurity activation annealing is performed by heating to approximately 1000°C. After that, hydrogen plasma processing is performed. As a result, defects in the semiconductor layer 30S are terminated with hydrogen, improving the characteristics of the switching element.

In step S11, as shown in Figures 25 and 26, slits 17a and 17b are formed by dry etching. The slits 17a and 17b are grooves for providing the light-shielding walls 7a and 7b. As described above, the slits 17a and 17b penetrate the first interlayer insulating layer 11a, the gate insulating layer 11b, and the second interlayer insulating layer 11c to reach the substrate 10s and are also formed in the substrate 10s. The slits 17a and 17b are arranged opposite each other in the ±Y direction (i.e., the second direction) with at least the LDD regions s2 and s4 of the semiconductor layer 30S in between. Note that in the B1-B2 cross section, the first slit 17a is formed, but only a portion of the second slit 17b is formed due to the gate electrode 30G being arranged therein.

In step S12, as shown in Figures 27 to 30, the light shielding walls 7a, 7b and the data lines 6 are formed. First, as shown in Figure 27, a cover layer 14 made of a silicon oxide film or the like is formed on the second interlayer insulating layer 11c including the insides of the slits 17a, 17b by using a CVD method or an ALD (Atomic Layer Deposition) method. The cover layer 14 is a film for ensuring insulation between the light shielding walls 7a, 7b and the scanning lines 3 to be formed later. The thickness of the cover layer 14 is, for example, 50 nm to 200 nm.

Next, as shown in Figures 27 and 28, contact holes CNT2 and CNT3 are formed by dry etching. The contact holes CNT2 and CNT3 penetrate the cover layer 14, the second interlayer insulating layer 11c, and the gate insulating layer 11b to reach the semiconductor layer 30S. In a plan view, the contact hole CNT2 overlaps one of the source drain regions s1, and the contact hole CNT3 overlaps a portion of the other source drain region s5 adjacent to the LDD region s4. Then, proceed to step S12.

Next, the light-shielding walls 7a and 7b, the data line 6, and the second relay layer 7 are provided. At this time, as shown in FIG. 29, the data line 6 and the second relay layer 7 are provided so as to fill the contact holes CNT2 and CNT3, respectively. Furthermore, the light-shielding walls 7a and 7b are provided by forming the same film as the data line 6 and the second relay layer 7 on the side and bottom surfaces of the slits 17a and 17b.

In this way, the light-shielding walls 7a and 7b are arranged facing each other in the ±Y direction (i.e., the second direction) across the LDD regions s2 and s4, so that light incident on the liquid crystal device 100 can be prevented from entering the LDD regions s2 and s4.

Also, as shown in FIG. 29, the slits 17a, 17b (i.e., the light-shielding walls 7a, 7b) are arranged so as to overlap a portion of the scanning line 3 in the second direction (overlapping portion 7c). In this way, the light-shielding walls 7a, 7b are arranged so as to overlap a portion of the scanning line 3, so that they can be brought closer to the scanning line 3 side compared to when they are arranged without overlapping with the scanning line 3. Therefore, by providing the light-shielding walls 7a, 7b, it is possible to prevent the aperture ratio from decreasing drastically.

In addition, the light-shielding walls 7a and 7b are at the drain potential, which is the same potential as the second relay layer 7. Since the TFT 30 is sandwiched between the light-shielding walls 7a and 7b, which are at the drain potential, the effect on the characteristics of the TFT 30 can be reduced.

As shown in FIG. 30, the data line 6 extends in the ±Y direction and overlaps with a portion of the other source drain region s5 (not shown) that extends in the ±Y direction. That is, the data line 6 extends in the ±Y direction so as to overlap the trench TR and the capacitive element 16 in a planar view. The data line 6 overlaps with the non-opening region CL that extends in the ±X direction and has a portion that protrudes in the +X direction. A contact hole CNT2 is provided in this portion.

The second relay layer 7 is provided in an island shape independent of the data line 6. The second relay layer 7 extends in the ±X direction and has a main body portion 7d that overlaps with a part of the underlying semiconductor layer 30S, and a protrusion portion 7e that protrudes from the main body portion 7d in the ±Y direction.

The data line 6 and one of the source/drain regions s1 of the semiconductor layer 30S are electrically connected via a contact hole CNT2. The second relay layer 7 and the other of the source/drain regions s5 of the semiconductor layer 30S are electrically connected via a contact hole CNT3. Then, proceed to step S13.

In step S13, layers above the data line 6 are formed. First, the third interlayer insulating layer 12 is provided in a solid form on the data line 6, the second relay layer 7, the light-shielding walls 7a and 7b, and the second interlayer insulating layer 11c. The third interlayer insulating layer 12 is provided by plasma CVD using, for example, a silicon oxide film.

Next, as shown in Figures 31 and 32, contact holes CNT4 and CNT5 are formed by dry etching. Contact hole CNT4 penetrates the third interlayer insulating layer 12 and the second interlayer insulating layer 11c, and reaches the second upper capacitance electrode 4 of the capacitance element 16. Contact hole CNT5 penetrates the third interlayer insulating layer 12, and reaches the second relay layer 7.

Next, as shown in FIG. 33, the capacitance line 8 and the first relay layer 9 are formed. At this time, the capacitance line 8 and the first relay layer 9 are provided so as to fill the contact holes CNT4 and CNT5.

The capacitance line 8 is electrically connected to the second upper capacitance electrode 4 through the contact hole CNT4. The first relay layer 9 is electrically connected to the other source/drain region s5 of the semiconductor layer 30S through the contact hole CNT5, the second relay layer 7, and the contact hole CNT3.

As shown in FIG. 34, the capacitance line 8 is provided extending in the ±Y direction so as to overlap with the non-opening region CL extending in the ±Y direction. The capacitance line 8 has a main body portion 8a extending in the ±Y direction overlapping with the data line 6 provided below, a protrusion portion 8b protruding from the main body portion 8a in the -X direction, and another protrusion portion 8c protruding from the main body portion 8a in the +X direction on the opposite side to the protrusion portion 8b. The protrusion portion 8b overlaps with a portion of the semiconductor layer 30S extending in the ±X direction. A contact hole CNT4 is provided in the protrusion portion 8b. The other protrusion portion 8c overlaps with another semiconductor layer 30S (not shown) adjacent to the semiconductor layer 30S in the +X direction.

The first relay layer 9 is provided as an island independent of the capacitance line 8 and overlaps the contact hole CNT5. The first relay layer 9 extends in the ±X direction and has a main body portion 9a that overlaps with a part of the underlying semiconductor layer 30S, and a protrusion portion 9b that protrudes from the main body portion 9a in the ±Y direction.

Next, as shown in Figures 35 and 36, a fourth interlayer insulating layer 13 is provided in a solid state on the capacitance line 8, the first relay layer 9, and the third interlayer insulating layer 12 exposed above. The fourth interlayer insulating layer 13 is provided by a plasma CVD method using, for example, a silicon oxide film. After providing the fourth interlayer insulating layer 13, a planarization process such as CMP (Chemical & Mechanical Polishing) is performed to reduce unevenness caused by the configuration of the lower layers.

Next, a contact hole CNT6 is provided by dry etching, penetrating the fourth interlayer insulating layer 13 to expose the first relay layer 9. Thereafter, as shown in Figures 37 and 38, a pixel electrode 15 corresponding to the opening region OP (see Figure 4) is provided on the fourth interlayer insulating layer 13. At this time, the contact hole CNT6 is provided so as to fill it. As a result, the pixel electrode 15 is electrically connected to the other source/drain region s5 of the semiconductor layer 30S via the contact hole CNT6, the first relay layer 9, the contact hole CNT5, the second relay layer 7, and the contact hole CNT3.

The subsequent steps in the method for manufacturing the element substrate 10 can use known techniques, and will not be described here. The element substrate 10 and liquid crystal device 100 are manufactured by the manufacturing method described above.

Next, the configuration of the projection display device 1000 as an electronic device will be described with reference to FIG. 39.

As shown in FIG. 39, the projection display device 1000 as an electronic device includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, three liquid crystal devices 1B, 1G, and 1R as electro-optical panels, three reflecting mirrors 1111, 1112, and 1113, three relay lenses 1121, 1122, and 1123, a dichroic prism 1130 as a color synthesis optical system, and a projection lens 1140 as a projection optical system.

The lamp unit 1001 employs, for example, a discharge type light source. The light source type is not limited to this, and a solid-state light source such as a light-emitting diode or laser may also be employed.

The light emitted from the lamp unit 1001 is separated by two dichroic mirrors 1011 and 1012 into three colored lights each having a different wavelength range. The three colored lights are approximately red light, approximately green light, and approximately blue light. In the following description, the approximately red light is also referred to as red light R, the approximately green light is also referred to as green light G, and the approximately blue light is also referred to as blue light B.

Dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. The red light R that transmits through dichroic mirror 1011 is reflected by reflecting mirror 1111 and enters liquid crystal device 1R. The green light G reflected by dichroic mirror 1011 is reflected by dichroic mirror 1012 and then enters liquid crystal device 1G. The blue light B reflected by dichroic mirror 1011 transmits through dichroic mirror 1012 and is emitted to relay lens system 1120.

The relay lens system 1120 has relay lenses 1121, 1122, and 1123, and reflecting mirrors 1112 and 1113. Blue light B has a longer optical path than green light G and red light R, so the luminous flux tends to become larger. For this reason, relay lens 1122 is used to suppress the expansion of the luminous flux. Blue light B that enters relay lens system 1120 is reflected by reflecting mirror 1112 and is converged by relay lens 1121 near relay lens 1122. Then, blue light B passes through reflecting mirror 1113 and relay lens 1123 and enters liquid crystal device 1B.

The liquid crystal device 100 as the electro-optical device of the above embodiment is applied to the liquid crystal devices 1R, 1G, and 1B, which are light modulation devices, in the projection display device 1000. In addition, liquid crystal devices other than those of this embodiment may be applied to the liquid crystal devices 1R, 1G, and 1B.

Each of the liquid crystal devices 1R, 1G, and 1B is electrically connected to a higher-level circuit of the projection display device 1000. As a result, image signals specifying the gradation levels of the red light R, green light G, and blue light B are supplied from external circuits and processed by the higher-level circuit. This drives the liquid crystal devices 1R, 1G, and 1B, modulating the respective color lights.

The red light R, green light G, and blue light B modulated by the liquid crystal devices 1R, 1G, and 1B are incident on the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. In the dichroic prism 1130, the red light R and blue light B are reflected at 90 degrees, and the green light G is transmitted. Therefore, the red light R, green light G, and blue light B are combined as display light that displays a color image, and are emitted toward the projection lens 1140.

The projection lens 1140 is disposed facing the outside of the projection display device 1000. The display light is magnified and emitted through the projection lens 1140, and projected onto the screen 1200, which is the projection target.

In this embodiment, a projection display device 1000 is exemplified as an electronic device, but the electronic devices to which the electro-optical device of the present invention is applied are not limited to this. For example, the device may be applied to electronic devices such as a projection type HUD (Head-Up Display), a direct-view type HMD (Head Mounted Display), a personal computer, a digital camera, and an LCD television.

As described above, the liquid crystal device 100 of this embodiment includes a substrate 10s, a scanning line 3 extending in a first direction, a data line 6 extending in a second direction intersecting the first direction, and one source/drain region s1, one LDD region s2, a channel region s3, the other LDD region s4, and a first portion s5a of the other source/drain region s5 (see FIG. 16) extending along the first direction at a position overlapping the scanning line 3, and a second portion s5b of the other source/drain region (see FIG. 16) at a position overlapping the data line 6. The TFT 30 has a semiconductor layer 30S extending along the second direction, and a capacitive element 16 including at least a second portion s5b at a position overlapping the data line 6. Light-shielding walls 7a and 7b are arranged on both sides of one LDD region s2 and the other LDD region s4 extending along the first direction, and the substrate 10s has recesses 17a and 17b in the region overlapping with the light-shielding walls 7a and 7b, and parts of the light-shielding walls 7a and 7b are arranged along the side and bottom surfaces of the recesses 17a and 17b.

According to this configuration, the light shielding walls 7a and 7b are arranged on both sides of the TFT 30 in the second direction, so that it is possible to easily block light from the second direction that is likely to enter the TFT 30, and the display quality can be improved. Furthermore, a high aperture ratio and a storage capacity can be ensured. Furthermore, the light shielding walls 7a and 7b are arranged on both sides of the LDD regions s2 and s4 in the second direction, which are likely to affect the characteristics of the TFT 30, so that it is possible to prevent light from entering the LDD regions s2 and s4. Furthermore, the light shielding walls 7a and 7b are provided on the side and bottom of the slits 17a and 17b provided in the substrate 10s, so that it is possible to block light reflected on the substrate 10s side with the ends 17d (see FIG. 5) of the light shielding walls 7a and 7b, and it is possible to prevent light from entering the TFT 30. That is, it is possible to block light reflected from the back surface. Furthermore, Light shielding walls 7a and 7b are arranged from one LDD region s2 to the other LDD region s4, so that light is prevented from entering the LDD regions s2 and s4, which are likely to affect the characteristics of the TFT 30.

In addition, in the liquid crystal device 100, the TFT 30 has a gate electrode 30G, and the end 17c (see FIG. 5) of the light-shielding walls 7a and 7b that is away from the substrate 10s is preferably arranged in a layer above the gate electrode 30G. With this configuration, the light-shielding walls 7a and 7b are arranged up to a layer above the gate electrode 30G, so that the light-shielding walls 7a and 7b can block light that enters from above the TFT 30.

In addition, in the liquid crystal device 100, it is preferable that the light-shielding walls 7a and 7b are arranged so as to overlap a portion of the scanning line 3 in the second direction. With this configuration, the light-shielding walls 7a and 7b are arranged so as to overlap a portion of the scanning line 3, so that they can be brought closer to the scanning line 3 side compared to a case where they are arranged without overlapping with the scanning line 3. Therefore, by providing the light-shielding walls 7a and 7b, it is possible to prevent the aperture ratio from decreasing drastically.

In addition, in the liquid crystal device 100, it is preferable that the light-shielding walls 7a and 7b are at drain potential. With this configuration, the TFT 30 is sandwiched between the light-shielding walls 7a and 7b at the drain potential, so that the effect on the characteristics of the TFT 30 can be reduced.

In addition, in the liquid crystal device 100, the light-shielding walls 7a and 7b are preferably made of a material that contains aluminum. With this configuration, the light-shielding walls 7a and 7b are made of a material that contains aluminum, which makes it difficult for light to pass through, thereby improving the light-shielding properties.

In addition, since the electronic device of this embodiment includes the liquid crystal device 100 described above, it is possible to provide an electronic device that can improve the display quality.

Below, we will explain some variations of the above embodiment.

The light-shielding walls 7a and 7b of the liquid crystal device 100 described above are provided from one LDD region s2 to the other LDD region s4, but this is not limited thereto. For example, they may be provided on both sides in the second direction to sandwich only the other LDD region s4. In this way, the light-shielding walls are provided to sandwich the LDD region s4 on the drain potential side, which is likely to affect the characteristics of the TFT 30, so that light can be effectively shielded using a small amount of material.

In addition, while the liquid crystal device 100 has been described as an example of an electro-optical device, the present invention is not limited to this and may be applied to, for example, an organic EL device, a plasma display, electronic paper (EPD), etc.

3...scanning line, 4...second upper capacitance electrode, 4a...main body, 4b...protruding portion, 4x...third conductive layer, 6...data line, 7...second relay layer, 7a...first light-shielding wall, 7b...second light-shielding wall, 7c...overlapping portion, 7d...main body, 7e...protruding portion, 8...capacitance line, 8a...main body, 8b...protruding portion, 8c...other protruding portion, 9...first relay layer, 9a...main body, 9b...protruding portion, 10...element substrate, 1 0s...substrate, 11a...first interlayer insulating layer, 11b...gate insulating layer, 11c...second interlayer insulating layer, 12...third interlayer insulating layer, 13...fourth interlayer insulating layer, 14...cover layer, 15...pixel electrode, 16...capacitive element, 16b...capacitive insulating layer, 16c...first upper capacitive electrode, 16x...insulating layer, 16y...second conductive layer, 17a...first slit as recess, 17b...second slit as recess , 18...alignment film, 20...opposing substrate, 20s...substrate, 21...opposing electrode, 22...alignment film, 24...partition, 25...insulating layer, 30...TFT as transistor, 30G...gate electrode, 30S...semiconductor layer, 40...sealing material, 50...liquid crystal layer, 100...liquid crystal device, 101...data line driving circuit, 102...scanning line driving circuit, 103...inspection circuit, 104...external connection terminal, 106...upper and lower conductive portion, 107...wiring, 1000...projection type display device, 1001...lamp unit, 1011, 1012...dichroic mirror, 1111, 1112, 1113...reflection mirror, 1120...relay lens system, 1121, 1122, 1123...relay lens, 1130...dichroic prism, 1140...projection lens, 1200...screen.

Claims (7)

A substrate having a recess ;
A scanning line extending along a first direction;
data lines extending along a second direction intersecting the first direction;
a transistor having a semiconductor layer, in which one source/drain region, one LDD region, a channel region, the other LDD region, and a first portion of the other source/drain region extend along the first direction at a position overlapping the scan line, and a second portion of the other source/drain region extends along the second direction at a position overlapping the data line;
a light-shielding wall disposed along the one LDD region or the other LDD region , and a portion of the light-shielding wall disposed within a recess of the substrate;
Electro-optical device. 2. The electro-optical device according to claim 1,
The transistor has a gate electrode,
an end portion of the light-shielding wall opposite to the substrate is disposed farther from the substrate than an end portion of the gate electrode opposite to the substrate, in accordance with an electro-optical device; 3. The electro-optical device according to claim 1,
an electro-optical device comprising : another light-shielding wall provided to sandwich the semiconductor layer and disposed along the one LDD region , the channel region, and the other LDD region; 4. The electro-optical device according to claim 1,
The electro-optical device , wherein the light blocking wall is disposed so as to overlap a part of the scanning line. 5. The electro-optical device according to claim 1,
The electro-optical device according to claim 1, wherein the light-shielding wall is electrically connected to the other of the source/drain regions . 6. The electro-optical device according to claim 1,
The electro-optical device, wherein the light-shielding wall is made of a material containing aluminum. An electronic device comprising the electro-optical device according to any one of claims 1 to 6.

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