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JP7306289B2 - semiconductor devices and amplifiers - Google Patents

semiconductor devices and amplifiers Download PDF

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Publication number
JP7306289B2
JP7306289B2 JP2020020547A JP2020020547A JP7306289B2 JP 7306289 B2 JP7306289 B2 JP 7306289B2 JP 2020020547 A JP2020020547 A JP 2020020547A JP 2020020547 A JP2020020547 A JP 2020020547A JP 7306289 B2 JP7306289 B2 JP 7306289B2
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Prior art keywords
bonding wire
conductive member
ground plane
capacitor
transistor
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JP2021125671A (en
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歩 本田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to JP2020020547A priority Critical patent/JP7306289B2/en
Priority to US17/167,213 priority patent/US11342279B2/en
Priority to CN202110180505.0A priority patent/CN113257802A/en
Publication of JP2021125671A publication Critical patent/JP2021125671A/en
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    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • Wire Bonding (AREA)
  • Waveguide Connection Structure (AREA)
  • Amplifiers (AREA)

Description

本開示は、半導体装置に関する。 The present disclosure relates to semiconductor devices.

接地導体面上に設けられた誘電体基板と、接地導体面上に設けられた半導体基板と、誘電体基板上の配線パターンと半導体基板上の電極との間を接続するボンディングワイヤと、接地導体面に電気的に接続される金属ブロックとを備える電子回路が知られている。この電子回路では、金属ブロックは、ボンディングワイヤの下方に配置されている（例えば、特許文献１の図７参照）。 A dielectric substrate provided on a ground conductor surface, a semiconductor substrate provided on the ground conductor surface, a bonding wire connecting a wiring pattern on the dielectric substrate and an electrode on the semiconductor substrate, and a ground conductor. Electronic circuits are known which comprise a metal block electrically connected to a surface. In this electronic circuit, the metal block is arranged below the bonding wires (see FIG. 7 of Patent Document 1, for example).

特開２０１２－１５１６９４号公報JP 2012-151694 A

ボンディングワイヤのインダクタンスが増加すると、ボンディングワイヤを通る信号の位相がずれて、信号の伝送に関する所望の特性が得られない場合がある。 As the inductance of the bond wire increases, the signal passing through the bond wire may be out of phase and the desired characteristics of signal transmission may not be achieved.

本開示は、ボンディングワイヤのインダクタンスを低減可能な半導体装置及び増幅器を提供する。 The present disclosure provides a semiconductor device and amplifier capable of reducing bonding wire inductance.

本開示は、
接地面と、
前記接地面の上に設けられ、第１上面を有するキャパシタと、
前記接地面の上に設けられ、第２上面を有する半導体チップと、
前記第１上面と前記第２上面との間を接続するボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材とを備え、
前記接地面に対する平面視にて、前記ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置する、半導体装置を提供する。 This disclosure is
a ground plane;
a capacitor disposed on the ground plane and having a first top surface;
a semiconductor chip provided on the ground plane and having a second upper surface;
a bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
When the direction in which the bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The conductive member provides a semiconductor device in which the conductive member is positioned away from the bonding wire in the second direction in the plan view.

また、本開示は、
接地面と、
前記接地面の上に設けられ、第１上面を有する第１キャパシタと、
前記接地面の上に設けられ、第２上面を有する第１トランジスタと、
前記第１上面と前記第２上面との間を接続する少なくとも一本の第１ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材と、
前記接地面の上に設けられ、第３上面を有する第２キャパシタと、
前記接地面の上に設けられ、第４上面を有する第２トランジスタと、
前記第３上面と前記第４上面との間を接続する複数の第２ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面まで貫通する空間が形成された基板とを備え、
前記第１トランジスタ及び前記第２トランジスタは、前記第１キャパシタ及び前記第２キャパシタを介して互いに並列に接続されており、
前記第１トランジスタは、前記第２トランジスタよりも低出力タイプであり、
前記第１ボンディングワイヤは、前記第２ボンディングワイヤよりも本数が少なく、
前記接地面に対する平面視にて、前記第１ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記第１ボンディングワイヤから前記第２方向に離れて位置する、増幅器を提供する。 This disclosure also provides
a ground plane;
a first capacitor provided on the ground plane and having a first top surface;
a first transistor overlying the ground plane and having a second top surface;
at least one first bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
a second capacitor provided on the ground plane and having a third upper surface;
a second transistor overlying the ground plane and having a fourth top surface;
a plurality of second bonding wires connecting between the third top surface and the fourth top surface;
a substrate provided on the ground plane and having a space penetrating to the ground plane;
the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor;
the first transistor is of a lower output type than the second transistor;
The first bonding wires are less in number than the second bonding wires,
When the direction in which the first bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The conductive member provides an amplifier spaced apart from the first bonding wire in the second direction in the plan view.

本開示によれば、ボンディングワイヤのインダクタンスを低減可能な半導体装置及び増幅器を提供できる。 According to the present disclosure, it is possible to provide a semiconductor device and an amplifier capable of reducing bonding wire inductance.

図１は、第１実施形態における半導体装置の構成例を示す斜視図である。FIG. 1 is a perspective view showing a configuration example of a semiconductor device according to a first embodiment. 図２は、第１実施形態における半導体装置の構成例を示す平面図である。FIG. 2 is a plan view showing a configuration example of the semiconductor device according to the first embodiment. 図３は、第１実施形態における半導体装置の構成例（変形例）を示す平面図である。FIG. 3 is a plan view showing a configuration example (modification) of the semiconductor device according to the first embodiment. 図４は、導電性部材とボンディングワイヤとの位置関係の第１例を示す図である。FIG. 4 is a diagram showing a first example of the positional relationship between the conductive members and the bonding wires. 図５は、導電性部材とボンディングワイヤとの位置関係の第２例を示す図である。FIG. 5 is a diagram showing a second example of the positional relationship between the conductive members and the bonding wires. 図６は、導電性部材とボンディングワイヤとの位置関係の第３例を示す図である。FIG. 6 is a diagram showing a third example of the positional relationship between the conductive members and the bonding wires. 図７は、第２実施形態における半導体装置の構成例を示す俯瞰図である。FIG. 7 is a bird's-eye view showing a configuration example of a semiconductor device according to the second embodiment. 図８は、第２実施形態における半導体装置の構成例を示す断面図である。FIG. 8 is a cross-sectional view showing a configuration example of a semiconductor device according to the second embodiment. 図９は、一実施形態における増幅器の構成例を示す回路ブロック図である。FIG. 9 is a circuit block diagram showing a configuration example of an amplifier in one embodiment. 図１０は、一実施形態における増幅器の一部の構成例を示す回路図である。FIG. 10 is a circuit diagram showing a configuration example of part of the amplifier in one embodiment. 図１１は、シミュレーション結果の一例を示す表である。FIG. 11 is a table showing an example of simulation results. 図１２は、シミュレーション結果の一例を示すグラフである。FIG. 12 is a graph showing an example of simulation results.

［本開示の実施形態の説明］
最初に本開示の実施形態を列記して説明する。 [Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure will be listed and described.

（１）本開示の一実施形態における半導体装置は、
接地面と、
前記接地面の上に設けられ、第１上面を有するキャパシタと、
前記接地面の上に設けられ、第２上面を有する半導体チップと、
前記第１上面と前記第２上面との間を接続するボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材とを備え、
前記接地面に対する平面視にて、前記ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置する、半導体装置である。 (1) A semiconductor device according to an embodiment of the present disclosure is
a ground plane;
a capacitor disposed on the ground plane and having a first top surface;
a semiconductor chip provided on the ground plane and having a second upper surface;
a bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
When the direction in which the bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The conductive member is a semiconductor device positioned apart from the bonding wire in the second direction in plan view.

（１）によれば、前記導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置するので、前記ボンディングワイヤを中心に同心円状に発生する磁力線（磁界）の少なくとも一部は、前記導電性部材によって遮断される。前記ボンディングワイヤから発生する磁界の少なくとも一部が前記導電性部材により遮断されることにより、前記ボンディングワイヤのインダクタンスを低減できる。 According to (1), since the conductive member is positioned away from the bonding wire in the second direction in plan view, the lines of magnetic force (magnetic field) generated concentrically around the bonding wire At least a portion is interrupted by the conductive member. At least part of the magnetic field generated from the bonding wire is blocked by the conductive member, so that the inductance of the bonding wire can be reduced.

また、ボンディングワイヤは上方に突出するように湾曲している。そのため、金属ブロックがボンディングワイヤの下方のみに位置する形態（例えば、特許文献１の図７）では、ボンディングワイヤのインダクタンスの低減効果を高めるには、金属ブロックの上端を上方に突出するように湾曲する形状に変形することが求められる。しかしながら、そのように湾曲させる変形は、製造やコストの点で難しい。これに対し、（１）の形態では、前記導電性部材が前記ボンディングワイヤから前記第２方向に離れて位置するので、前記導電性部材をそのように変形しなくても、前記ワイヤボンディング（特に、上方の突出する頂部）に前記導電性部材を容易に近づけることができる。したがって、（１）の形態は、金属ブロックがボンディングワイヤの下方のみに位置する形態に比べて、ボンディングワイヤのインダクタンスを容易に低減できる。 Also, the bonding wires are curved so as to protrude upward. Therefore, in a configuration in which the metal block is positioned only below the bonding wires (for example, FIG. 7 of Patent Document 1), in order to enhance the effect of reducing the inductance of the bonding wires, the upper end of the metal block should be curved so as to protrude upward. It is required to transform into a shape that However, such curving deformation is difficult in terms of manufacturing and cost. On the other hand, in the mode (1), the conductive member is positioned apart from the bonding wire in the second direction, so that the wire bonding (especially , an upper protruding top) can be easily accessed by the conductive member. Therefore, the configuration (1) can easily reduce the inductance of the bonding wires compared to the configuration in which the metal block is positioned only below the bonding wires.

また、金属ブロックがボンディングワイヤの下方のみに位置する形態（例えば、特許文献１の図７）では、金属ブロックの設置後でなければ、ボンディングワイヤを組み付けることは難しい。これに対し、（１）の形態では、前記導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置するので、前記導電性部材の設置後でも設置前でも、前記ボンディングワイヤを組み付けできる。よって、半導体装置の製造の自由度が向上する。 In addition, in a form in which the metal block is positioned only below the bonding wire (for example, FIG. 7 of Patent Document 1), it is difficult to assemble the bonding wire until after the metal block is installed. On the other hand, in the mode (1), the conductive member is positioned apart from the bonding wire in the second direction in the plan view, so that the conductive member can The bonding wire can be assembled. Therefore, the degree of freedom in manufacturing the semiconductor device is improved.

（２）前記導電性部材から前記ボンディングワイヤの頂部までの最短距離は、前記接地面から前記頂部までの最短距離以下でもよい。 (2) The shortest distance from the conductive member to the top of the bonding wire may be less than or equal to the shortest distance from the ground plane to the top.

（２）によれば、前記導電性部材が前記ボンディングワイヤに近接するので、前記ボンディングワイヤから発生する磁界が、前記導電性部材によって遮断される面積が大きくなる。よって、前記ボンディングワイヤのインダクタンスをより低減できる。 According to (2), since the conductive member is close to the bonding wire, the area where the magnetic field generated from the bonding wire is blocked by the conductive member increases. Therefore, the inductance of the bonding wire can be further reduced.

（３）前記導電性部材の前記接地面からの最大高さは、前記ボンディングワイヤの頂部の前記接地面からの高さ以上でもよい。 (3) The maximum height of the conductive member from the ground plane may be greater than or equal to the height of the top of the bonding wire from the ground plane.

（３）によれば、前記ボンディングワイヤの頂部から斜め上方の磁界部分が前記導電性部材によって遮断されるので、前記ボンディングワイヤから発生する磁界が、前記導電性部材によって遮断される面積が大きくなる。よって、前記ボンディングワイヤのインダクタンスをより低減できる。 According to (3), since the magnetic field obliquely upward from the top of the bonding wire is blocked by the conductive member, the area where the magnetic field generated from the bonding wire is blocked by the conductive member increases. . Therefore, the inductance of the bonding wire can be further reduced.

（４）前記導電性部材は、前記平面視にて、前記キャパシタと前記半導体チップとの間に位置してもよい。 (4) The conductive member may be located between the capacitor and the semiconductor chip in plan view.

（４）によれば、前記導電性部材が前記ボンディングワイヤに近接するので、前記ボンディングワイヤから発生する磁界が、前記導電性部材によって遮断される面積が大きくなる。よって、前記ボンディングワイヤのインダクタンスをより低減できる。 According to (4), since the conductive member is close to the bonding wire, the area where the magnetic field generated from the bonding wire is blocked by the conductive member increases. Therefore, the inductance of the bonding wire can be further reduced.

（５）前記導電性部材は、前記第２方向からの側面視にて、前記ボンディングワイヤの少なくとも一部と重なってもよい。 (5) The conductive member may overlap at least a portion of the bonding wire in a side view from the second direction.

（５）によれば、前記ボンディングワイヤの少なくとも一部を中心に同心円状に発生する磁界が、前記導電性部材によって遮断される面積が大きくなるので、前記ボンディングワイヤのインダクタンスをより低減できる。 According to (5), the magnetic field concentrically generated around at least a part of the bonding wire is blocked by the conductive member in a larger area, so that the inductance of the bonding wire can be further reduced.

（６）前記導電性部材は、前記第２方向からの側面視にて、前記ボンディングワイヤの少なくとも頂部と重なってもよい。 (6) The conductive member may overlap at least the top portion of the bonding wire in a side view from the second direction.

（６）によれば、前記ボンディングワイヤの頂部を中心に同心円状に発生する磁界が、前記導電性部材によって遮断される面積が大きくなるので、前記ボンディングワイヤのインダクタンスをより低減できる。 According to (6), the magnetic field concentrically generated around the top of the bonding wire is blocked by the conductive member in a larger area, so that the inductance of the bonding wire can be further reduced.

（７）前記平面視にて、前記第２方向とは反対向きの方向を第３方向とするとき、
例えば、
前記導電性部材に含まれる第１導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置し、
前記導電性部材に含まれる第２導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第３方向に離れて位置する。 (7) When the direction opposite to the second direction in plan view is the third direction,
for example,
a first conductive member included in the conductive member is positioned apart from the bonding wire in the second direction in the plan view;
A second conductive member included in the conductive member is positioned apart from the bonding wire in the third direction in plan view.

（７）によれば、前記ボンディングワイヤから発生する磁界の前記第２方向の側の磁界部分は、前記第１導電性部材によって遮断され、前記ボンディングワイヤから発生する磁界の前記第３方向の側の磁界部分は、前記第２導電性部材によって遮断される。これにより、前記ボンディングワイヤから発生する磁界が、前記導電性部材によって遮断される面積が大きくなるので、前記ボンディングワイヤのインダクタンスを更に低減できる。 According to (7), the magnetic field portion on the second direction side of the magnetic field generated from the bonding wire is blocked by the first conductive member, and the magnetic field generated from the bonding wire is cut off from the third direction side. is interrupted by said second conductive member. As a result, the area where the magnetic field generated from the bonding wire is blocked by the conductive member is increased, so that the inductance of the bonding wire can be further reduced.

（８）前記接地面の上に設けられ、前記接地面まで貫通する空間が形成された基板を備え、
前記導電性部材、前記ボンディングワイヤ、前記キャパシタ及び前記半導体チップは、前記空間に配置されてもよい。 (8) a substrate provided on the ground plane and having a space penetrating to the ground plane;
The conductive member, the bonding wire, the capacitor and the semiconductor chip may be arranged in the space.

（８）によれば、前記導電性部材、前記ボンディングワイヤ、前記キャパシタ及び前記半導体チップが前記空間に配置されるので、前記接地面の上に設けられる基板が追加されても、半導体装置の前記平面視の方向での厚さの増大を抑制できる。 According to (8), the conductive member, the bonding wire, the capacitor, and the semiconductor chip are arranged in the space. An increase in thickness in the planar view direction can be suppressed.

（９）前記半導体チップは、トランジスタでもよい。 (9) The semiconductor chip may be a transistor.

（９）によれば、前記キャパシタと前記ボンディングワイヤとを使って、前記トランジスタから見たインピーダンスを整合できるので、前記トランジスタを通過する信号の基本波や高調波に対するインピーダンス整合が可能となる。前記ボンディングワイヤのインダクタンスが低減されることにより、２次高調波に対するインピーダンスの分散の増大を抑制できる。これにより、２次高調波に対するインピーダンス整合を広帯域で高精度に実施でき、トランジスタの所望の増幅効率を実現する周波数範囲を広げることができる。 According to (9), since the impedance seen from the transistor can be matched using the capacitor and the bonding wire, it is possible to match the impedance with respect to the fundamental wave and harmonics of the signal passing through the transistor. By reducing the inductance of the bonding wire, it is possible to suppress an increase in the dispersion of the impedance with respect to the second harmonic. As a result, the impedance matching for the second harmonic can be performed over a wide band with high accuracy, and the frequency range in which the desired amplification efficiency of the transistor is achieved can be widened.

（１０）本開示の一実施形態における増幅器は、
接地面と、
前記接地面の上に設けられ、第１上面を有する第１キャパシタと、
前記接地面の上に設けられ、第２上面を有する第１トランジスタと、
前記第１上面と前記第２上面との間を接続する少なくとも一本の第１ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材と、
前記接地面の上に設けられ、第３上面を有する第２キャパシタと、
前記接地面の上に設けられ、第４上面を有する第２トランジスタと、
前記第３上面と前記第４上面との間を接続する複数の第２ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面まで貫通する空間が形成された基板とを備え、
前記導電性部材、前記第１キャパシタ、前記第１トランジスタ、前記第１ボンディングワイヤ、前記第２キャパシタ、前記第２トランジスタ及び前記第２ボンディングワイヤは、前記空間に配置されており、
前記第１トランジスタ及び前記第２トランジスタは、前記第１キャパシタ及び前記第２キャパシタを介して互いに並列に接続されており、
前記第１トランジスタは、前記第２トランジスタよりも低出力タイプであり、
前記第１ボンディングワイヤは、前記第２ボンディングワイヤよりも本数が少なく、
前記接地面に対する平面視にて、前記第１ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記第１ボンディングワイヤから前記第２方向に離れて位置する、増幅器である。 (10) An amplifier in an embodiment of the present disclosure,
a ground plane;
a first capacitor provided on the ground plane and having a first top surface;
a first transistor overlying the ground plane and having a second top surface;
at least one first bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
a second capacitor provided on the ground plane and having a third upper surface;
a second transistor overlying the ground plane and having a fourth top surface;
a plurality of second bonding wires connecting between the third top surface and the fourth top surface;
a substrate provided on the ground plane and having a space penetrating to the ground plane;
the conductive member, the first capacitor, the first transistor, the first bonding wire, the second capacitor, the second transistor and the second bonding wire are arranged in the space;
the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor;
the first transistor is of a lower output type than the second transistor;
The first bonding wires are less in number than the second bonding wires,
When the direction in which the first bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The conductive member is an amplifier positioned apart from the first bonding wire in the second direction in plan view.

（１０）によれば、前記導電性部材は、前記平面視にて、前記第１ボンディングワイヤから前記第２方向に離れて位置するので、前記第１ボンディングワイヤを中心に同心円状に発生する磁力線（磁界）の少なくとも一部は、前記導電性部材によって遮断される。前記第１ボンディングワイヤから発生する磁界の少なくとも一部が前記導電性部材により遮断されることにより、前記第１ボンディングワイヤのインダクタンスを低減できる。 According to (10), since the conductive member is positioned away from the first bonding wire in the second direction in plan view, magnetic lines of force are generated concentrically around the first bonding wire. At least part of the (magnetic field) is blocked by the conductive member. At least part of the magnetic field generated from the first bonding wire is blocked by the conductive member, so that the inductance of the first bonding wire can be reduced.

また、（１０）によれば、前記第１キャパシタと前記第１ボンディングワイヤとを使って、前記第１トランジスタから見たインピーダンスを整合できるので、前記第１トランジスタを通過する信号の基本波や高調波に対するインピーダンス整合が可能となる。前記第２キャパシタと前記第２ボンディングワイヤとを使って、前記第２トランジスタから見たインピーダンスを整合できるので、前記第２トランジスタを通過する信号の基本波や高調波に対するインピーダンス整合が可能となる。 Further, according to (10), since the impedance seen from the first transistor can be matched using the first capacitor and the first bonding wire, the fundamental wave and harmonics of the signal passing through the first transistor can be matched. Impedance matching for waves becomes possible. Since the impedance viewed from the second transistor can be matched using the second capacitor and the second bonding wire, it is possible to match the impedance with respect to the fundamental wave and harmonics of the signal passing through the second transistor.

また、（１０）では、前記第１トランジスタは、前記第２トランジスタよりも低出力タイプであり、前記第１ボンディングワイヤは、前記第２ボンディングワイヤよりも本数が少ない。そのため、前記第１ボンディングワイヤのインダクタンスの変化は、前記第２ボンディングワイヤのインダクタンスの変化に比べて、高調波のインピーダンス整合に対する影響が大きい。しかしながら、（１０）によれば、前記第１ボンディングワイヤのインダクタンスが低減されることにより、前記第１トランジスタを通過する信号の２次高調波に対するインピーダンスの分散の増大を抑制できる。これにより、当該２次高調波に対するインピーダンス整合を広帯域で高精度に実施でき、前記第１トランジスタの所望の増幅効率を実現する周波数範囲を広げることができる。その結果、所望の増幅効率を実現する広帯域の増幅器を実現できる。 Further, in (10), the first transistor is of a lower output type than the second transistor, and the number of the first bonding wires is smaller than that of the second bonding wires. Therefore, the change in the inductance of the first bonding wire has a greater influence on the impedance matching of harmonics than the change in the inductance of the second bonding wire. However, according to (10), by reducing the inductance of the first bonding wire, it is possible to suppress an increase in impedance dispersion with respect to the second harmonic of the signal passing through the first transistor. Thereby, impedance matching for the second harmonic can be performed over a wide band with high accuracy, and the frequency range in which the desired amplification efficiency of the first transistor is realized can be widened. As a result, a broadband amplifier that achieves desired amplification efficiency can be realized.

また、金属ブロックがボンディングワイヤの下方のみに位置する形態（例えば、特許文献１の図７）では、金属ブロックの設置後でなければ、ボンディングワイヤを組み付けることは難しい。これに対し、（１０）の形態では、前記導電性部材は、前記平面視にて、前記第１ボンディングワイヤから前記第２方向に離れて位置するので、前記導電性部材の設置後でも設置前でも、前記第１ボンディングワイヤを組み付けできる。よって、増幅器の製造の自由度が向上する。 In addition, in a form in which the metal block is positioned only below the bonding wire (for example, FIG. 7 of Patent Document 1), it is difficult to assemble the bonding wire until after the metal block is installed. On the other hand, in the mode (10), the conductive member is positioned apart from the first bonding wire in the second direction in the plan view, so that even after the conductive member is installed and before the installation However, the first bonding wire can be assembled. Therefore, the degree of freedom in manufacturing the amplifier is improved.

次に、本開示の実施形態における半導体装置及び増幅器の具体例を、図面を参照しつつ説明する。なお、本発明は、これらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。 Next, specific examples of semiconductor devices and amplifiers according to embodiments of the present disclosure will be described with reference to the drawings. The present invention is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

［本開示の実施形態の詳細］
図１は、第１実施形態における半導体装置の構成例を示す斜視図である。図２は、第１実施形態における半導体装置の構成例を示す平面図である。図１，２を参照して、第１実施形態における半導体装置の構成例について説明する。 [Details of the embodiment of the present disclosure]
FIG. 1 is a perspective view showing a configuration example of a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing a configuration example of the semiconductor device according to the first embodiment. A configuration example of the semiconductor device according to the first embodiment will be described with reference to FIGS.

なお、理解の容易のため、図面における各部材の縮尺は実際とは異なる場合がある。本開示の実施形態では、３軸方向（Ｘ軸方向、Ｙ軸方向、Ｚ軸方向）の３次元直交座標系が用いられる。平行、直角、直交、水平、垂直、上下、左右などの方向には、本開示の実施形態の効果を損なわない程度のずれが許容される。Ｘ軸方向、Ｙ軸方向、Ｚ軸方向は、それぞれ、Ｘ軸に平行な方向、Ｙ軸に平行な方向、Ｚ軸に平行な方向を表す。Ｘ軸方向とＹ軸方向とＺ軸方向は、互いに直交する。ＸＹ平面、ＹＺ平面、ＺＸ平面は、それぞれ、Ｘ軸方向及びＹ軸方向に平行な仮想平面、Ｙ軸方向及びＺ軸方向に平行な仮想平面、Ｚ軸方向及びＸ軸方向に平行な仮想平面を表す。 For ease of understanding, the scale of each member in the drawings may differ from the actual scale. In the embodiment of the present disclosure, a three-dimensional orthogonal coordinate system with three axial directions (X-axis direction, Y-axis direction, Z-axis direction) is used. In directions such as parallel, right angle, orthogonal, horizontal, vertical, up and down, left and right, misalignment is allowed to the extent that the effects of the embodiments of the present disclosure are not compromised. The X-axis direction, Y-axis direction, and Z-axis direction represent directions parallel to the X-axis, directions parallel to the Y-axis, and directions parallel to the Z-axis, respectively. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. The XY plane, YZ plane, and ZX plane are virtual planes parallel to the X-axis direction and Y-axis direction, virtual planes parallel to the Y-axis direction and Z-axis direction, and virtual planes parallel to the Z-axis direction and X-axis direction, respectively. represents

図１，２に示す半導体装置１０１は、接地面１０、キャパシタ２０、半導体チップ３０、ボンディングワイヤ４０、第１導電性部材５０及び第２導電性部材６０を備える。 A semiconductor device 101 shown in FIGS. 1 and 2 includes a ground plane 10 , a capacitor 20 , a semiconductor chip 30 , bonding wires 40 , first conductive members 50 and second conductive members 60 .

接地面１０は、接地用の導体面である。接地面１０は、例えば、銅等の導体板又は導体膜の表面である。 The ground plane 10 is a conductor plane for grounding. The ground plane 10 is, for example, the surface of a conductive plate or film made of copper or the like.

キャパシタ２０は、接地面１０の上に設けられる素子であり、第１上面２１を有する。キャパシタ２０は、例えば、接地面１０に接する裏面電極を有するダイキャパシタである。キャパシタ２０の裏面電極が接地面１０に接することで、キャパシタ２０の裏面電極は接地面１０に接地されるとともに、キャパシタ２０の熱は接地面１０に放熱される。キャパシタ２０は、第１上面２１に形成された第１電極２２を有する。キャパシタ２０は、第１電極２２と裏面電極との間に容量部を有する。 Capacitor 20 is an element provided on ground plane 10 and has a first upper surface 21 . Capacitor 20 is, for example, a die capacitor having a backside electrode in contact with ground plane 10 . Since the back electrode of the capacitor 20 is in contact with the ground plane 10 , the back electrode of the capacitor 20 is grounded to the ground plane 10 and the heat of the capacitor 20 is radiated to the ground plane 10 . Capacitor 20 has a first electrode 22 formed on first top surface 21 . The capacitor 20 has a capacitive part between the first electrode 22 and the back electrode.

半導体チップ３０は、接地面１０の上に設けられる素子であり、第２上面３１を有する。半導体チップ３０は、接地面１０に接する裏面電極を有する。半導体チップ３０の裏面電極が接地面１０に接することで、半導体チップ３０の裏面電極は接地面１０に接地されるとともに、半導体チップ３０の熱は接地面１０に放熱される。半導体チップ３０は、第２上面３１に形成された第２電極３２を有する。 The semiconductor chip 30 is an element provided on the ground plane 10 and has a second upper surface 31 . The semiconductor chip 30 has a back electrode in contact with the ground plane 10 . Since the back electrode of the semiconductor chip 30 is in contact with the ground plane 10 , the back electrode of the semiconductor chip 30 is grounded to the ground plane 10 and the heat of the semiconductor chip 30 is radiated to the ground plane 10 . The semiconductor chip 30 has a second electrode 32 formed on the second upper surface 31 .

半導体チップ３０は、例えば、ＧａＮ（窒化ガリウム）デバイス等のトランジスタである。ＧａＮデバイスは、他の半導体デバイス（例えば、Ｓｉ－ＬＤＭＯＳ（シリコン横方向拡散金属酸化膜半導体）やＧａＡｓ－ＦＥＴ（ガリウム砒素電界効果トランジスタ）等）と比較し、バンドギャップが広くて移動度も高いため、優れた高周波出力特性を有する。半導体チップ３０は、トランジスタ以外の半導体素子（例えば、ダイオード）でもよい。 The semiconductor chip 30 is, for example, a transistor such as a GaN (gallium nitride) device. GaN devices have a wider band gap and higher mobility than other semiconductor devices (e.g., Si-LDMOS (silicon laterally diffused metal oxide semiconductor), GaAs-FET (gallium arsenide field effect transistor), etc.). Therefore, it has excellent high frequency output characteristics. The semiconductor chip 30 may be a semiconductor element (for example, a diode) other than a transistor.

ボンディングワイヤ４０は、第１上面２１と第２上面３１との間を接続する導体であり、第１上面２１上の第１電極２２に電気的に接続される第１ワイヤ端４１と、第２上面３１上の第２電極３２に電気的に接続される第２ワイヤ端４２とを有する。ボンディングワイヤ４０は、接地面１０から最も離れた頂部４３を有し、頂部４３を頂点に湾曲している。 The bonding wire 40 is a conductor connecting between the first upper surface 21 and the second upper surface 31, and has a first wire end 41 electrically connected to the first electrode 22 on the first upper surface 21 and a second and a second wire end 42 electrically connected to the second electrode 32 on the top surface 31 . The bonding wire 40 has a top portion 43 farthest from the ground plane 10 and is curved with the top portion 43 being the vertex.

第１導電性部材５０及び第２導電性部材６０は、接地面１０の上に設けられ、接地面１０に電気的に接続される。第１導電性部材５０及び第２導電性部材６０の図１に示す外形は、直方体であるが、他の形状でもよい。第１導電性部材５０及び第２導電性部材６０は、それぞれ、ボンディングワイヤ４０に対向する表面を有し、図１に示す形態では、ＺＸ平面に平行な表面を有する。 The first conductive member 50 and the second conductive member 60 are provided on the ground plane 10 and electrically connected to the ground plane 10 . Although the outer shape of the first conductive member 50 and the second conductive member 60 shown in FIG. 1 is a rectangular parallelepiped, other shapes may be used. Each of the first conductive member 50 and the second conductive member 60 has a surface facing the bonding wire 40, and in the form shown in FIG. 1, has a surface parallel to the ZX plane.

第１導電性部材５０及び第２導電性部材６０は、その表面の少なくとも一部が金メッキ等の導体で覆われていれば、その内部が導体でなくてもよい。第１導電性部材５０及び第２導電性部材６０は、例えば、銀ペースト等の導電性の接着部材によって接地面１０に固定される。 The inside of the first conductive member 50 and the second conductive member 60 does not have to be a conductor as long as at least a part of the surface thereof is covered with a conductor such as gold plating. The first conductive member 50 and the second conductive member 60 are fixed to the ground plane 10 by, for example, a conductive adhesive member such as silver paste.

図２は、接地面１０に対する平面視で半導体装置１０１を示している。接地面１０に対する平面視にて、ボンディングワイヤ４０が延伸する方向を第１方向とし、第１方向に直交する方向を第２方向とし、第２方向とは反対向きの方向を第３方向とする。例えば図２において、正のＸ軸方向は、第１方向の一例であり、負のＹ軸方向は、第２方向の一例であり、正のＹ軸方向は、第３方向の一例である。図２において、接地面１０に対する平面視は、接地面１０の法線方向（Ｚ軸方向）からの視点を示す。 FIG. 2 shows the semiconductor device 101 in plan view with respect to the ground plane 10 . In a plan view of the ground plane 10, the direction in which the bonding wire 40 extends is defined as a first direction, the direction orthogonal to the first direction is defined as a second direction, and the direction opposite to the second direction is defined as a third direction. . For example, in FIG. 2, the positive X-axis direction is an example of a first direction, the negative Y-axis direction is an example of a second direction, and the positive Y-axis direction is an example of a third direction. In FIG. 2 , a plan view of the ground plane 10 shows a viewpoint from the normal direction (Z-axis direction) of the ground plane 10 .

第１導電性部材５０は、接地面１０に対する平面視にて、ボンディングワイヤ４０から負のＹ軸方向に離れて位置し、第２導電性部材６０は、接地面１０に対する平面視にて、ボンディングワイヤ４０から正のＹ軸方向に離れて位置する。したがって、ボンディングワイヤ４０から発生する磁界の負のＹ軸方向の側の磁界部分は、第１導電性部材５０によって遮断され、ボンディングワイヤ４０から発生する磁界の正のＹ軸方向の側の磁界部分は、第２導電性部材６０によって遮断される。これにより、ボンディングワイヤ４０から発生する磁界が、ボンディングワイヤ４０の両側に位置する第１導電性部材５０及び第２導電性部材６０によって遮断される。よって、ボンディングワイヤ４０のインダクタンスを低減する度合いは、ボンディングワイヤ４０の片側のみに導電性部材が配置されている形態（例えば、第２導電性部材６０が無い形態）に比べて高い。 The first conductive member 50 is positioned away from the bonding wire 40 in the negative Y-axis direction in plan view with respect to the ground plane 10 , and the second conductive member 60 is positioned at a bonding wire in plan view with respect to the ground plane 10 . It is located away from wire 40 in the positive Y-axis direction. Therefore, the magnetic field portion on the negative Y-axis direction side of the magnetic field generated by the bonding wire 40 is blocked by the first conductive member 50, and the magnetic field portion on the positive Y-axis direction side of the magnetic field generated by the bonding wire 40 is blocked by the first conductive member 50. is interrupted by the second conductive member 60 . Thereby, the magnetic field generated from the bonding wire 40 is blocked by the first conductive member 50 and the second conductive member 60 positioned on both sides of the bonding wire 40 . Therefore, the degree of reduction in the inductance of the bonding wire 40 is higher than in a mode in which the conductive member is arranged only on one side of the bonding wire 40 (for example, a mode in which the second conductive member 60 is not provided).

第１導電性部材５０と第２導電性部材６０とのうち、一方の導電性部材は、無くてもよい。この形態でも、残りの導電性部材によって、ボンディングワイヤ４０のインダクタンスを低減できる。 One of the first conductive member 50 and the second conductive member 60 may be omitted. Also in this form, the inductance of the bonding wire 40 can be reduced by the remaining conductive member.

ボンディングワイヤ４０の負のＹ軸方向の側の側面から負のＹ軸方向に離れて位置する第１導電性部材５０の個数は、一つに限られず、複数でもよい。ボンディングワイヤ４０の正のＹ軸方向の側の側面から正のＹ軸方向に離れて位置する第２導電性部材６０の個数は、一つに限られず、複数でもよい。 The number of first conductive members 50 positioned away from the negative Y-axis direction side surface of the bonding wire 40 in the negative Y-axis direction is not limited to one, and may be plural. The number of second conductive members 60 positioned apart in the positive Y-axis direction from the side surface of the bonding wire 40 on the positive Y-axis direction side is not limited to one, and may be plural.

第１導電性部材５０と第２導電性部材６０とのうち少なくとも一方の導電性部材は、例えば、接地面１０に対する平面視にて、キャパシタ２０と半導体チップ３０との間に位置する。これにより、当該少なくとも一方の導電性部材がボンディングワイヤ４０に近接するので、ボンディングワイヤ４０から発生する磁界が、当該少なくとも一方の導電性部材によって遮断される面積が大きくなる。よって、ボンディングワイヤ４０のインダクタンスをより低減できる。図２に示す形態では、第１導電性部材５０と第２導電性部材６０との両方が、接地面１０に対する平面視にて、キャパシタ２０と半導体チップ３０との間に位置する。 At least one of the first conductive member 50 and the second conductive member 60 is positioned between the capacitor 20 and the semiconductor chip 30 in plan view with respect to the ground plane 10, for example. As a result, since the at least one conductive member is close to the bonding wire 40, the area where the magnetic field generated from the bonding wire 40 is blocked by the at least one conductive member increases. Therefore, the inductance of the bonding wire 40 can be further reduced. In the form shown in FIG. 2 , both the first conductive member 50 and the second conductive member 60 are positioned between the capacitor 20 and the semiconductor chip 30 in plan view with respect to the ground plane 10 .

図３は、第１実施形態における半導体装置の構成例（変形例）を示す平面図である。図３に示すように、第１導電性部材５０と第２導電性部材６０との両方が、接地面１０に対する平面視にて、キャパシタ２０と半導体チップ３０との間に位置しなくてもよい。図３に示す形態でも、ボンディングワイヤ４０から発生する磁界の負のＹ軸方向の側の磁界部分は、第１導電性部材５０によって遮断され、ボンディングワイヤ４０から発生する磁界の正のＹ軸方向の側の磁界部分は、第２導電性部材６０によって遮断される。したがって、図３に示す形態でも、ボンディングワイヤ４０のインダクタンスを低減できる。 FIG. 3 is a plan view showing a configuration example (modification) of the semiconductor device according to the first embodiment. As shown in FIG. 3, both the first conductive member 50 and the second conductive member 60 need not be positioned between the capacitor 20 and the semiconductor chip 30 in plan view with respect to the ground plane 10. . 3, the magnetic field portion of the magnetic field generated by the bonding wire 40 on the negative Y-axis direction side is blocked by the first conductive member 50, and the magnetic field generated by the bonding wire 40 is blocked in the positive Y-axis direction. The magnetic field portion on the side of is interrupted by the second conductive member 60 . Therefore, the inductance of the bonding wire 40 can be reduced also in the form shown in FIG.

図１，２において、例えば、第１導電性部材５０からボンディングワイヤ４０の頂部４３までの最短距離ｄ１は、接地面１０から頂部４３までの最短距離Ｈ（例えば、接地面１０から頂部４３の下面までの高さｈ０）以下である。これにより、第１導電性部材５０がボンディングワイヤ４０に近接するので、ボンディングワイヤ４０から発生する磁界が、第１導電性部材５０によって遮断される面積が大きくなる。よって、ボンディングワイヤ４０のインダクタンスをより低減できる。同様に、第２導電性部材６０からボンディングワイヤ４０の頂部４３までの最短距離ｄ２は、接地面１０から頂部４３までの最短距離Ｈ（例えば、接地面１０から頂部４３の下面までの高さｈ０）以下でもよい。これにより、ボンディングワイヤ４０のインダクタンスをより低減できる。 1 and 2, for example, the shortest distance d1 from the first conductive member 50 to the top portion 43 of the bonding wire 40 is the shortest distance H from the ground plane 10 to the top portion 43 (for example, from the ground plane 10 to the bottom surface of the top portion 43). height h0) or less. As a result, since the first conductive member 50 is close to the bonding wire 40, the area where the magnetic field generated from the bonding wire 40 is blocked by the first conductive member 50 increases. Therefore, the inductance of the bonding wire 40 can be further reduced. Similarly, the shortest distance d2 from the second conductive member 60 to the top portion 43 of the bonding wire 40 is the shortest distance H from the ground plane 10 to the top portion 43 (for example, the height h0 from the ground plane 10 to the bottom surface of the top portion 43). ) or less. Thereby, the inductance of the bonding wire 40 can be further reduced.

図４は、導電性部材とボンディングワイヤとの位置関係の第１例を示す図である。第１導電性部材５０の接地面１０からの最大高さｈ５は、図４に示すように、ボンディングワイヤ４０の頂部４３の接地面１０からの高さ（例えば、接地面１０から頂部４３の下面までの高さｈ０）未満でもよい。図４に示す形態でも、頂部４３を中心に同心円状に発生する磁界を第１導電性部材５０によって遮断できるので、ボンディングワイヤ４０のインダクタンスを低減できる。 FIG. 4 is a diagram showing a first example of the positional relationship between the conductive members and the bonding wires. The maximum height h5 of the first conductive member 50 from the ground plane 10 is, as shown in FIG. may be less than the height h0). In the form shown in FIG. 4 as well, the magnetic field generated concentrically around the top portion 43 can be cut off by the first conductive member 50, so that the inductance of the bonding wire 40 can be reduced.

第２導電性部材６０の接地面１０からの最大高さｈ６は、図４に示すように、ボンディングワイヤ４０の頂部４３の接地面１０からの高さ（例えば、接地面１０から頂部４３の下面までの高さｈ０）未満でもよい。第１導電性部材５０と同様に、ボンディングワイヤ４０のインダクタンスを低減できる。 The maximum height h6 of the second conductive member 60 from the ground plane 10 is, as shown in FIG. may be less than the height h0). As with the first conductive member 50, the inductance of the bonding wire 40 can be reduced.

図５は、導電性部材とボンディングワイヤとの位置関係の第２例を示す図である。第１導電性部材５０の接地面１０からの最大高さｈ５は、図５に示すように、高さｈ０以上高さｈ３未満でもよい。高さｈ０は、接地面１０から頂部４３の下面までの高さを表し、高さｈ３は、接地面１０から頂部４３の上面までの高さを表す。図５に示す形態でも、頂部４３を中心に同心円状に発生する磁界を第１導電性部材５０によって遮断できるので、ボンディングワイヤ４０のインダクタンスを低減できる。同様に、第２導電性部材６０の接地面１０からの最大高さｈ６を高さｈ０以上高さｈ３未満にしても、ボンディングワイヤ４０のインダクタンスを低減できる。 FIG. 5 is a diagram showing a second example of the positional relationship between the conductive members and the bonding wires. A maximum height h5 of the first conductive member 50 from the ground plane 10 may be equal to or more than the height h0 and less than the height h3, as shown in FIG. A height h0 represents the height from the ground plane 10 to the bottom surface of the top portion 43, and a height h3 represents the height from the ground plane 10 to the top surface of the top portion 43. FIG. 5, the magnetic field generated concentrically around the top portion 43 can be cut off by the first conductive member 50, so that the inductance of the bonding wire 40 can be reduced. Similarly, the inductance of the bonding wire 40 can be reduced by making the maximum height h6 of the second conductive member 60 from the ground plane 10 equal to or more than the height h0 and less than the height h3.

図６は、導電性部材とボンディングワイヤとの位置関係の第３例を示す図である。第１導電性部材５０の接地面１０からの最大高さｈ５は、図６に示すように、高さｈ３以上でもよい。図６に示す形態でも、頂部４３を中心に同心円状に発生する磁界を第１導電性部材５０によって遮断できるので、ボンディングワイヤ４０のインダクタンスを低減できる。同様に、第２導電性部材６０の接地面１０からの最大高さｈ６を高さｈ３以上にしても、ボンディングワイヤ４０のインダクタンスを低減できる。 FIG. 6 is a diagram showing a third example of the positional relationship between the conductive members and the bonding wires. The maximum height h5 of the first conductive member 50 from the ground plane 10 may be equal to or greater than the height h3, as shown in FIG. In the form shown in FIG. 6 as well, the magnetic field generated concentrically around the top portion 43 can be cut off by the first conductive member 50, so that the inductance of the bonding wire 40 can be reduced. Similarly, the inductance of the bonding wire 40 can be reduced by making the maximum height h6 of the second conductive member 60 from the ground plane 10 equal to or greater than the height h3.

図７は、第２実施形態における半導体装置の構成例を示す不感図である。図８は、第２実施形態における半導体装置の構成例を示す平面図である。図７，８を参照して、第２実施形態における半導体装置の構成例について説明する。なお、上述の実施形態と同様の構成についての説明は、上述の説明を援用することで、省略又は簡略する。 FIG. 7 is a dead diagram showing a configuration example of a semiconductor device according to the second embodiment. FIG. 8 is a plan view showing a configuration example of a semiconductor device according to the second embodiment. A configuration example of the semiconductor device according to the second embodiment will be described with reference to FIGS. It should be noted that the description of the configuration similar to that of the above-described embodiment will be omitted or simplified by citing the above-described description.

図７，８に示す半導体装置１０２は、導体板１１、キャパシタ１２０、第１トランジスタ１３０、ボンディングワイヤ４０、第１導電性部材５０、第２導電性部材６０及び基板１２を備える。第１トランジスタ１３０は、半導体チップの一例である。 A semiconductor device 102 shown in FIGS. 7 and 8 includes a conductor plate 11 , a capacitor 120 , a first transistor 130 , a bonding wire 40 , a first conductive member 50 , a second conductive member 60 and a substrate 12 . The first transistor 130 is an example of a semiconductor chip.

導体板１１の上面は、接地面１０である。導体板１１は、例えば、銅板である。 The upper surface of the conductor plate 11 is the ground plane 10 . The conductor plate 11 is, for example, a copper plate.

基板１２は、接地面１０の上に設けられる、例えば誘電体基板である。基板１２は、基板上面１３と基板下面１４とを有する。基板下面１４は、接地面１０に接する。基板１２には、接地面１０まで貫通する空間１５が形成されている。空間１５は、例えば、基板上面１３から基板下面１４まで貫通する孔であり、キャビティとも称される。空間１５は、完全な孔に限られず、その側面が開口している形態でもよい。接地面１０は、空間１５を介して露出している。 The substrate 12 is provided on the ground plane 10 and is, for example, a dielectric substrate. Substrate 12 has a substrate top surface 13 and a substrate bottom surface 14 . The substrate bottom surface 14 contacts the ground plane 10 . A space 15 penetrating to the ground plane 10 is formed in the substrate 12 . The space 15 is, for example, a hole penetrating from the substrate top surface 13 to the substrate bottom surface 14, and is also called a cavity. The space 15 is not limited to a complete hole, and may be open on the side. The ground plane 10 is exposed through the space 15 .

第１導電性部材５０、第２導電性部材６０、ボンディングワイヤ４０、キャパシタ１２０及び第１トランジスタ１３０は、空間１５に配置される。第１導電性部材５０等が空間１５に配置されるので、接地面１０の上に設けられる基板１２が存在していても、半導体装置１０２の平面視の方向での厚さの増大を抑制できる。 A first conductive member 50 , a second conductive member 60 , a bonding wire 40 , a capacitor 120 and a first transistor 130 are arranged in the space 15 . Since the first conductive member 50 and the like are arranged in the space 15, even if the substrate 12 provided on the ground plane 10 exists, it is possible to suppress an increase in the thickness of the semiconductor device 102 in the plan view direction. .

キャパシタ１２０は、第１電極２２及び第３電極２３が第１上面２１に形成されている。キャパシタ１２０は、第１電極２２と裏面電極との間に形成される第１容量部と、第３電極２３と裏面電極との間に形成される第２容量部とを有する。 The capacitor 120 has a first electrode 22 and a third electrode 23 formed on the first upper surface 21 . Capacitor 120 has a first capacitance section formed between first electrode 22 and a back electrode, and a second capacitance section formed between third electrode 23 and the back electrode.

ボンディングワイヤ１４０は、第１電極２２と第３電極２３との間を接続する導体であり、第３電極２３に電気的に接続されるワイヤ端１４１と、第１電極２２に電気的に接続されるワイヤ端１４２とを有する。 The bonding wire 140 is a conductor that connects between the first electrode 22 and the third electrode 23 , and has a wire end 141 that is electrically connected to the third electrode 23 and an end that is electrically connected to the first electrode 22 . and a wire end 142 that

ボンディングワイヤ７０は、基板上面１３と第１上面２１との間を接続する導体であり、基板上面１３上の電極９１に電気的に接続されるワイヤ端７１と、第１上面２１上の第３電極２３に電気的に接続されるワイヤ端７２とを有する。電極９１は、入力端子１１１に直接又不図示の部品を介して入力端子１１１に電気的に接続される。 The bonding wire 70 is a conductor connecting between the substrate top surface 13 and the first top surface 21 , and has a wire end 71 electrically connected to the electrode 91 on the substrate top surface 13 and a third bonding wire on the first top surface 21 . and a wire end 72 electrically connected to the electrode 23 . The electrode 91 is electrically connected to the input terminal 111 directly or via a component (not shown).

第１トランジスタ１３０は、第２電極３２及び第４電極３３が第２上面３１に形成されている。例えば、第２電極３２は、ゲート電極であり、第４電極３３は、ドレイン電極である。 The first transistor 130 has a second electrode 32 and a fourth electrode 33 formed on the second upper surface 31 . For example, the second electrode 32 is a gate electrode and the fourth electrode 33 is a drain electrode.

ボンディングワイヤ８０は、第２上面３１と基板上面１３との間を接続する導体であり、第２上面３１上の第４電極３３に電気的に接続されるワイヤ端８１と、基板上面１３上の電極９２に電気的に接続されるワイヤ端８２とを有する。電極９２は、メイン出力端子１１２に電気的に接続される。 The bonding wire 80 is a conductor connecting between the second top surface 31 and the substrate top surface 13 , and has a wire end 81 electrically connected to the fourth electrode 33 on the second top surface 31 and a wire end 81 on the substrate top surface 13 . and a wire end 82 electrically connected to the electrode 92 . Electrode 92 is electrically connected to main output terminal 112 .

図８において、第１導電性部材５０及び第２導電性部材６０は、Ｙ軸方向からの側面視にて、ボンディングワイヤ４０の少なくとも一部と重なる。これにより、ボンディングワイヤ４０の少なくとも一部を中心に同心円状に発生する磁界が、第１導電性部材５０及び第２導電性部材６０によって遮断される面積が大きくなるので、ボンディングワイヤ４０のインダクタンスをより低減できる。 In FIG. 8, the first conductive member 50 and the second conductive member 60 overlap at least a portion of the bonding wire 40 when viewed from the side in the Y-axis direction. As a result, the magnetic field generated concentrically around at least a part of the bonding wire 40 is blocked by the first conductive member 50 and the second conductive member 60, so that the inductance of the bonding wire 40 is reduced. can be further reduced.

図８では、第１導電性部材５０及び第２導電性部材６０は、Ｙ軸方向からの側面視にて、ボンディングワイヤ４０の少なくとも頂部４３と重なる。これにより、頂部４３を中心に同心円状に発生する磁界が、第１導電性部材５０及び第２導電性部材６０によって遮断される面積が大きくなるので、ボンディングワイヤ４０のインダクタンスをより低減できる。 In FIG. 8, the first conductive member 50 and the second conductive member 60 overlap at least the top portion 43 of the bonding wire 40 when viewed from the side in the Y-axis direction. As a result, the area in which the magnetic field generated concentrically around the top portion 43 is blocked by the first conductive member 50 and the second conductive member 60 is increased, so that the inductance of the bonding wire 40 can be further reduced.

図９は、一実施形態における増幅器の構成例を示す回路ブロック図である。上述の実施形態と同様の構成については、上述の説明を援用することで、省略又は簡略する。図９に示す増幅器１０３は、第１トランジスタ１３０及び第２トランジスタ２３０が第１キャパシタ１２０及び第２キャパシタ２２０を介して互いに並列に接続されるドハティ型の増幅器である。 FIG. 9 is a circuit block diagram showing a configuration example of an amplifier in one embodiment. Configurations similar to those of the above embodiments are omitted or simplified by citing the above description. The amplifier 103 shown in FIG. 9 is a Doherty amplifier in which a first transistor 130 and a second transistor 230 are connected in parallel via a first capacitor 120 and a second capacitor 220 .

増幅器１０３は、入力端子１１１、整合回路９３、駆動アンプ９０、整合回路９４及び分配器９９を有する入力回路を備える。増幅器１０３は、整合回路９７、第１ボンディングワイヤ４０、第１トランジスタ１３０、ボンディングワイヤ８０、整合回路９５及びメイン出力端子１１２を有するキャリア増幅回路を有する。増幅器１０３は、整合回路２９７、第２ボンディングワイヤ２４０、第２トランジスタ２３０、ボンディングワイヤ２８０、整合回路９６及びピーク出力端子１１３を有するピーク増幅回路を有する。増幅器１０３は、第１導電性部材５０及び第２導電性部材６０を更に備える。 Amplifier 103 comprises an input circuit having input terminal 111 , matching circuit 93 , driver amplifier 90 , matching circuit 94 and divider 99 . Amplifier 103 has a carrier amplifier circuit with matching circuit 97 , first bonding wire 40 , first transistor 130 , bonding wire 80 , matching circuit 95 and main output terminal 112 . Amplifier 103 includes a peak amplifier circuit having matching circuit 297 , second bonding wire 240 , second transistor 230 , bonding wire 280 , matching circuit 96 and peak output terminal 113 . Amplifier 103 further comprises a first conductive member 50 and a second conductive member 60 .

整合回路９７は、フィルタ部１７０、ボンディングワイヤ７０及び第１キャパシタ１２０を有する。整合回路２９７は、フィルタ部２７０、ワイヤボンディング２７３及び第２キャパシタ２２０を有する。整合回路９７と整合回路２９７は、互いに同じ回路構成を有する。 The matching circuit 97 has a filter section 170 , bonding wires 70 and a first capacitor 120 . Matching circuit 297 has filter section 270 , wire bonding 273 and second capacitor 220 . The matching circuit 97 and the matching circuit 297 have the same circuit configuration.

図１０に示すように、フィルタ部１７０は、インダクタ１７１とキャパシタ１７２とを有し、フィルタ部２７０は、インダクタ２７１とキャパシタ２７２とを有する。第１キャパシタ１２０は、第１容量部１２１及び第２容量部１２２を有する。第１容量部１２１及び第２容量部１２２の各々の一端は、ボンディングワイヤ１４０を介して互いに接続される。第２キャパシタ２２０は、第３容量部２２１及び第４容量部２２２を有する。第３容量部２２１及び第４容量部２２２の各々の一端は、ボンディングワイヤ２４１を介して互いに接続される。 As shown in FIG. 10 , filter section 170 has inductor 171 and capacitor 172 , and filter section 270 has inductor 271 and capacitor 272 . The first capacitor 120 has a first capacitive section 121 and a second capacitive section 122 . One end of each of the first capacitive section 121 and the second capacitive section 122 is connected to each other via a bonding wire 140 . The second capacitor 220 has a third capacitive section 221 and a fourth capacitive section 222 . One end of each of the third capacitive section 221 and the fourth capacitive section 222 is connected to each other via a bonding wire 241 .

第１導電性部材５０、第２導電性部材６０、第１キャパシタ１２０、第１トランジスタ１３０、第１ボンディングワイヤ４０、第２キャパシタ２２０、第２トランジスタ２３０及び第２ボンディングワイヤ２４０は、空間１５（図７参照）に配置されている。空間１５に配置される以外の上述の部品は、基板１２に実装される。 The first conductive member 50, the second conductive member 60, the first capacitor 120, the first transistor 130, the first bonding wire 40, the second capacitor 220, the second transistor 230 and the second bonding wire 240 form the space 15 ( (see FIG. 7). The components described above other than those placed in the space 15 are mounted on the board 12 .

図９において、第１トランジスタ１３０は、第２トランジスタ２３０よりも低出力タイプであり、第１ボンディングワイヤ４０は、第２ボンディングワイヤ２４０よりも本数が少ない。第１ボンディングワイヤ４０の本数は、少なくとも１本（例えば、１本）であり、第２ボンディングワイヤ２４０の本数は、複数（例えば、２本）である。そのため、第１ボンディングワイヤ４０のインダクタンスの変化は、第２ボンディングワイヤ２４０のインダクタンスの変化に比べて、高調波のインピーダンス整合に対する影響が大きい。しかしながら、増幅器１０３によれば、第１ボンディングワイヤ４０のインダクタンスが低減されることにより、第１トランジスタ１３０を通過する信号の２次高調波に対するインピーダンスの分散の増大を抑制できる。これにより、当該２次高調波に対するインピーダンス整合を広帯域で高精度に実施でき、第１トランジスタ１３０の所望の増幅効率を実現する周波数範囲を広げることができる。その結果、所望の増幅効率を実現する広帯域の増幅器１０３を実現できる。 In FIG. 9 , the first transistor 130 is of a lower output type than the second transistor 230 , and the number of the first bonding wires 40 is less than that of the second bonding wires 240 . The number of first bonding wires 40 is at least one (eg, one), and the number of second bonding wires 240 is plural (eg, two). Therefore, the change in inductance of the first bonding wire 40 has a greater effect on impedance matching of harmonics than the change in inductance of the second bonding wire 240 . However, according to the amplifier 103 , by reducing the inductance of the first bonding wire 40 , it is possible to suppress an increase in impedance dispersion with respect to the second harmonic of the signal passing through the first transistor 130 . Thereby, impedance matching for the second harmonic can be performed in a wide band with high accuracy, and the frequency range in which the desired amplification efficiency of the first transistor 130 is achieved can be widened. As a result, a wideband amplifier 103 that achieves desired amplification efficiency can be realized.

ボンディングワイヤから発生する磁界を遮断する面積を大きくするほど、ボンディングワイヤのインダクタンスを低減する効果が高くなるため、ワイヤの本数が少ない、特に１本のワイヤの場合に、最も効果がある。 The effect of reducing the inductance of the bonding wire increases as the area for blocking the magnetic field generated from the bonding wire increases.

図１１は、シミュレーション結果の一例を示す表である。図１２は、図１１に示すシミュレーション結果の一例を示すグラフである。図１１，１２は、図１に示す構成において、高さｈ０を０．２７ｍｍに固定した状態で最短距離ｄ１，ｄ２の両方を変化させた場合の、ボンディングワイヤ４０のインダクタンス（Ｌ値）とその低減量を示す。図１１において、ｈ０＝０．２７ｍｍでｄ１，ｄ２＝∞の欄は、図１に示す構成から第１導電性部材５０及び第２導電性部材６０を削除した形態（比較形態）のデータを表す。Ｌ値低減量は、比較形態のＬ値からの低減量を表す。最短距離ｄ１，ｄ２を高さｈ０よりも短くすることによって、Ｌ値低減量が増加している。 FIG. 11 is a table showing an example of simulation results. 12 is a graph showing an example of the simulation results shown in FIG. 11. FIG. 11 and 12 show the inductance (L value) of the bonding wire 40 and its value when both the shortest distances d1 and d2 are changed while the height h0 is fixed at 0.27 mm in the configuration shown in FIG. Indicates the amount of reduction. In FIG. 11 , the column of h0=0.27 mm and d1, d2=∞ represents the data of the configuration (comparative configuration) in which the first conductive member 50 and the second conductive member 60 are removed from the configuration shown in FIG. . The amount of L value reduction represents the amount of reduction from the L value of the comparative embodiment. By making the shortest distances d1 and d2 shorter than the height h0, the L value reduction amount is increased.

以上、実施形態を説明したが、特許請求の範囲の趣旨及び範囲から逸脱することなく、形態や詳細の多様な変更が可能なことが理解されるであろう。他の実施形態の一部又は全部との組み合わせや置換などの種々の変形及び改良が可能である。 Although the embodiments have been described above, it will be appreciated that various changes in form and detail may be made without departing from the spirit and scope of the claims. Various modifications and improvements such as combination or replacement with part or all of other embodiments are possible.

１０ 接地面
１１ 導体板
１２ 基板
１３ 基板上面
１４ 基板下面
１５ 空間
２０ キャパシタ
２１ 第１上面
２２ 第１電極
２３ 第３電極
３０ 半導体チップ
３１ 第２上面
３２ 第２電極
３３ 第４電極
４０ 第１ボンディングワイヤ
４０ ボンディングワイヤ
４１ 第１ワイヤ端
４２ 第２ワイヤ端
４３ 頂部
５０ 第１導電性部材
６０ 第２導電性部材
７０ ボンディングワイヤ
７１ ワイヤ端
７２ ワイヤ端
８０ ボンディングワイヤ
８１ ワイヤ端
８２ ワイヤ端
９０ 駆動アンプ
９１ 電極
９２ 電極
９３ 整合回路
９４ 整合回路
９５ 整合回路
９６ 整合回路
９７ 整合回路
９９ 分配器
１０１ 半導体装置
１０２ 半導体装置
１０３ 増幅器
１１１ 入力端子
１１２ メイン出力端子
１１３ ピーク出力端子
１２０ 第１キャパシタ
１２０ キャパシタ
１２１ 第１容量部
１２２ 第２容量部
１３０ 第１トランジスタ
１４０ ボンディングワイヤ
１４１ ワイヤ端
１４２ ワイヤ端
１７０ フィルタ部
１７１ インダクタ
１７２ キャパシタ
２２０ 第２キャパシタ
２２１ 第３容量部
２２２ 第４容量部
２３０ 第２トランジスタ
２４０ 第２ボンディングワイヤ
２４１ ボンディングワイヤ
２７０ フィルタ部
２７１ インダクタ
２７２ キャパシタ
２７３ ワイヤボンディング
２８０ ボンディングワイヤ
２９７ 整合回路 10 ground plane 11 conductor plate 12 substrate 13 substrate top surface 14 substrate bottom surface 15 space 20 capacitor 21 first top surface 22 first electrode 23 third electrode 30 semiconductor chip 31 second top surface 32 second electrode 33 fourth electrode 40 first bonding wire 40 bonding wire 41 first wire end 42 second wire end 43 top 50 first conductive member 60 second conductive member 70 bonding wire 71 wire end 72 wire end 80 bonding wire 81 wire end 82 wire end 90 drive amplifier 91 electrode 92 electrode 93 matching circuit 94 matching circuit 95 matching circuit 96 matching circuit 97 matching circuit 99 distributor 101 semiconductor device 102 semiconductor device 103 amplifier 111 input terminal 112 main output terminal 113 peak output terminal 120 first capacitor 120 capacitor 121 first capacitor 122 second capacitive section 130 first transistor 140 bonding wire 141 wire end 142 wire end 170 filter section 171 inductor 172 capacitor 220 second capacitor 221 third capacitive section 222 fourth capacitive section 230 second transistor 240 second bonding wire 241 bonding wire 270 filter section 271 inductor 272 capacitor 273 wire bonding 280 bonding wire 297 matching circuit

Claims (10)

接地面と、
前記接地面の上に設けられ、第１上面を有するキャパシタと、
前記接地面の上に設けられ、第２上面を有する半導体チップと、
前記第１上面と前記第２上面との間を接続するボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材とを備え、
前記接地面に対する平面視にて、前記ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置する、半導体装置。 a ground plane;
a capacitor disposed on the ground plane and having a first top surface;
a semiconductor chip provided on the ground plane and having a second upper surface;
a bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
When the direction in which the bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The semiconductor device, wherein the conductive member is positioned apart from the bonding wire in the second direction in plan view. 前記導電性部材から前記ボンディングワイヤの頂部までの最短距離は、前記接地面から前記頂部までの最短距離以下である、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the shortest distance from said conductive member to the top of said bonding wire is equal to or less than the shortest distance from said ground plane to said top. 前記導電性部材の前記接地面からの最大高さは、前記ボンディングワイヤの頂部の前記接地面からの高さ以上である、請求項１又は請求項２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the maximum height of said conductive member from said ground plane is equal to or greater than the height of the top of said bonding wire from said ground plane. 前記導電性部材は、前記平面視にて、前記キャパシタと前記半導体チップとの間に位置する、請求項１から請求項３のいずれか一項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein said conductive member is positioned between said capacitor and said semiconductor chip in said plan view. 前記導電性部材は、前記第２方向からの側面視にて、前記ボンディングワイヤの少なくとも一部と重なる、請求項１から請求項４のいずれか一項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein said conductive member overlaps with at least part of said bonding wire in a side view from said second direction. 前記導電性部材は、前記第２方向からの側面視にて、前記ボンディングワイヤの少なくとも頂部と重なる、請求項５に記載の半導体装置。 6. The semiconductor device according to claim 5, wherein said conductive member overlaps at least a top portion of said bonding wire in a side view from said second direction. 前記平面視にて、前記第２方向とは反対向きの方向を第３方向とするとき、
前記導電性部材に含まれる第１導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第２方向に離れて位置し、
前記導電性部材に含まれる第２導電性部材は、前記平面視にて、前記ボンディングワイヤから前記第３方向に離れて位置する、請求項１から請求項６のいずれか一項に記載の半導体装置。 When the direction opposite to the second direction in the plan view is the third direction,
a first conductive member included in the conductive member is positioned apart from the bonding wire in the second direction in the plan view;
7. The semiconductor according to claim 1, wherein a second conductive member included in said conductive member is positioned away from said bonding wire in said third direction in said plan view. Device. 前記接地面の上に設けられ、前記接地面まで貫通する空間が形成された基板を備え、
前記導電性部材、前記ボンディングワイヤ、前記キャパシタ及び前記半導体チップは、前記空間に配置される、請求項１から請求項７のいずれか一項に記載の半導体装置。 A substrate provided on the ground plane and having a space penetrating to the ground plane,
8. The semiconductor device according to claim 1, wherein said conductive member, said bonding wire, said capacitor and said semiconductor chip are arranged in said space. 前記半導体チップは、トランジスタである、請求項１から請求項８のいずれか一項に記載の半導体装置。 9. The semiconductor device according to claim 1, wherein said semiconductor chip is a transistor. 接地面と、
前記接地面の上に設けられ、第１上面を有する第１キャパシタと、
前記接地面の上に設けられ、第２上面を有する第１トランジスタと、
前記第１上面と前記第２上面との間を接続する少なくとも一本の第１ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面に電気的に接続される少なくとも一つの導電性部材と、
前記接地面の上に設けられ、第３上面を有する第２キャパシタと、
前記接地面の上に設けられ、第４上面を有する第２トランジスタと、
前記第３上面と前記第４上面との間を接続する複数の第２ボンディングワイヤと、
前記接地面の上に設けられ、前記接地面まで貫通する空間が形成された基板とを備え、
前記導電性部材、前記第１キャパシタ、前記第１トランジスタ、前記第１ボンディングワイヤ、前記第２キャパシタ、前記第２トランジスタ及び前記第２ボンディングワイヤは、前記空間に配置されており、
前記第１トランジスタ及び前記第２トランジスタは、前記第１キャパシタ及び前記第２キャパシタを介して互いに並列に接続されており、
前記第１トランジスタは、前記第２トランジスタよりも低出力タイプであり、
前記第１ボンディングワイヤは、前記第２ボンディングワイヤよりも本数が少なく、
前記接地面に対する平面視にて、前記第１ボンディングワイヤが延伸する方向を第１方向とし、前記第１方向に直交する方向を第２方向とするとき、
前記導電性部材は、前記平面視にて、前記第１ボンディングワイヤから前記第２方向に離れて位置する、増幅器。 a ground plane;
a first capacitor provided on the ground plane and having a first top surface;
a first transistor overlying the ground plane and having a second top surface;
at least one first bonding wire connecting between the first top surface and the second top surface;
at least one conductive member provided on the ground plane and electrically connected to the ground plane;
a second capacitor provided on the ground plane and having a third upper surface;
a second transistor overlying the ground plane and having a fourth top surface;
a plurality of second bonding wires connecting between the third top surface and the fourth top surface;
a substrate provided on the ground plane and having a space penetrating to the ground plane;
the conductive member, the first capacitor, the first transistor, the first bonding wire, the second capacitor, the second transistor and the second bonding wire are arranged in the space;
the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor;
the first transistor is of a lower output type than the second transistor;
The first bonding wires are less in number than the second bonding wires,
When the direction in which the first bonding wire extends is defined as a first direction and the direction orthogonal to the first direction is defined as a second direction in plan view with respect to the ground plane,
The amplifier, wherein the conductive member is positioned apart from the first bonding wire in the second direction in plan view.
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