JP2021069068A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of high-efficiency operation in a wide band.SOLUTION: A semiconductor device according to the present invention comprises: a transistor chip including a plurality of first pads that input or output a signal, and a first harmonic wave pad provided between the first pads and electrically connected to the first pads; a first fundamental wave matching circuit that matches the signal to the fundamental wave; a plurality of first bonding wires extending in a first direction and connecting the first pads and the first fundamental wave matching circuit; a first harmonic wave matching circuit that suppresses the harmonic wave included in the signal; and a first harmonic wave bonding wire extending in a second direction not parallel to the first direction and connecting the first harmonic wave pad and the first harmonic wave matching circuit.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device.

Patent Document 1 discloses a high-frequency semiconductor amplifier. This high frequency semiconductor amplifier has a semiconductor amplification element, an input circuit, and an output circuit. The output circuit includes a first transmission line, a second transmission line, a short stub including the transmission line, and a bonding wire. The first transmission line is provided between the second transmission line and the output terminal. The short stub is connected to the output electrode of the semiconductor amplification element. The first transmission line has a first characteristic impedance and a first electrical length that is 90 degrees at the center frequency. The second transmission line has a second characteristic impedance that is lower than the first characteristic impedance and a second electrical length that is 90 degrees at the center frequency. The short stub has an electrical length of 180 degrees with respect to a double wave of the center frequency. The output circuit matches the capacitive output impedance of the semiconductor amplification element with the external load.

Japanese Unexamined Patent Publication No. 2015-149626

In Patent Document 1, the bonding wire connecting the semiconductor amplification element and the second transmission line and the bonding wire connecting the semiconductor amplification element and the short stub are parallel to each other. In the case of this configuration, interference due to mutual inductance may occur between the wires stretched in parallel. Therefore, the frequency dependence of the impedance of the double wave when the load side is viewed from the drain end may increase. Therefore, it may not be possible to operate with high efficiency in a wide band.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device capable of high-efficiency operation over a wide band.

The semiconductor device according to the present invention is for a first harmonic that is provided between a plurality of first pads that input or output a signal and the plurality of first pads and is electrically connected to the plurality of first pads. A transistor chip having a pad, a first fundamental wave matching circuit that matches the signal to the fundamental wave, and a plurality of first pads extending in the first direction and the first fundamental wave matching circuit are connected to each other. A plurality of first bonding wires, a first harmonic matching circuit that suppresses harmonics contained in the signal, a pad for the first harmonic extending in a second direction non-parallel to the first direction, and the pad. The first harmonic bonding wire for connecting to the first harmonic matching circuit is provided.

In the semiconductor device according to the present invention, the first bonding wire and the first harmonic bonding wire are non-parallel. Therefore, interference due to mutual inductance between wires can be suppressed, and high-efficiency operation in a wide band becomes possible.

It is an equivalent circuit diagram of the semiconductor device which concerns on Embodiment 1. FIG. It is a figure explaining the structure of the output side of the transistor chip which concerns on Embodiment 1. FIG. It is a figure explaining the structure of the output side of the transistor chip which concerns on a comparative example. It is an equivalent circuit diagram of the semiconductor device which concerns on Embodiment 2. FIG. It is a figure explaining the structure of the input side of the transistor chip which concerns on Embodiment 2. FIG. It is an equivalent circuit diagram of the semiconductor device which concerns on Embodiment 3. FIG. It is a figure explaining the structure of the input side and the output side of the transistor chip which concerns on Embodiment 3. FIG.

The semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is an equivalent circuit diagram of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a package. The package has two amplifiers 20, 50 inside. The semiconductor device 100 is a high-frequency semiconductor device such as a Doherty amplifier. The package may include one or more amplifiers. Further, the semiconductor device 100 is not limited to the Doherty amplifier.

The amplifier 20 includes an input fundamental wave matching circuit 21, a transistor chip 30, an output fundamental wave matching circuit 22, and an output harmonic matching circuit 40. A plurality of transistors 31 are formed on the transistor chip 30. The transistor 31 is, for example, a FET (Field Effect Transistor). In FIG. 1, only one transistor 31 is shown for convenience. The transistor chip 30 is one of the carrier amplifier and the peak amplifier among the Doherty amplifiers.

The transistor chip 30 has a drain pad 33. The drain pad 33 and the input end of the output fundamental wave matching circuit 22 are connected by a plurality of bonding wires 81. In FIG. 1, for convenience, only one bonding wire 81 is shown. Further, the transistor chip 30 has a first harmonic pad 35. The first harmonic pad 35 and the input end of the output harmonic matching circuit 40 are connected by a harmonic bonding wire 82. The output end of the output harmonic matching circuit 40 is electrically connected to the grounding pattern. Further, the transistor chip 30 has a gate pad 32. The gate pad 32 and the output end of the input fundamental wave matching circuit 21 are connected by a plurality of bonding wires 83. In FIG. 1, for convenience, only one bonding wire 83 is shown.

The amplifier 50 includes an input fundamental wave matching circuit 51, a transistor chip 60, an output fundamental wave matching circuit 52, and an output harmonic matching circuit 70. A plurality of transistors 61 are formed on the transistor chip 60. The transistor 61 is, for example, a FET. In FIG. 1, only one transistor 61 is shown for convenience. The transistor chip 60 is the other of the carrier amplifier and the peak amplifier among the Doherty amplifiers.

The transistor chip 60 has a drain pad 63. The drain pad 63 and the input end of the output fundamental wave matching circuit 52 are connected by a plurality of bonding wires 91. In FIG. 1, for convenience, only one bonding wire 91 is shown. Further, the transistor chip 60 has a first harmonic pad 65. The first harmonic pad 65 and the input end of the output harmonic matching circuit 70 are connected by a harmonic bonding wire 92. The output end of the output harmonic matching circuit 40 is electrically connected to the grounding pattern. Further, the transistor chip 60 has a gate pad 62. The gate pad 62 and the output end of the input fundamental wave matching circuit 51 are connected by a plurality of bonding wires 93. In FIG. 1, for convenience, only one bonding wire 93 is shown.

Each of the transistor chips 30 and 60 includes a substrate. The substrate is, for example, a SiC (Silicon Carbide) substrate. A semiconductor layer is provided on the upper surface side of the substrate. The semiconductor layer uses, for example, GaN (Gallium Nitride) as a main material. The semiconductor layer is formed by epitaxial growth. For example, HEMT (High Electron Mobility Transistor) is formed on the substrate. As a result, the semiconductor device 100 having excellent high frequency characteristics can be obtained. Each of the transistor chips 30 and 60 is obtained by slicing such a semiconductor substrate.

Each of the transistor chips 30 and 60 has a gate electrode, a source electrode and a drain electrode. In the transistor chip 30, the gate electrode and the drain electrode are electrically connected to the gate pad 32 and the drain pad 33, respectively. In the transistor chip 60, the gate electrode and the drain electrode are electrically connected to the gate pad 62 and the drain pad 63, respectively.

In each of the transistor chips 30 and 60, metallizing is formed on the back surface of the substrate. The source electrode is electrically connected to the metallizing applied to the back surface of the substrate by a through hole penetrating the substrate. The source electrode is electrically connected to the grounding pattern via metallizing.

Each of the transistor chips 30 and 60 is fixed to the package by a bonding material. The joining material is solder, a conductive adhesive, or the like. Each of the transistor chips 30 and 60 is electrically connected to the package via a bonding material.

The package has a multilayer board. The multilayer board is, for example, a glass epoxy board. A high frequency pattern is formed on the surface layer of the glass epoxy substrate. The multilayer board has a grounding electrode or an electrode for secondary mounting in the lowermost layer. The high frequency pattern provided on the surface layer of the multilayer board includes a pad for wire bonding. Further, on the surface layer of the multilayer board, a land for mounting an SMD (Surface Mount Device) component is provided. The SMD component constitutes, for example, a matching circuit. In the amplifier 20, the matching circuit includes an input fundamental wave matching circuit 21, an output fundamental wave matching circuit 22, and an output harmonic matching circuit 40. In the amplifier 50, the matching circuit includes an input fundamental wave matching circuit 51, an output fundamental wave matching circuit 52, and an output harmonic matching circuit 70.

The surface layer of the multilayer board or a plurality of layers extending from the surface layer are partially removed. As a result, a recess is formed on the surface layer side of the multilayer substrate. A transistor chip 30 or a transistor chip 60 is mounted in the recess. A grounding pattern is formed at the bottom of the depression. The grounding pattern may be formed of solid material. The grounding pattern is grounded by a through hole penetrating the multilayer board.

The material of the package is not limited to the glass epoxy material. The package may be formed, for example, from an electrically low loss material. Further, the multilayer substrate may have an intermediate layer between the surface layer and the bottom layer.

Each of the input fundamental wave matching circuits 21, 51, the output fundamental wave matching circuits 22, 52, and the output harmonic matching circuits 40, 70 may be formed by using only the surface layer of the multilayer board. Further, each of the input fundamental wave matching circuits 21, 51, the output fundamental wave matching circuits 22, 52, and the output harmonic matching circuits 40, 70 may be formed by using the surface layer and the intermediate layer of the multilayer board.

The input end of the input fundamental wave matching circuit 21 and the input end of the input fundamental wave matching circuit 51 are connected to the input terminal 10 via the input power distribution circuit 11. Further, the output end of the output fundamental wave matching circuit 22 and the output end of the output fundamental wave matching circuit 52 are connected to the output terminal 13 via the output power synthesis circuit 12.

A transmission line having an electric length of 1/4 wavelength with respect to the fundamental wave is provided between the drain pad 33 and the output power synthesis circuit 12 and between the drain pad 63 and the output power synthesis circuit 12. Further, on one of the gate pad 32 and the input power distribution circuit 11 and between the gate pad 62 and the input power distribution circuit 11, the difference in electrical length on the output side is canceled with respect to the fundamental wave. A transmission line having an electrical length of 1/4 wavelength is provided.

FIG. 2 is a diagram illustrating a configuration on the output side of the transistor chips 30 and 60 according to the first embodiment. The transistor chip 30 has a substrate 34. Gate pads 32a and 32b, drain pads 33a and 33b, and first harmonic pad 35 are provided on the upper surface of the substrate 34.

The gate pad 32a and the drain pad 33a are electrically connected to the gate electrode and the drain electrode of one of the plurality of transistors 31 formed on the transistor chip 30, respectively. The gate pad 32b and the drain pad 33b are electrically connected to the gate electrode and the drain electrode of the other transistor 31 among the plurality of transistors 31 formed on the transistor chip 30.

The plurality of bonding wires 81 include a bonding wire 81a and a bonding wire 81b. The plurality of bonding wires 81a and 81b connect the plurality of drain pads 33a and 33b and the output fundamental wave matching circuit 22, respectively. The plurality of bonding wires 81a and 81b extend in the first direction, respectively. Here, the first direction is the direction in which the output fundamental wave matching circuit 22 is provided with respect to the transistor chip 30. Further, the first direction may be a direction from the gate to the drain or a waveguide direction of the fundamental wave.

In the transistor chip 30, two transistors 31 are connected in parallel. The number of transistors 31 formed on the transistor chip 30 may be three or more.

A first harmonic pad 35 is provided between the plurality of drain pads 33a and 33b. The first harmonic pad 35 is provided at the center of the transistor chip 30 in the direction in which the plurality of drain pads 33a and 33b are arranged. The first harmonic pad 35 is electrically connected to the plurality of drain pads 33a and 33b. The first harmonic pad 35 may be in contact with the drain pads 33a and 33b.

The harmonic bonding wire 82 connects the first harmonic pad 35 and the output harmonic matching circuit 40. The harmonic bonding wire 82 extends in the second direction. The second direction is the direction in which the output harmonic matching circuit 40 is provided with respect to the transistor chip 30. In this embodiment, the first direction and the second direction are orthogonal to each other.

The transistor chip 60 has a substrate 64. Gate pads 62a and 62b, drain pads 63a and 63b, and first harmonic pad 65 are provided on the upper surface of the substrate 64. The gate pad 62a and the drain pad 63a are electrically connected to the gate electrode and the drain electrode of one of the plurality of transistors 61 formed on the transistor chip 60, respectively. The gate pad 62b and the drain pad 63b are electrically connected to the gate electrode and the drain electrode of the other transistor 61 among the plurality of transistors 61 formed on the transistor chip 60, respectively.

The plurality of bonding wires 91 include a bonding wire 91a and a bonding wire 91b. The plurality of bonding wires 91a and 91b connect the plurality of drain pads 63a and 63b and the output fundamental wave matching circuit 52, respectively. The plurality of bonding wires 91a and 91b extend in the first direction, respectively.

In the transistor chip 60, two transistors 61 are connected in parallel. The number of transistors 61 formed on the transistor chip 60 may be three or more.

A first harmonic pad 65 is provided between the plurality of drain pads 63a and 63b. The first harmonic pad 65 is provided at the center of the transistor chip 60 in the direction in which the plurality of drain pads 63a and 63b are arranged. The first harmonic pad 65 is electrically connected to the plurality of drain pads 63a and 63b. The first harmonic pad 65 may be in contact with the drain pads 63a and 63b. The harmonic bonding wire 92 connects the first harmonic pad 65 and the output harmonic matching circuit 70. The harmonic bonding wire 92 extends in the third direction. The third direction is the direction in which the output harmonic matching circuit 70 is provided with respect to the transistor chip 60. In this embodiment, the first direction and the third direction are orthogonal to each other.

Next, the operation of the semiconductor device 100 will be described. An input signal is input to the input terminal 10 from a circuit provided on the input side. The input signal is distributed by the input power distribution circuit 11 and input to the input fundamental wave matching circuits 21 and 51. The input fundamental wave matching circuits 21 and 51 match the input signal with the fundamental wave, respectively. Each of the input fundamental wave matching circuits 21 and 51 matches the impedance between the circuit connected to the input side of the input terminal 10 and the transistor chips 30 and 60 at the frequency of the fundamental wave.

The signal output from the input fundamental wave matching circuit 21 is input to the transistor chip 30 from the gate pads 32a and 32b. Each of the gate pads 32a and 32b is a pad for inputting a signal. The transistor chip 30 amplifies the signal at each transistor 31. The amplified signal is output from the plurality of drain pads 33a and 33b as an output signal. Each of the drain pads 33a and 33b is a pad that outputs a signal. The output signals from the drain pads 33a and 33b are input to the output fundamental wave matching circuit 22.

Similarly, the signal output from the input fundamental wave matching circuit 51 is input to the transistor chip 60 from the gate pads 62a and 62b. The transistor chip 60 amplifies the signal at each transistor 61. The amplified signal is output from the plurality of drain pads 63a and 63b as an output signal. The output signals from the drain pads 63a and 63b are input to the output fundamental wave matching circuit 52.

The output fundamental wave matching circuits 22 and 52 match the output signal with the fundamental wave. Each of the output fundamental wave matching circuits 22 and 52 matches the impedance between the circuit connected to the output side of the output terminal 13 and the transistor chips 30 and 60 at the frequency of the fundamental wave. The output signals from the output fundamental wave matching circuits 22 and 52 are combined by the output power synthesis circuit 12 and output from the output terminal 13. For example, a load is connected to the output terminal 13.

The output harmonic matching circuit 40 suppresses harmonics included in the output signals from the drain pads 33a and 33b. The output harmonic matching circuit 40 short-circuits the impedance of the second harmonic when viewed from the drain on the load side, for example. The output harmonic matching circuit 40 may include, for example, an LC trap circuit composed of the inductance L of the harmonic bonding wire 82 and the capacitance C of the SMD capacitor. This enables highly efficient operation.

Similarly, the output harmonic matching circuit 70 suppresses harmonics included in the output signals from the drain pads 63a and 63b. The output harmonic matching circuit 70 short-circuits the impedance of the second harmonic when viewed from the drain on the load side, for example. The output harmonic matching circuits 40 and 70 can prevent the harmonics from propagating to the output side.

With the increase in communication capacity, there is a tendency that the realization of a compact and low power consumption power amplifier (PA, Power Amplifier) having characteristics of wide band and low distortion is required. Such power amplifiers are used, for example, for mobile base stations. As the power amplifier, a Doherty amplifier capable of satisfying the above requirements may be used. Moreover, in the age of 5G, it is considered necessary to increase the capacity by 100 times or more as compared with the conventional one. At this time, it may be necessary to arrange a large number of miniaturized amplifiers to operate as an array antenna.

In this embodiment, the transistor chips 30 and 60 are formed of GaN. Therefore, the transistor chips 30 and 60 can be miniaturized as compared with the case where they are formed of a compound semiconductor such as Si or GaAs, and can be operated at a high voltage or a large current.

Further, in the present embodiment, the transistor chips 30 and 60 are mounted on a multilayer glass epoxy substrate and wire-bonded. A large number of chip components such as inductors and capacitors for matching are mounted on the glass epoxy board by soldering. Further, the glass epoxy substrate may be plastic-molded. When molding a package, the semiconductor device 100 is designed in consideration of changes in characteristics due to the molding. Such a configuration is often applied to a small output power amplifier such as a mobile terminal having an output of about several watts in general. According to this configuration, the semiconductor device 100 can be miniaturized.

In addition, harmonic processing may be performed for high efficiency operation of the amplifier. The harmonic processing is, for example, a processing for short-circuiting or opening the impedance of the second harmonic when the load side is viewed from the drain end.

Generally, in a transistor chip composed of a plurality of cells, a plurality of wires may be stretched in parallel with each other in order to avoid deterioration of characteristics due to variation of each finger or to limit the layout. In this case, interference may occur due to mutual inductance between the fundamental wave wire and the double wave wire. At this time, the frequency dependence of the impedance of the double wave when the load side is viewed from the drain end may increase. Therefore, high efficiency operation may not be realized in a wide band.

On the other hand, in the present embodiment, the bonding wires 81a and 81b and the harmonic bonding wires 82 extend in a direction in which they intersect in a plan view. Similarly, the bonding wires 91a and 91b and the harmonic bonding wire 92 extend in a direction in which they intersect in a plan view. Therefore, interference due to mutual inductance between the bonding wires 81a and 81b and the harmonic bonding wire 82 and between the bonding wires 91a and 91b and the harmonic bonding wire 92 can be suppressed.

Therefore, in the present embodiment, a harmonic processing circuit that suppresses electromagnetic coupling between the fundamental wave and the harmonic can be realized. As a result, the frequency dependence of the impedance of the harmonics can be suppressed, and high-efficiency operation can be performed over a wide band. In addition, since interference between wires is suppressed, design can be facilitated. This embodiment is particularly effective in a Doherty amplifier for high efficiency operation over a wide band.

In the present embodiment, the first direction and the second direction and the first direction and the third direction are orthogonal to each other. As a result, the effect of suppressing interference due to mutual inductance can be effectively obtained. Not limited to this, the direction in which the bonding wires 81a and 81b extend and the direction in which the harmonic bonding wire 82 extends may be non-parallel. Further, the direction in which the bonding wires 91a and 91b extend and the direction in which the harmonic bonding wire 92 extends may be non-parallel.

FIG. 3 is a diagram illustrating a configuration on the output side of the transistor chips 130 and 160 according to the comparative example. The semiconductor device 101 according to the comparative example includes transistor chips 130 and 160. The transistor chip 130 is different from the transistor chip 30 in that it has drain pads 133a and 133b and does not have a first harmonic pad 35. The transistor chip 160 is different from the transistor chip 60 in that it has drain pads 163a and 163b and does not have a first harmonic pad 65.

In the transistor chip 130, the drain pad 133a is connected to the output fundamental wave matching circuit 22 by the bonding wire 81a. Further, the drain pad 133a is connected to the output harmonic matching circuit 140a by the bonding wire 182a. The drain pad 133b is connected to the output fundamental wave matching circuit 22 by a bonding wire 81b. Further, the drain pad 133b is connected to the output harmonic matching circuit 140b by a bonding wire 182b.

Similarly, in the transistor chip 160, the drain pad 163a is connected to the output fundamental wave matching circuit 52 by the bonding wire 91a. Further, the drain pad 163a is connected to the output harmonic matching circuit 170a by the bonding wire 192a. The drain pad 163b is connected to the output fundamental wave matching circuit 52 by a bonding wire 91b. Further, the drain pad 163b is connected to the output harmonic matching circuit 170b by a bonding wire 192b. The output harmonic matching circuits 140a, 140b, 170a, 170b are circuits that suppress harmonics included in the output signal.

In the semiconductor device 101 according to the comparative example, a bonding wire for fundamental waves and a bonding wire for harmonics are connected to one drain pad. Therefore, the interference between the fundamental wave bonding wire and the harmonic bonding wire may increase. Further, an output harmonic matching circuit is provided for each drain pad. As a result, the semiconductor device 101 may become large in size. Further, when three or more drain pads are provided on one transistor chip, the wires may intersect with each other. In this case, wire bonding may be difficult.

On the other hand, in the present embodiment, the first harmonic pad 35 is provided separately from the drain pads 33a and 33b. Further, the first harmonic pad 65 is provided separately from the drain pads 63a and 63b. As a result, interference between the bonding wire for the fundamental wave and the bonding wire for the harmonics can be further suppressed.

Further, in the present embodiment, the first harmonic pads 35 and 65 are formed long in the gate-drain direction. The first harmonic pad 35 projects from the plurality of drain pads 33a and 33b to the side opposite to the side from which the plurality of bonding wires 81a and 81b are drawn out. Similarly, the first harmonic pad 65 projects from the plurality of drain pads 63a and 63b to the side opposite to the side from which the plurality of bonding wires 91a and 91b are drawn out.

The harmonic bonding wire 82 is connected to a portion of the first harmonic pad 35 that protrudes from the plurality of drain pads 33a and 33b. Further, the harmonic bonding wire 92 is connected to a portion of the first harmonic pad 65 that protrudes from the plurality of drain pads 63a and 63b. According to such a configuration, the distance between the bonding wire for the fundamental wave and the bonding wire for the harmonics can be secured. Therefore, interference can be further suppressed.

Further, according to such a configuration, it is possible to prevent the bonding wires 81a and 81b from intersecting with the harmonic bonding wires 82. Similarly, it is possible to prevent the bonding wires 91a and 91b from intersecting with the harmonic bonding wires 92. Therefore, wire bonding can be easily performed.

Further, in the present embodiment, only one first harmonic pad 35, 65 is provided on each of the transistor chips 30 and 60, respectively. Therefore, the semiconductor device 100 can be miniaturized.

Further, the first harmonic pads 35 and 65 are arranged at the center of the transistor chips 30 and 60, respectively. As a result, even when only one first harmonic pad is provided for the plurality of drain pads in each of the transistor chips 30 and 60, the distance between the first harmonic pad and the drain electrode of each FET is provided. The difference can be reduced. Therefore, the difference in impedance of the double wave seen from each FET can be reduced. Therefore, it is possible to reduce the variation in the load impedance of the fundamental wave and the double wave of the plurality of cells and to operate the plurality of cells uniformly. Thereby, the output power, gain and efficiency of the semiconductor device 100 can be improved.

In each of the transistor chips 30 and 60, when three or more drain pads are provided on one transistor chip, the first harmonic pad is provided between two adjacent drain pads among the plurality of drain pads. Also in this case, by providing the first harmonic pad between the drain pads, the difference in impedance of the second harmonic seen from each transistor can be reduced.

Further, the transistor chip 30 of the present embodiment has a pair of first sides and a pair of second sides provided on both sides of the first side. One of the first sides faces the output fundamental wave matching circuit 22. One of the second sides faces the output harmonic matching circuit 40. The other side of the second side faces the transistor chip 60. The plurality of drain pads 33a and 33b are arranged along one of the first sides. According to such a configuration, the bonding wires 81a and 81b and the harmonic bonding wires 82 can be easily wired in a non-parallel manner.

As a modification of the present embodiment, the output harmonic matching circuits 40 and 70 are not limited to double waves and may be circuits that suppress harmonics. Further, in the present embodiment, one output fundamental wave matching circuit and one input fundamental wave matching circuit are provided on one transistor chip. Not limited to this, a plurality of output fundamental wave matching circuits or a plurality of input fundamental wave matching circuits may be provided on one transistor chip.

These modifications can be appropriately applied to the semiconductor device according to the following embodiment. Since the semiconductor devices according to the following embodiments have much in common with the first embodiment, the differences from the first embodiment will be mainly described.

Embodiment 2.
FIG. 4 is an equivalent circuit diagram of the semiconductor device 200 according to the second embodiment. The semiconductor device 200 includes a package. The package has two amplifiers 220, 250 inside.

The amplifier 220 includes an input fundamental wave matching circuit 21, a transistor chip 230, an output fundamental wave matching circuit 22, and an input harmonic matching circuit 241. A plurality of transistors 231 are formed on the transistor chip 230. The amplifier 220 is different from the first embodiment in that the amplifier 220 has an input harmonic matching circuit 241 instead of the output harmonic matching circuit 40 as a matching circuit.

The transistor chip 230 has a drain pad 233. The drain pad 233 and the input end of the output fundamental wave matching circuit 22 are connected by a plurality of bonding wires 81. Further, the transistor chip 230 has a gate pad 232. The gate pad 232 and the output end of the input fundamental wave matching circuit 21 are connected by a plurality of bonding wires 83. Further, the transistor chip 230 has a second harmonic pad 236. The second harmonic pad 236 and the input end of the input harmonic matching circuit 241 are connected by a harmonic bonding wire 284. The output end of the input harmonic matching circuit 241 is electrically connected to the grounding pattern.

The amplifier 250 includes an input fundamental wave matching circuit 51, a transistor chip 260, an output fundamental wave matching circuit 52, and an input harmonic matching circuit 271. A plurality of transistors 261 are formed on the transistor chip 260. The amplifier 250 is different from the first embodiment in that the amplifier 250 has an input harmonic matching circuit 271 instead of the output harmonic matching circuit 70 as a matching circuit.

The transistor chip 260 has a drain pad 263. The drain pad 263 and the input end of the output fundamental wave matching circuit 52 are connected by a plurality of bonding wires 91. Further, the transistor chip 260 has a gate pad 262. The gate pad 262 and the output end of the input fundamental wave matching circuit 51 are connected by a plurality of bonding wires 93. Further, the transistor chip 260 has a second harmonic pad 266. The second harmonic pad 266 and the input end of the input harmonic matching circuit 271 are connected by a harmonic bonding wire 294. The output end of the input harmonic matching circuit 271 is electrically connected to the grounding pattern.

FIG. 5 is a diagram illustrating a configuration on the input side of the transistor chips 230 and 260 according to the second embodiment. The transistor chip 230 has a substrate 234. Gate pads 232a, 232b, drain pads 233a, 233b, and second harmonic pad 236 are provided on the upper surface of the substrate 234.

The plurality of bonding wires 83 include a bonding wire 83a and a bonding wire 83b. The plurality of bonding wires 83a and 83b connect the plurality of gate pads 232a and 232b and the input fundamental wave matching circuit 21, respectively. The plurality of bonding wires 83a and 83b extend in the fourth direction, respectively. Here, the fourth direction is the direction in which the input fundamental wave matching circuit 21 is provided for the transistor chip 230. Further, the fourth direction may be a direction from the drain to the gate.

A second harmonic pad 236 is provided between the plurality of gate pads 232a and 232b. The second harmonic pad 236 is provided at the center of the transistor chip 230 in the direction in which the plurality of gate pads 232a and 232b are arranged. The second harmonic pad 236 is electrically connected to the plurality of gate pads 232a and 232b. The second harmonic pad 236 may be in contact with the gate pads 232a and 232b.

The harmonic bonding wire 284 connects the second harmonic pad 236 and the input harmonic matching circuit 241. The harmonic bonding wire 284 extends in the second direction. The second direction is the direction in which the input harmonic matching circuit 241 is provided with respect to the transistor chip 230. In this embodiment, the second direction and the fourth direction are orthogonal to each other.

The transistor chip 260 has a substrate 264. Gate pads 262a and 262b, drain pads 263a and 263b, and second harmonic pad 266 are provided on the upper surface of the substrate 264.

The plurality of bonding wires 93 include a bonding wire 93a and a bonding wire 93b. The plurality of bonding wires 93a and 93b connect the plurality of gate pads 262a and 262b and the input fundamental wave matching circuit 51, respectively. The plurality of bonding wires 93a and 93b extend in the fourth direction, respectively. Here, the fourth direction is the direction in which the input fundamental wave matching circuit 51 is provided for the transistor chip 260.

A second harmonic pad 266 is provided between the plurality of gate pads 262a and 262b. The second harmonic pad 266 is provided at the center of the transistor chip 260 in the direction in which the plurality of gate pads 262a and 262b are arranged. The second harmonic pad 266 is electrically connected to a plurality of gate pads 262a and 262b. The second harmonic pad 266 may be in contact with the gate pads 262a and 262b.

The harmonic bonding wire 294 connects the second harmonic pad 266 and the input harmonic matching circuit 271. The harmonic bonding wire 294 extends in the third direction. The third direction is the direction in which the input harmonic matching circuit 271 is provided with respect to the transistor chip 260.

The input harmonic matching circuit 241 suppresses harmonics included in the input signal to the gate pads 232a and 232b. The input harmonic matching circuit 241 short-circuits, for example, the impedance of the second harmonic. Similarly, the input harmonic matching circuit 271 suppresses harmonics included in the input signals from the gate pads 262a and 262b. The input harmonic matching circuit 271 short-circuits, for example, the impedance of the second harmonic. The input harmonic matching circuits 241 and 271 can prevent the harmonics from propagating to the output side.

In the present embodiment, the bonding wires 83a and 83b and the harmonic bonding wires 284 extend in a direction in which they intersect in a plan view. Similarly, the bonding wires 93a and 93b and the harmonic bonding wire 294 extend in a direction in which they intersect in a plan view. Therefore, interference due to mutual inductance between the bonding wires 83a and 83b and the harmonic bonding wire 284 and between the bonding wires 93a and 93b and the harmonic bonding wire 294 can be suppressed. Therefore, the frequency dependence of the impedance of the harmonics can be suppressed, and high-efficiency operation can be performed in a wide band.

In the present embodiment, the fourth direction and the second direction and the fourth direction and the third direction are orthogonal to each other. As a result, the effect of suppressing interference due to mutual inductance can be effectively obtained. Not limited to this, the direction in which the bonding wires 83a and 83b extend and the direction in which the harmonic bonding wires 284 extend may be non-parallel. Further, the direction in which the bonding wires 93a and 93b extend and the direction in which the harmonic bonding wires 294 extend may be non-parallel.

In the present embodiment, the second harmonic pad 236 is provided separately from the gate pads 232a and 232b. Further, a second harmonic pad 266 is provided separately from the gate pads 262a and 262b. As a result, interference between the bonding wire for the fundamental wave and the bonding wire for the harmonics can be further suppressed.

Further, in the present embodiment, the second harmonic pads 236 and 266 are formed long in the drain-gate direction. The second harmonic pad 236 projects from the plurality of gate pads 232a and 232b to the side opposite to the side from which the plurality of bonding wires 83a and 83b are drawn out. Similarly, the second harmonic pad 266 projects from the plurality of gate pads 262a and 262b to the side opposite to the side from which the plurality of bonding wires 93a and 93b are drawn out.

The harmonic bonding wire 284 is connected to a portion of the second harmonic pad 236 that protrudes from the plurality of gate pads 232a and 232b. Similarly, the harmonic bonding wire 294 is connected to a portion of the second harmonic pad 266 that protrudes from the plurality of gate pads 262a and 262b. According to such a configuration, the distance between the bonding wire for the fundamental wave and the bonding wire for the harmonics can be secured, and interference can be further suppressed. Further, it is possible to prevent the bonding wire for the fundamental wave and the bonding wire for the harmonic from intersecting with each other. Therefore, wire bonding can be easily performed.

Further, in the present embodiment, only one second harmonic pad 236 and 266 are provided on the transistor chips 230 and 260, respectively. Therefore, the semiconductor device 200 can be miniaturized.

Further, the second harmonic pads 236 and 266 are arranged at the center of the transistor chips 230 and 260, respectively. As a result, the distance between the second harmonic pad and the drain electrode of each FET even when only one second harmonic pad is provided for the plurality of drain pads in each of the transistor chips 230 and 260. The difference can be reduced. Therefore, the difference in impedance of the double wave seen from each FET can be reduced. Therefore, it is possible to reduce the variation in the load impedance of the fundamental wave and the double wave of the plurality of cells and to operate the plurality of cells uniformly. Thereby, the output power, gain and efficiency of the semiconductor device 200 can be improved.

Further, the other of the pair of first sides of the transistor chip 230 of the present embodiment faces the input fundamental wave matching circuit 21. One of the pair of second sides of the transistor chip 230 faces the input harmonic matching circuit 241. The plurality of gate pads 232a and 232b are arranged along the other side of the first side. According to such a configuration, the bonding wires 83a and 83b and the harmonic bonding wires 284 can be easily wired in a non-parallel manner.

Embodiment 3.
FIG. 6 is an equivalent circuit diagram of the semiconductor device 300 according to the third embodiment. The semiconductor device 300 includes a package. The package has two amplifiers 320, 350 inside.

The amplifier 320 includes an input fundamental wave matching circuit 21, a transistor chip 330, an output fundamental wave matching circuit 22, an input harmonic matching circuit 241 and an output harmonic matching circuit 40. A plurality of transistors 331 are formed on the transistor chip 330. The amplifier 320 is different from the first and second embodiments in that it has both the output harmonic matching circuit 40 and the input harmonic matching circuit 241 as matching circuits.

The transistor chip 330 has a drain pad 333. The drain pad 333 and the input end of the output fundamental wave matching circuit 22 are connected by a plurality of bonding wires 81. Further, the transistor chip 330 has a first harmonic pad 335. The first harmonic pad 335 and the input end of the output harmonic matching circuit 40 are connected by a harmonic bonding wire 82. The output end of the output harmonic matching circuit 40 is electrically connected to the grounding pattern.

Further, the transistor chip 330 has a gate pad 332. The gate pad 232 and the output end of the input fundamental wave matching circuit 21 are connected by a plurality of bonding wires 83. Further, the transistor chip 330 has a second harmonic pad 336. The second harmonic pad 336 and the input end of the input harmonic matching circuit 241 are connected by a harmonic bonding wire 284. The output end of the input harmonic matching circuit 241 is electrically connected to the grounding pattern.

The amplifier 350 includes an input fundamental wave matching circuit 51, a transistor chip 360, an output fundamental wave matching circuit 52, an input harmonic matching circuit 271 and an output harmonic matching circuit 70. A plurality of transistors 361 are formed on the transistor chip 360. The amplifier 350 differs from the first and second embodiments in that it has both an output harmonic matching circuit 70 and an input harmonic matching circuit 271 as matching circuits.

The transistor chip 360 has a drain pad 363. The drain pad 363 and the input end of the output fundamental wave matching circuit 52 are connected by a plurality of bonding wires 91. Further, the transistor chip 360 has a first harmonic pad 365. The first harmonic pad 365 and the input end of the output harmonic matching circuit 70 are connected by a harmonic bonding wire 92. The output end of the output harmonic matching circuit 70 is electrically connected to the grounding pattern.

Further, the transistor chip 330 has a gate pad 362. The gate pad 362 and the output end of the input fundamental wave matching circuit 51 are connected by a plurality of bonding wires 93. Further, the transistor chip 360 has a second harmonic pad 366. The second harmonic pad 366 and the input end of the input harmonic matching circuit 271 are connected by a harmonic bonding wire 294. The output end of the input harmonic matching circuit 271 is electrically connected to the grounding pattern.

FIG. 7 is a diagram illustrating configurations on the input side and the output side of the transistor chips 330 and 360 according to the third embodiment. The transistor chip 330 has a substrate 334. Gate pads 332a, 332b, drain pads 333a, 333b, first harmonic pads 335, and second harmonic pads 336 are provided on the upper surface of the substrate 334.

The plurality of bonding wires 81a and 81b connect the plurality of drain pads 333a and 333b and the output fundamental wave matching circuit 22, respectively. The plurality of bonding wires 83a and 83b connect the plurality of gate pads 332a and 332b and the input fundamental wave matching circuit 21, respectively.

A first harmonic pad 335 is provided between the plurality of drain pads 333a and 333b. A second harmonic pad 336 is provided between the plurality of gate pads 332a and 332b. The harmonic bonding wire 82 connects the first harmonic pad 335 and the output harmonic matching circuit 40. The harmonic bonding wire 82 extends in the third direction. The harmonic bonding wire 284 connects the second harmonic pad 336 and the input harmonic matching circuit 241. The harmonic bonding wire 284 extends in the second direction.

The transistor chip 360 has a substrate 364. Gate pads 362a, 362b, drain pads 363a, 363b, first harmonic pad 365, and second harmonic pad 366 are provided on the upper surface of the substrate 364.

The plurality of bonding wires 91a and 91b connect the plurality of drain pads 363a and 363b and the output fundamental wave matching circuit 52, respectively. The plurality of bonding wires 93a and 93b connect the plurality of gate pads 362a and 362b and the input fundamental wave matching circuit 51, respectively.

A first harmonic pad 365 is provided between the plurality of drain pads 363a and 363b. A second harmonic pad 266 is provided between the plurality of gate pads 362a and 362b. The harmonic bonding wire 92 connects the first harmonic pad 365 and the output harmonic matching circuit 70. The harmonic bonding wire 92 extends in the second direction. The harmonic bonding wire 294 connects the second harmonic pad 366 and the input harmonic matching circuit 271. The harmonic bonding wire 294 extends in the third direction.

In the present embodiment, interference between the fundamental wave bonding wire and the harmonic bonding wire can be further suppressed on both the input side and the output side of the transistor chip. Therefore, the frequency dependence of the impedance of the harmonics can be further suppressed, and high-efficiency operation can be performed in a wide band.

In the present embodiment, the harmonic bonding wire 82 and the harmonic bonding wire 284 extend from the transistor chip 330 in opposite directions. Similarly, the harmonic bonding wire 92 and the harmonic bonding wire 294 extend in opposite directions from the transistor chip 360. As a result, interference between the harmonic bonding wires can be suppressed.

The arrangement of the harmonic bonding wires 82, 284, 92, 294 is not limited to this. The harmonic bonding wires 82 and 284 may be drawn from the same side of the transistor chip 330. Similarly, the harmonic bonding wires 92 and 294 may be drawn from the same side of the transistor chip 360. Further, the harmonic bonding wires 82 and 284 may extend non-parallel to each other. Similarly, the harmonic bonding wires 92 and 294 may extend non-parallel to each other.

Further, the bonding wires 81a and 81b and the bonding wires 83a and 83b extend from the transistor chip 330 in opposite directions. The direction in which the bonding wires 81a and 81b and the bonding wires 83a and 83b extend is not limited to this. Similarly, the directions in which the bonding wires 91a and 91b and the bonding wires 93a and 93b extend are not limited to those shown in FIG. Further, the arrangement of the pads or bonding wires may be different between the transistor chip 330 and the transistor chip 360.

The technical features described in each embodiment may be used in combination as appropriate.

10 input terminal, 11 input power distribution circuit, 12 output power synthesis circuit, 13 output terminal, 20 amplifier, 21 input fundamental wave matching circuit, 22 output fundamental wave matching circuit, 30 transistor chip, 31 transistor, 32, 32a, 32b gate Pad, 33, 33a, 33b Drain pad, 34 board, 35 1st harmonic pad, 40 output harmonic matching circuit, 50 amplifier, 51 input fundamental wave matching circuit, 52 output fundamental wave matching circuit, 60 transistor chip, 61 Transistor, 62, 62a, 62b Gate pad, 63, 63a, 63b Drain pad, 64 board, 65 1st harmonic pad, 70 output harmonic matching circuit, 81, 81a, 81b bonding wire, 82 harmonic bonding wire , 83, 83a, 83b Bonding Wire, 91, 91a, 91b Bonding Wire, 92 Harmonic Bonding Wire, 93, 93a, 93b Bonding Wire, 100, 101 Semiconductor Equipment, 130 Transistor Chips, 133a, 133b Drain Pads, 140a, 140b output harmonic matching circuit, 160 transistor chip, 163a, 163b drain pad, 170a, 170b output harmonic matching circuit, 182a, 182b, 192a, 192b bonding wire, 200 semiconductor device, 220 amplifier, 230 transistor chip, 231 transistor, 232, 232a, 232b gate pad, 233, 233a, 233b drain pad, 234 board, 236 second harmonic pad, 241 input harmonic matching circuit, 250 amplifier, 260 transistor chip, 261 transistor, 262, 262a, 262b gate Pad, 263, 263a, 263b Drain pad, 264 board, 266 second harmonic pad, 271 input harmonic matching circuit, 284, 294 harmonic bonding wire, 300 semiconductor device, 320 amplifier, 330 transistor chip, 331 transistor , 332, 332a, 332b Gate pad, 333, 333a, 333b Drain pad, 334 substrate, 335 1st harmonic pad, 336 2nd harmonic pad, 350 Amplifier, 360 transistor chip, 361 transistor, 362, 362a, 362b gate pad, 363, 363a, 363b drain pad, 364 board, 365 first harmonic pad, 366 second harmonic pad

Claims (9)

A transistor chip having a plurality of first pads for inputting or outputting signals, and a first harmonic pad provided between the plurality of first pads and electrically connected to the plurality of first pads. ,
A first fundamental wave matching circuit that matches the signal to the fundamental wave,
A plurality of first bonding wires extending in each of the first directions and connecting the plurality of first pads and the first fundamental wave matching circuit, respectively.
A first harmonic matching circuit that suppresses the harmonics contained in the signal,
A first harmonic bonding wire extending in a second direction non-parallel to the first direction and connecting the first harmonic pad and the first harmonic matching circuit.
A semiconductor device characterized by comprising. The semiconductor device according to claim 1, wherein the first direction and the second direction are orthogonal to each other. The semiconductor device according to claim 1 or 2, wherein the first harmonic pad is provided at the center of the transistor chip in the direction in which the plurality of first pads are arranged. The first harmonic pad projects from the plurality of first pads to the side opposite to the side from which the plurality of first bonding wires are drawn out.
The first harmonic bonding wire according to any one of claims 1 to 3, wherein the first harmonic bonding wire is connected to a portion of the first harmonic pad that protrudes from the plurality of first pads. Semiconductor device. The semiconductor device according to any one of claims 1 to 4, wherein only one first harmonic pad is provided on the transistor chip. The transistor chip has a first side and second sides provided on both sides of the first side.
The plurality of first pads are arranged along the first side,
The first fundamental wave matching circuit faces the first side and
The semiconductor device according to any one of claims 1 to 5, wherein the first harmonic matching circuit faces one of the second sides. A second fundamental wave matching circuit that matches the output signal from the transistor chip with the fundamental wave,
With multiple second bonding wires,
A second harmonic matching circuit that suppresses the harmonics contained in the output signal,
Bonding wire for second harmonic and
With
The signal is input to the plurality of first pads, and the signal is input to the plurality of first pads.
The transistor chip has a plurality of second pads and a second harmonic pad provided between the plurality of second pads and electrically connected to the plurality of second pads, and the signal. Amplifies and outputs the output signal from the plurality of second pads.
The plurality of second bonding wires extend in the third direction, respectively, and connect the plurality of second pads and the second fundamental wave matching circuit, respectively.
The second harmonic bonding wire extends in a fourth direction non-parallel to the third direction, and connects the second harmonic pad and the second harmonic matching circuit. The semiconductor device according to any one of 1 to 6. The semiconductor device according to claim 7, wherein the first harmonic bonding wire and the second harmonic bonding wire extend in opposite directions to each other. The semiconductor device according to any one of claims 1 to 8, wherein the transistor chip is one of a carrier amplifier and a peak amplifier among Doherty amplifiers.

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